git.gag.com Git - fw/altos/blob - src/samd21/ao_timer.c

   1 /*
   2  * Copyright © 2019 Keith Packard <keithp@keithp.com>
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation, either version 2 of the License, or
   7  * (at your option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful, but
  10  * WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  12  * General Public License for more details.
  13  */
  14
  15 #include <ao.h>
  16
  17 #ifndef HAS_TICK
  18 #define HAS_TICK 1
  19 #endif
  20
  21 #if HAS_TICK
  22 volatile AO_TICK_TYPE ao_tick_count;
  23
  24 AO_TICK_TYPE
  25 ao_time(void)
  26 {
  27         return ao_tick_count;
  28 }
  29
  30 uint64_t
  31 ao_time_ns(void)
  32 {
  33         AO_TICK_TYPE    before, after;
  34         uint32_t        cvr;
  35
  36         do {
  37                 before = ao_tick_count;
  38                 cvr = samd21_systick.cvr;
  39                 after = ao_tick_count;
  40         } while (before != after);
  41
  42         return (uint64_t) after * (1000000000ULL / AO_HERTZ) +
  43                 (uint64_t) cvr * (1000000000ULL / AO_SYSTICK);
  44 }
  45
  46 #if AO_DATA_ALL
  47 volatile uint8_t        ao_data_interval = 1;
  48 volatile uint8_t        ao_data_count;
  49 #endif
  50
  51 void samd21_systick_isr(void)
  52 {
  53         ao_arch_release_interrupts();
  54         if (samd21_systick.csr & (1 << SAMD21_SYSTICK_CSR_COUNTFLAG)) {
  55                 ++ao_tick_count;
  56                 ao_task_check_alarm();
  57 #if AO_DATA_ALL
  58                 if (++ao_data_count == ao_data_interval && ao_data_interval) {
  59                         ao_data_count = 0;
  60 #if HAS_FAKE_FLIGHT
  61                         if (ao_fake_flight_active)
  62                                 ao_fake_flight_poll();
  63                         else
  64 #endif
  65                                 ao_adc_poll();
  66 #if (AO_DATA_ALL & ~(AO_DATA_ADC))
  67                         ao_wakeup((void *) &ao_data_count);
  68 #endif
  69                 }
  70 #endif
  71 #ifdef AO_TIMER_HOOK
  72                 AO_TIMER_HOOK;
  73 #endif
  74         }
  75 }
  76
  77 #if HAS_ADC
  78 void
  79 ao_timer_set_adc_interval(uint8_t interval)
  80 {
  81         ao_arch_critical(
  82                 ao_data_interval = interval;
  83                 ao_data_count = 0;
  84                 );
  85 }
  86 #endif
  87
  88 #define SYSTICK_RELOAD (AO_SYSTICK / AO_HERTZ - 1)
  89
  90 void
  91 ao_timer_init(void)
  92 {
  93         samd21_systick.csr = 0;
  94         samd21_systick.rvr = SYSTICK_RELOAD;
  95         samd21_systick.cvr = 0;
  96         samd21_systick.csr = ((1 << SAMD21_SYSTICK_CSR_ENABLE) |
  97                            (1 << SAMD21_SYSTICK_CSR_TICKINT) |
  98                            (SAMD21_SYSTICK_CSR_CLKSOURCE_HCLK_8 << SAMD21_SYSTICK_CSR_CLKSOURCE));
  99         /* Set clock to lowest priority */
 100         samd21_scb.shpr3 |= 3UL << 30;
 101 }
 102
 103 #endif
 104
 105
 106 void
 107 ao_clock_init(void)
 108 {
 109         /* Set flash wait state to tolerate 48MHz */
 110         samd21_nvmctrl.ctrlb |= (1 << SAMD21_NVMCTRL_CTRLB_RWS);
 111
 112         samd21_pm.apbamask |= ((1 << SAMD21_PM_APBAMASK_GCLK) |
 113                                (1 << SAMD21_PM_APBAMASK_SYSCTRL));
 114
 115         /* Reset gclk */
 116         samd21_gclk.ctrl = (1 << SAMD21_GCLK_CTRL_SWRST)
 117                 ;
 118
 119         /* Wait for reset to complete */
 120         while ((samd21_gclk.ctrl & (1 << SAMD21_GCLK_CTRL_SWRST)) &&
 121                (samd21_gclk.status & (1 << SAMD21_GCLK_STATUS_SYNCBUSY)))
 122                 ;
 123
 124 #ifdef AO_XOSC
 125         /* Enable xosc (external xtal oscillator) */
 126         samd21_sysctrl.xosc = ((SAMD21_SYSCTRL_XOSC_STARTUP_8192 << SAMD21_SYSCTRL_XOSC_STARTUP) |
 127                                (0 << SAMD21_SYSCTRL_XOSC_AMPGC) |
 128                                (SAMD21_SYSCTRL_XOSC_GAIN_16MHz << SAMD21_SYSCTRL_XOSC_GAIN) |
 129                                (0 << SAMD21_SYSCTRL_XOSC_ONDEMAND) |
 130                                (1 << SAMD21_SYSCTRL_XOSC_RUNSTDBY) |
 131                                (1 << SAMD21_SYSCTRL_XOSC_XTALEN));
 132         samd21_sysctrl.xosc |= ((1 << SAMD21_SYSCTRL_XOSC_ENABLE));
 133
 134         /* Wait for xosc */
 135         while ((samd21_sysctrl.pclksr & (1 << SAMD21_SYSCTRL_PCLKSR_XOSCRDY)) == 0)
 136                 ;
 137
 138         /* program DPLL */
 139
 140         /* Divide down */
 141         samd21_sysctrl.dpllctrlb = (((AO_XOSC_DIV/2 - 1) << SAMD21_SYSCTRL_DPLLCTRLB_DIV) |
 142                                     (0 << SAMD21_SYSCTRL_DPLLCTRLB_LBYPASS) |
 143                                     (SAMD21_SYSCTRL_DPLLCTRLB_LTIME_DEFAULT << SAMD21_SYSCTRL_DPLLCTRLB_LTIME) |
 144                                     (SAMD21_SYSCTRL_DPLLCTRLB_REFCLK_XOSC << SAMD21_SYSCTRL_DPLLCTRLB_REFCLK) |
 145                                     (0 << SAMD21_SYSCTRL_DPLLCTRLB_WUF) |
 146                                     (1 << SAMD21_SYSCTRL_DPLLCTRLB_LPEN) |
 147                                     (SAMD21_SYSCTRL_DPLLCTRLB_FILTER_DEFAULT << SAMD21_SYSCTRL_DPLLCTRLB_FILTER));
 148
 149         /* Multiply up */
 150         samd21_sysctrl.dpllratio = ((AO_XOSC_MUL - 1) << SAMD21_SYSCTRL_DPLLRATIO_LDR);
 151
 152         /* Always on in run mode, off in standby mode */
 153         samd21_sysctrl.dpllctrla = ((0 << SAMD21_SYSCTRL_DPLLCTRLA_ONDEMAND) |
 154                                     (0 << SAMD21_SYSCTRL_DPLLCTRLA_RUNSTDBY));
 155
 156         /* Enable DPLL */
 157         samd21_sysctrl.dpllctrla |= (1 << SAMD21_SYSCTRL_DPLLCTRLA_ENABLE);
 158
 159         /* Wait for the DPLL to be enabled */
 160         while ((samd21_sysctrl.dpllstatus & (1 << SAMD21_SYSCTRL_DPLLSTATUS_ENABLE)) == 0)
 161                 ;
 162
 163         /* Wait for the DPLL to be ready */
 164         while ((samd21_sysctrl.dpllstatus & (1 << SAMD21_SYSCTRL_DPLLSTATUS_CLKRDY)) == 0)
 165                 ;
 166
 167         samd21_gclk_wait_sync();
 168
 169         /*
 170          * Switch generator 0 (CPU clock) to DPLL
 171          */
 172
 173         /* divide by 1 */
 174         samd21_gclk_gendiv(AO_GCLK_SYSCLK, AO_XOSC_GCLK_DIV);
 175
 176         /* select DPLL as source */
 177         samd21_gclk_genctrl(SAMD21_GCLK_GENCTRL_SRC_FDPLL96M, AO_GCLK_FDPLL96M);
 178 #endif
 179
 180 #ifdef AO_DFLL48M
 181
 182         /*
 183          * Enable DFLL48M clock
 184          */
 185
 186         samd21_sysctrl.dfllctrl = (1 << SAMD21_SYSCTRL_DFLLCTRL_ENABLE);
 187         samd21_dfll_wait_sync();
 188
 189 #ifdef AO_XOSC32K
 190 #define AO_GCLK_XOSC32K 1
 191
 192         /* Enable xosc32k (external 32.768kHz oscillator) */
 193         samd21_sysctrl.xosc32k = ((6 << SAMD21_SYSCTRL_XOSC32K_STARTUP) |
 194                                   (1 << SAMD21_SYSCTRL_XOSC32K_XTALEN) |
 195                                   (1 << SAMD21_SYSCTRL_XOSC32K_EN32K));
 196
 197         /* requires separate store */
 198         samd21_sysctrl.xosc32k |= (1 << SAMD21_SYSCTRL_XOSC32K_ENABLE);
 199
 200         /* Wait for osc */
 201         while ((samd21_sysctrl.pclksr & (1 << SAMD21_SYSCTRL_PCLKSR_XOSC32KRDY)) == 0)
 202                 ;
 203
 204         /*
 205          * Use xosc32k as source of gclk generator AO_GCLK_XOSC32K
 206          */
 207
 208         samd21_gclk_gendiv(AO_GCLK_XOSC32K, 1);
 209         samd21_gclk_genctrl(SAMD21_GCLK_GENCTRL_SRC_XOSC32K, AO_GCLK_XOSC32K);
 210
 211         /*
 212          * Use generator as source for dfm48m reference
 213          */
 214
 215         samd21_gclk_clkctrl(AO_GCLK_XOSC32K, SAMD21_GCLK_CLKCTRL_ID_DFLL48M_REF);
 216
 217         /* Set multiplier to get as close to 48MHz as we can without going over */
 218         samd21_sysctrl.dfllmul = (((31/4) << SAMD21_SYSCTRL_DFLLMUL_CSTEP) |
 219                                   ((255/4) << SAMD21_SYSCTRL_DFLLMUL_FSTEP) |
 220                                   ((AO_DFLL48M / AO_XOSC32K) << SAMD21_SYSCTRL_DFLLMUL_MUL));
 221
 222         /* pull out coarse calibration value from rom */
 223         uint32_t coarse = ((samd21_aux1.calibration >> SAMD21_AUX1_CALIBRATION_DFLL48M_COARSE_CAL) &
 224                            SAMD21_AUX1_CALIBRATION_DFLL48M_COARSE_CAL_MASK);
 225
 226         samd21_sysctrl.dfllval = ((coarse << SAMD21_SYSCTRL_DFLLVAL_COARSE) |
 227                                   (512 << SAMD21_SYSCTRL_DFLLVAL_FINE));
 228
 229         samd21_sysctrl.dfllctrl = 0;
 230         samd21_dfll_wait_sync();
 231
 232         samd21_sysctrl.dfllctrl = ((1 << SAMD21_SYSCTRL_DFLLCTRL_MODE) |
 233                                    (1 << SAMD21_SYSCTRL_DFLLCTRL_ENABLE));
 234
 235         samd21_dfll_wait_sync();
 236         samd21_gclk_wait_sync();
 237
 238         /* wait for fine lock */
 239         while ((samd21_sysctrl.pclksr & (1 << SAMD21_SYSCTRL_PCLKSR_DFLLLCKC)) == 0 ||
 240                (samd21_sysctrl.pclksr & (1 << SAMD21_SYSCTRL_PCLKSR_DFLLLCKF)) == 0)
 241                 ;
 242 #else
 243         samd21_sysctrl.dfllmul = (((31/4) << SAMD21_SYSCTRL_DFLLMUL_CSTEP) |
 244                                   ((255/4) << SAMD21_SYSCTRL_DFLLMUL_FSTEP) |
 245                                   ((AO_DFLL48M / 1000) << SAMD21_SYSCTRL_DFLLMUL_MUL));
 246
 247         /* pull out coarse calibration value from rom */
 248         uint32_t coarse = ((samd21_aux1.calibration >> SAMD21_AUX1_CALIBRATION_DFLL48M_COARSE_CAL) &
 249                            SAMD21_AUX1_CALIBRATION_DFLL48M_COARSE_CAL_MASK);
 250
 251         samd21_sysctrl.dfllval = ((coarse << SAMD21_SYSCTRL_DFLLVAL_COARSE) |
 252                                   (512 << SAMD21_SYSCTRL_DFLLVAL_FINE));
 253
 254         samd21_sysctrl.dfllctrl = 0;
 255         samd21_dfll_wait_sync();
 256
 257         samd21_sysctrl.dfllctrl = ((1 << SAMD21_SYSCTRL_DFLLCTRL_MODE) |
 258                                    (1 << SAMD21_SYSCTRL_DFLLCTRL_BPLCKC) |
 259                                    (1 << SAMD21_SYSCTRL_DFLLCTRL_CCDIS) |
 260                                    (1 << SAMD21_SYSCTRL_DFLLCTRL_USBCRM) |
 261                                    (1 << SAMD21_SYSCTRL_DFLLCTRL_ENABLE));
 262
 263         samd21_dfll_wait_sync();
 264         samd21_gclk_wait_sync();
 265 #endif
 266
 267         /*
 268          * Switch generator to DFLL48M
 269          */
 270
 271         /* divide by 1 */
 272         samd21_gclk_gendiv(AO_GCLK_SYSCLK, 1);
 273
 274         /* select DFLL48M as source */
 275         samd21_gclk_genctrl(SAMD21_GCLK_GENCTRL_SRC_DFLL48M, AO_GCLK_DFLL48M);
 276 #endif
 277
 278         /* Set up all of the clocks to be /1 */
 279
 280         samd21_pm.cpusel = ((0 << SAMD21_PM_CPUSEL_CPUDIV));
 281         samd21_pm.apbasel = ((0 << SAMD21_PM_APBASEL_APBADIV));
 282         samd21_pm.apbbsel = ((0 << SAMD21_PM_APBBSEL_APBBDIV));
 283         samd21_pm.apbcsel = ((0 << SAMD21_PM_APBCSEL_APBCDIV));
 284
 285         /* Disable OSC8M */
 286         samd21_sysctrl.osc8m &= ~(1UL << SAMD21_SYSCTRL_OSC8M_ENABLE);
 287
 288         /* Additional misc configuration stuff */
 289
 290         /* Disable automatic NVM write operations */
 291         samd21_nvmctrl.ctrlb |= (1UL << SAMD21_NVMCTRL_CTRLB_MANW);
 292 }