git.gag.com Git - fw/altos/blob - src/samd21/ao_timer.c

   1 /*
   2  * Copyright © 2019 Keith Packard <keithp@keithp.com>
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation, either version 2 of the License, or
   7  * (at your option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful, but
  10  * WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  12  * General Public License for more details.
  13  */
  14
  15 #include <ao.h>
  16
  17 #ifndef HAS_TICK
  18 #define HAS_TICK 1
  19 #endif
  20
  21 #if HAS_TICK
  22 volatile AO_TICK_TYPE ao_tick_count;
  23
  24 AO_TICK_TYPE
  25 ao_time(void)
  26 {
  27         return ao_tick_count;
  28 }
  29
  30 uint64_t
  31 ao_time_ns(void)
  32 {
  33         AO_TICK_TYPE    before, after;
  34         uint32_t        cvr;
  35
  36         do {
  37                 before = ao_tick_count;
  38                 cvr = samd21_systick.cvr;
  39                 after = ao_tick_count;
  40         } while (before != after);
  41
  42         return (uint64_t) after * (1000000000ULL / AO_HERTZ) +
  43                 (uint64_t) cvr * (1000000000ULL / AO_SYSTICK);
  44 }
  45
  46 #if AO_DATA_ALL
  47 volatile uint8_t        ao_data_interval = 1;
  48 volatile uint8_t        ao_data_count;
  49 #endif
  50
  51 void samd21_systick_isr(void)
  52 {
  53         ao_arch_release_interrupts();
  54         if (samd21_systick.csr & (1 << SAMD21_SYSTICK_CSR_COUNTFLAG)) {
  55                 ++ao_tick_count;
  56 #ifdef AO_TIMER_HOOK
  57                 AO_TIMER_HOOK;
  58 #endif
  59         }
  60 }
  61
  62 #if HAS_ADC
  63 void
  64 ao_timer_set_adc_interval(uint8_t interval)
  65 {
  66         ao_arch_critical(
  67                 ao_data_interval = interval;
  68                 ao_data_count = 0;
  69                 );
  70 }
  71 #endif
  72
  73 #define SYSTICK_RELOAD (AO_SYSTICK / AO_HERTZ - 1)
  74
  75 void
  76 ao_timer_init(void)
  77 {
  78         samd21_systick.csr = 0;
  79         samd21_systick.rvr = SYSTICK_RELOAD;
  80         samd21_systick.cvr = 0;
  81         samd21_systick.csr = ((1 << SAMD21_SYSTICK_CSR_ENABLE) |
  82                            (1 << SAMD21_SYSTICK_CSR_TICKINT) |
  83                            (SAMD21_SYSTICK_CSR_CLKSOURCE_HCLK_8 << SAMD21_SYSTICK_CSR_CLKSOURCE));
  84         /* Set clock to lowest priority */
  85         samd21_scb.shpr3 |= 3UL << 30;
  86 }
  87
  88 #endif
  89
  90
  91 void
  92 ao_clock_init(void)
  93 {
  94         /* Set flash wait state to tolerate 48MHz */
  95         samd21_nvmctrl.ctrlb |= (1 << SAMD21_NVMCTRL_CTRLB_RWS);
  96
  97         samd21_pm.apbamask |= ((1 << SAMD21_PM_APBAMASK_GCLK) |
  98                                (1 << SAMD21_PM_APBAMASK_SYSCTRL));
  99
 100         /* Reset gclk */
 101         samd21_gclk.ctrl = (1 << SAMD21_GCLK_CTRL_SWRST)
 102                 ;
 103
 104         /* Wait for reset to complete */
 105         while ((samd21_gclk.ctrl & (1 << SAMD21_GCLK_CTRL_SWRST)) &&
 106                (samd21_gclk.status & (1 << SAMD21_GCLK_STATUS_SYNCBUSY)))
 107                 ;
 108
 109 #ifdef AO_XOSC
 110         /* Enable xosc (external xtal oscillator) */
 111         samd21_sysctrl.xosc = ((SAMD21_SYSCTRL_XOSC_STARTUP_8192 << SAMD21_SYSCTRL_XOSC_STARTUP) |
 112                                (0 << SAMD21_SYSCTRL_XOSC_AMPGC) |
 113                                (SAMD21_SYSCTRL_XOSC_GAIN_16MHz << SAMD21_SYSCTRL_XOSC_GAIN) |
 114                                (0 << SAMD21_SYSCTRL_XOSC_ONDEMAND) |
 115                                (1 << SAMD21_SYSCTRL_XOSC_RUNSTDBY) |
 116                                (1 << SAMD21_SYSCTRL_XOSC_XTALEN));
 117         samd21_sysctrl.xosc |= ((1 << SAMD21_SYSCTRL_XOSC_ENABLE));
 118
 119         /* Wait for xosc */
 120         while ((samd21_sysctrl.pclksr & (1 << SAMD21_SYSCTRL_PCLKSR_XOSCRDY)) == 0)
 121                 ;
 122
 123         /* program DPLL */
 124
 125         /* Divide down */
 126         samd21_sysctrl.dpllctrlb = (((AO_XOSC_DIV/2 - 1) << SAMD21_SYSCTRL_DPLLCTRLB_DIV) |
 127                                     (0 << SAMD21_SYSCTRL_DPLLCTRLB_LBYPASS) |
 128                                     (SAMD21_SYSCTRL_DPLLCTRLB_LTIME_DEFAULT << SAMD21_SYSCTRL_DPLLCTRLB_LTIME) |
 129                                     (SAMD21_SYSCTRL_DPLLCTRLB_REFCLK_XOSC << SAMD21_SYSCTRL_DPLLCTRLB_REFCLK) |
 130                                     (0 << SAMD21_SYSCTRL_DPLLCTRLB_WUF) |
 131                                     (1 << SAMD21_SYSCTRL_DPLLCTRLB_LPEN) |
 132                                     (SAMD21_SYSCTRL_DPLLCTRLB_FILTER_DEFAULT << SAMD21_SYSCTRL_DPLLCTRLB_FILTER));
 133
 134         /* Multiply up */
 135         samd21_sysctrl.dpllratio = ((AO_XOSC_MUL - 1) << SAMD21_SYSCTRL_DPLLRATIO_LDR);
 136
 137         /* Always on in run mode, off in standby mode */
 138         samd21_sysctrl.dpllctrla = ((0 << SAMD21_SYSCTRL_DPLLCTRLA_ONDEMAND) |
 139                                     (0 << SAMD21_SYSCTRL_DPLLCTRLA_RUNSTDBY));
 140
 141         /* Enable DPLL */
 142         samd21_sysctrl.dpllctrla |= (1 << SAMD21_SYSCTRL_DPLLCTRLA_ENABLE);
 143
 144         /* Wait for the DPLL to be enabled */
 145         while ((samd21_sysctrl.dpllstatus & (1 << SAMD21_SYSCTRL_DPLLSTATUS_ENABLE)) == 0)
 146                 ;
 147
 148         /* Wait for the DPLL to be ready */
 149         while ((samd21_sysctrl.dpllstatus & (1 << SAMD21_SYSCTRL_DPLLSTATUS_CLKRDY)) == 0)
 150                 ;
 151
 152         samd21_gclk_wait_sync();
 153
 154         /*
 155          * Switch generator 0 (CPU clock) to DPLL
 156          */
 157
 158         /* divide by 1 */
 159         samd21_gclk_gendiv(AO_GCLK_SYSCLK, AO_XOSC_GCLK_DIV);
 160
 161         /* select DPLL as source */
 162         samd21_gclk_genctrl(SAMD21_GCLK_GENCTRL_SRC_FDPLL96M, AO_GCLK_FDPLL96M);
 163 #endif
 164
 165 #ifdef AO_DFLL48M
 166
 167         /*
 168          * Enable DFLL48M clock
 169          */
 170
 171         samd21_sysctrl.dfllctrl = (1 << SAMD21_SYSCTRL_DFLLCTRL_ENABLE);
 172         samd21_dfll_wait_sync();
 173
 174 #ifdef AO_XOSC32K
 175 #define AO_GCLK_XOSC32K 1
 176
 177         /* Enable xosc32k (external 32.768kHz oscillator) */
 178         samd21_sysctrl.xosc32k = ((6 << SAMD21_SYSCTRL_XOSC32K_STARTUP) |
 179                                   (1 << SAMD21_SYSCTRL_XOSC32K_XTALEN) |
 180                                   (1 << SAMD21_SYSCTRL_XOSC32K_EN32K));
 181
 182         /* requires separate store */
 183         samd21_sysctrl.xosc32k |= (1 << SAMD21_SYSCTRL_XOSC32K_ENABLE);
 184
 185         /* Wait for osc */
 186         while ((samd21_sysctrl.pclksr & (1 << SAMD21_SYSCTRL_PCLKSR_XOSC32KRDY)) == 0)
 187                 ;
 188
 189         /*
 190          * Use xosc32k as source of gclk generator AO_GCLK_XOSC32K
 191          */
 192
 193         samd21_gclk_gendiv(AO_GCLK_XOSC32K, 1);
 194         samd21_gclk_genctrl(SAMD21_GCLK_GENCTRL_SRC_XOSC32K, AO_GCLK_XOSC32K);
 195
 196         /*
 197          * Use generator as source for dfm48m reference
 198          */
 199
 200         samd21_gclk_clkctrl(AO_GCLK_XOSC32K, SAMD21_GCLK_CLKCTRL_ID_DFLL48M_REF);
 201
 202         /* Set multiplier to get as close to 48MHz as we can without going over */
 203         samd21_sysctrl.dfllmul = (((31/4) << SAMD21_SYSCTRL_DFLLMUL_CSTEP) |
 204                                   ((255/4) << SAMD21_SYSCTRL_DFLLMUL_FSTEP) |
 205                                   ((AO_DFLL48M / AO_XOSC32K) << SAMD21_SYSCTRL_DFLLMUL_MUL));
 206
 207         /* pull out coarse calibration value from rom */
 208         uint32_t coarse = ((samd21_aux1.calibration >> SAMD21_AUX1_CALIBRATION_DFLL48M_COARSE_CAL) &
 209                            SAMD21_AUX1_CALIBRATION_DFLL48M_COARSE_CAL_MASK);
 210
 211         samd21_sysctrl.dfllval = ((coarse << SAMD21_SYSCTRL_DFLLVAL_COARSE) |
 212                                   (512 << SAMD21_SYSCTRL_DFLLVAL_FINE));
 213
 214         samd21_sysctrl.dfllctrl = 0;
 215         samd21_dfll_wait_sync();
 216
 217         samd21_sysctrl.dfllctrl = ((1 << SAMD21_SYSCTRL_DFLLCTRL_MODE) |
 218                                    (1 << SAMD21_SYSCTRL_DFLLCTRL_ENABLE));
 219
 220         samd21_dfll_wait_sync();
 221         samd21_gclk_wait_sync();
 222
 223         /* wait for fine lock */
 224         while ((samd21_sysctrl.pclksr & (1 << SAMD21_SYSCTRL_PCLKSR_DFLLLCKC)) == 0 ||
 225                (samd21_sysctrl.pclksr & (1 << SAMD21_SYSCTRL_PCLKSR_DFLLLCKF)) == 0)
 226                 ;
 227 #else
 228         samd21_sysctrl.dfllmul = (((31/4) << SAMD21_SYSCTRL_DFLLMUL_CSTEP) |
 229                                   ((255/4) << SAMD21_SYSCTRL_DFLLMUL_FSTEP) |
 230                                   ((AO_DFLL48M / 1000) << SAMD21_SYSCTRL_DFLLMUL_MUL));
 231
 232         /* pull out coarse calibration value from rom */
 233         uint32_t coarse = ((samd21_aux1.calibration >> SAMD21_AUX1_CALIBRATION_DFLL48M_COARSE_CAL) &
 234                            SAMD21_AUX1_CALIBRATION_DFLL48M_COARSE_CAL_MASK);
 235
 236         samd21_sysctrl.dfllval = ((coarse << SAMD21_SYSCTRL_DFLLVAL_COARSE) |
 237                                   (512 << SAMD21_SYSCTRL_DFLLVAL_FINE));
 238
 239         samd21_sysctrl.dfllctrl = 0;
 240         samd21_dfll_wait_sync();
 241
 242         samd21_sysctrl.dfllctrl = ((1 << SAMD21_SYSCTRL_DFLLCTRL_MODE) |
 243                                    (1 << SAMD21_SYSCTRL_DFLLCTRL_BPLCKC) |
 244                                    (1 << SAMD21_SYSCTRL_DFLLCTRL_CCDIS) |
 245                                    (1 << SAMD21_SYSCTRL_DFLLCTRL_USBCRM) |
 246                                    (1 << SAMD21_SYSCTRL_DFLLCTRL_ENABLE));
 247
 248         samd21_dfll_wait_sync();
 249         samd21_gclk_wait_sync();
 250 #endif
 251
 252         /*
 253          * Switch generator to DFLL48M
 254          */
 255
 256         /* divide by 1 */
 257         samd21_gclk_gendiv(AO_GCLK_SYSCLK, 1);
 258
 259         /* select DFLL48M as source */
 260         samd21_gclk_genctrl(SAMD21_GCLK_GENCTRL_SRC_DFLL48M, AO_GCLK_DFLL48M);
 261 #endif
 262
 263         /* Set up all of the clocks to be /1 */
 264
 265         samd21_pm.cpusel = ((0 << SAMD21_PM_CPUSEL_CPUDIV));
 266         samd21_pm.apbasel = ((0 << SAMD21_PM_APBASEL_APBADIV));
 267         samd21_pm.apbbsel = ((0 << SAMD21_PM_APBBSEL_APBBDIV));
 268         samd21_pm.apbcsel = ((0 << SAMD21_PM_APBCSEL_APBCDIV));
 269
 270         /* Disable OSC8M */
 271         samd21_sysctrl.osc8m &= ~(1UL << SAMD21_SYSCTRL_OSC8M_ENABLE);
 272
 273         /* Additional misc configuration stuff */
 274
 275         /* Disable automatic NVM write operations */
 276         samd21_nvmctrl.ctrlb |= (1UL << SAMD21_NVMCTRL_CTRLB_MANW);
 277 }