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   1 /*
   2  * Copyright © 2022 Keith Packard <keithp@keithp.com>
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation, either version 2 of the License, or
   7  * (at your option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful, but
  10  * WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  12  * General Public License for more details.
  13  */
  14
  15 #include <ao.h>
  16 #include <ao_dma_samd21.h>
  17
  18 static uint8_t          ao_spi_mutex[SAMD21_NUM_SERCOM];
  19 static uint16_t         ao_spi_pin_config[SAMD21_NUM_SERCOM];
  20
  21 #define SPI_DEBUG       0
  22 #define SPI_USE_DMA     1
  23
  24 /*
  25  * DMA is only used for USARTs in altos, which makes assigning DMA IDs
  26  * pretty easy
  27  */
  28
  29 #define MISO_DMA_ID(id)         ((uint8_t) ((id) * 2U + 0U))
  30 #define MOSI_DMA_ID(id)         ((uint8_t) ((id) * 2U + 1U))
  31
  32 struct ao_spi_samd21_info {
  33         struct samd21_sercom    *sercom;
  34 };
  35
  36 static const struct ao_spi_samd21_info ao_spi_samd21_info[SAMD21_NUM_SERCOM] = {
  37         {
  38                 .sercom = &samd21_sercom0,
  39         },
  40         {
  41                 .sercom = &samd21_sercom1,
  42         },
  43         {
  44                 .sercom = &samd21_sercom2,
  45         },
  46         {
  47                 .sercom = &samd21_sercom3,
  48         },
  49         {
  50                 .sercom = &samd21_sercom4,
  51         },
  52         {
  53                 .sercom = &samd21_sercom5,
  54         },
  55 };
  56
  57 static uint8_t  spi_dev_null;
  58
  59 #if SPI_USE_DMA
  60
  61 static uint8_t  ao_spi_done[SAMD21_NUM_SERCOM];
  62
  63 static void
  64 _ao_spi_recv_dma_done(uint8_t dma_id, void *closure)
  65 {
  66         uint8_t id = (uint8_t) (uintptr_t) closure;
  67
  68         (void) dma_id;
  69         ao_spi_done[id] = 1;
  70         ao_wakeup(&ao_spi_done[id]);
  71 }
  72
  73 static inline uint32_t
  74 dma_chctrlb(uint8_t id, bool tx)
  75 {
  76         uint32_t        chctrlb = 0;
  77
  78         /* No complicated actions needed */
  79         chctrlb |= SAMD21_DMAC_CHCTRLB_CMD_NOACT << SAMD21_DMAC_CHCTRLB_CMD;
  80
  81         /* Trigger after each byte transferred */
  82         chctrlb |= SAMD21_DMAC_CHCTRLB_TRIGACT_BEAT << SAMD21_DMAC_CHCTRLB_TRIGACT;
  83
  84         /* Set the trigger source */
  85         if (tx)
  86                 chctrlb |= SAMD21_DMAC_CHCTRLB_TRIGSRC_SERCOM_TX(id) << SAMD21_DMAC_CHCTRLB_TRIGSRC;
  87         else
  88                 chctrlb |= SAMD21_DMAC_CHCTRLB_TRIGSRC_SERCOM_RX(id) << SAMD21_DMAC_CHCTRLB_TRIGSRC;
  89
  90         /* RX has priority over TX so that we don't drop incoming bytes */
  91         if (tx)
  92                 chctrlb |= SAMD21_DMAC_CHCTRLB_LVL_LVL0 << SAMD21_DMAC_CHCTRLB_LVL;
  93         else
  94                 chctrlb |= SAMD21_DMAC_CHCTRLB_LVL_LVL3 << SAMD21_DMAC_CHCTRLB_LVL;
  95
  96         /* No events needed */
  97         chctrlb |= 0UL << SAMD21_DMAC_CHCTRLB_EVOE;
  98         chctrlb |= 0UL << SAMD21_DMAC_CHCTRLB_EVIE;
  99
 100         /* And no actions either */
 101         chctrlb |= SAMD21_DMAC_CHCTRLB_EVACT_NOACT << SAMD21_DMAC_CHCTRLB_EVACT;
 102
 103         return chctrlb;
 104 }
 105
 106 static inline uint16_t
 107 dma_btctrl(bool step, bool tx)
 108 {
 109         uint16_t        btctrl = 0;
 110
 111         /* Always step by 1 */
 112         btctrl |= SAMD21_DMAC_DESC_BTCTRL_STEPSIZE_X1 << SAMD21_DMAC_DESC_BTCTRL_STEPSIZE;
 113
 114         /* Step the source if transmit, otherwise step the dest */
 115         if (tx)
 116                 btctrl |= SAMD21_DMAC_DESC_BTCTRL_STEPSEL_SRC << SAMD21_DMAC_DESC_BTCTRL_STEPSEL;
 117         else
 118                 btctrl |= SAMD21_DMAC_DESC_BTCTRL_STEPSEL_DST << SAMD21_DMAC_DESC_BTCTRL_STEPSEL;
 119
 120         /* Set the increment if stepping */
 121         if (tx) {
 122                 if (step)
 123                         btctrl |= 1UL << SAMD21_DMAC_DESC_BTCTRL_SRCINC;
 124                 else
 125                         btctrl |= 0UL << SAMD21_DMAC_DESC_BTCTRL_SRCINC;
 126                 btctrl |= 0UL << SAMD21_DMAC_DESC_BTCTRL_DSTINC;
 127         } else {
 128                 btctrl |= 0UL << SAMD21_DMAC_DESC_BTCTRL_SRCINC;
 129                 if (step)
 130                         btctrl |= 1UL << SAMD21_DMAC_DESC_BTCTRL_DSTINC;
 131                 else
 132                         btctrl |= 0UL << SAMD21_DMAC_DESC_BTCTRL_DSTINC;
 133         }
 134
 135         /* byte at a time please */
 136         btctrl |= SAMD21_DMAC_DESC_BTCTRL_BEATSIZE_BYTE << SAMD21_DMAC_DESC_BTCTRL_BEATSIZE;
 137
 138         /*
 139          * Watch for interrupts on RX -- we need to wait for the last byte to get received
 140          * to know the SPI bus is idle
 141          */
 142         if (tx)
 143                 btctrl |= SAMD21_DMAC_DESC_BTCTRL_BLOCKACT_NOACT << SAMD21_DMAC_DESC_BTCTRL_BLOCKACT;
 144         else
 145                 btctrl |= SAMD21_DMAC_DESC_BTCTRL_BLOCKACT_INT << SAMD21_DMAC_DESC_BTCTRL_BLOCKACT;
 146
 147         /* don't need any events */
 148         btctrl |= SAMD21_DMAC_DESC_BTCTRL_EVOSEL_DISABLE << SAMD21_DMAC_DESC_BTCTRL_EVOSEL;
 149
 150         /* And make the descriptor valid */
 151         btctrl |= 1UL << SAMD21_DMAC_DESC_BTCTRL_VALID;
 152
 153         return btctrl;
 154 }
 155
 156 static void
 157 spi_run(const void *out, void *in, uint16_t len, uint16_t spi_index, bool step_out, bool step_in)
 158 {
 159         const uint8_t           *o = out;
 160         uint8_t                 *i = in;
 161         uint8_t                 id = AO_SPI_INDEX(spi_index);
 162         struct samd21_sercom    *sercom = ao_spi_samd21_info[id].sercom;
 163
 164         ao_arch_block_interrupts();
 165         ao_spi_done[id] = 0;
 166
 167         /*
 168          * Stepped addresses to the DMA engine point past the end of
 169          * the block
 170          */
 171         if (step_out)
 172                 o += len;
 173         if (step_in)
 174                 i += len;
 175
 176         /* read any stuck data */
 177         (void) sercom->data;
 178
 179         _ao_dma_start_transfer(MISO_DMA_ID(id),
 180                                (void *) &sercom->data,
 181                                i,
 182                                len,
 183                                dma_chctrlb(id, false),
 184                                dma_btctrl(step_in, false),
 185
 186                                _ao_spi_recv_dma_done,
 187                                (void *) (uintptr_t) id
 188                 );
 189
 190         _ao_dma_start_transfer(MOSI_DMA_ID(id),
 191                                o,
 192                                (void *) &sercom->data,
 193                                len,
 194                                dma_chctrlb(id, true),
 195                                dma_btctrl(step_out, true),
 196                                NULL,
 197                                NULL
 198                 );
 199
 200         while (ao_spi_done[id] == 0)
 201                 ao_sleep(&ao_spi_done[id]);
 202
 203         _ao_dma_done_transfer(MOSI_DMA_ID(id));
 204         _ao_dma_done_transfer(MISO_DMA_ID(id));
 205         ao_arch_release_interrupts();
 206 }
 207
 208 #else
 209
 210 static void
 211 spi_run(const void *out, void *in, uint16_t len, uint16_t spi_index, bool step_out, bool step_in)
 212 {
 213         uint8_t                 id = AO_SPI_INDEX(spi_index);
 214         struct samd21_sercom    *sercom = ao_spi_samd21_info[id].sercom;
 215         const uint8_t           *o = out;
 216         uint8_t                 *i = in;
 217
 218         while (len--) {
 219 #if SPI_DEBUG
 220                 printf("%02x", *o);
 221 #endif
 222                 sercom->data = *o;
 223                 while ((sercom->intflag & (1 << SAMD21_SERCOM_INTFLAG_RXC)) == 0)
 224                         ;
 225                 *i = (uint8_t) sercom->data;
 226 #if SPI_DEBUG
 227                 printf("\t%02x\n", *i);
 228 #endif
 229                 if (step_out)
 230                         o++;
 231                 if (step_in)
 232                         i++;
 233         }
 234 }
 235
 236 #endif
 237
 238 void
 239 ao_spi_send(const void *block, uint16_t len, uint16_t spi_index)
 240 {
 241         spi_run(block, &spi_dev_null, len, spi_index, true, false);
 242 }
 243
 244
 245 void
 246 ao_spi_recv(void *block, uint16_t len, uint16_t spi_index)
 247 {
 248         spi_dev_null = 0xff;
 249         spi_run(&spi_dev_null, block, len, spi_index, false, true);
 250 }
 251
 252
 253 void
 254 ao_spi_duplex(const void *out, void *in, uint16_t len, uint16_t spi_index)
 255 {
 256         spi_run(out, in, len, spi_index, true, true);
 257 }
 258
 259 static void
 260 ao_spi_disable_pin_config(uint16_t spi_pin_config)
 261 {
 262         switch (spi_pin_config) {
 263 #if HAS_SPI_0
 264         case AO_SPI_PIN_CONFIG(AO_SPI_0_PA08_PA09_PA10):
 265                 samd21_port_pmux_clr(&samd21_port_a, 8);        /* MOSI */
 266                 samd21_port_pmux_clr(&samd21_port_a, 9);        /* SCLK */
 267                 samd21_port_pmux_clr(&samd21_port_a, 10);       /* MISO */
 268                 break;
 269         case AO_SPI_PIN_CONFIG(AO_SPI_0_PA04_PA05_PA06):
 270                 samd21_port_pmux_clr(&samd21_port_a, 4);        /* MOSI */
 271                 samd21_port_pmux_clr(&samd21_port_a, 5);        /* SCLK */
 272                 samd21_port_pmux_clr(&samd21_port_a, 6);        /* MISO */
 273                 break;
 274 #endif
 275 #if HAS_SPI_5
 276         case AO_SPI_PIN_CONFIG(AO_SPI_5_PB22_PB23_PB03):
 277                 samd21_port_pmux_clr(&samd21_port_b, 22);       /* MOSI */
 278                 samd21_port_pmux_clr(&samd21_port_b, 23);       /* SCLK */
 279                 samd21_port_pmux_clr(&samd21_port_b, 3);        /* MISO */
 280                 break;
 281 #endif
 282         case 0xffff:
 283                 break;
 284         }
 285 }
 286
 287 static void
 288 ao_spi_enable_pin_config(uint16_t spi_pin_config)
 289 {
 290         switch (spi_pin_config) {
 291 #if HAS_SPI_0
 292         case AO_SPI_PIN_CONFIG(AO_SPI_0_PA08_PA09_PA10):
 293                 ao_enable_output(&samd21_port_a, 8, 1);
 294                 ao_enable_output(&samd21_port_a, 9, 1);
 295                 ao_enable_input(&samd21_port_a, 10, AO_MODE_PULL_NONE);
 296
 297                 samd21_port_pmux_set(&samd21_port_a, 8, SAMD21_PORT_PMUX_FUNC_C);       /* MOSI */
 298                 samd21_port_pmux_set(&samd21_port_a, 9, SAMD21_PORT_PMUX_FUNC_C);       /* SCLK */
 299                 samd21_port_pmux_set(&samd21_port_a, 10, SAMD21_PORT_PMUX_FUNC_C);      /* MISO */
 300                 break;
 301         case AO_SPI_PIN_CONFIG(AO_SPI_0_PA04_PA05_PA06):
 302                 ao_enable_output(&samd21_port_a, 4, 1);
 303                 ao_enable_output(&samd21_port_a, 5, 1);
 304                 ao_enable_input(&samd21_port_a, 6, AO_MODE_PULL_NONE);
 305
 306                 samd21_port_pmux_set(&samd21_port_a, 4, SAMD21_PORT_PMUX_FUNC_C);       /* MOSI */
 307                 samd21_port_pmux_set(&samd21_port_a, 5, SAMD21_PORT_PMUX_FUNC_C);       /* SCLK */
 308                 samd21_port_pmux_set(&samd21_port_a, 6, SAMD21_PORT_PMUX_FUNC_C);       /* MISO */
 309                 break;
 310 #endif
 311 #if HAS_SPI_4
 312         case AO_SPI_PIN_CONFIG(AO_SPI_4_PB10_PB11_PA12):
 313                 ao_enable_output(&samd21_port_b, 10, 1);
 314                 ao_enable_output(&samd21_port_b, 11, 1);
 315                 ao_enable_input(&samd21_port_a, 12, AO_MODE_PULL_NONE);
 316
 317                 samd21_port_pmux_set(&samd21_port_b, 10, SAMD21_PORT_PMUX_FUNC_D);      /* MOSI */
 318                 samd21_port_pmux_set(&samd21_port_b, 11, SAMD21_PORT_PMUX_FUNC_D);      /* SCLK */
 319                 samd21_port_pmux_set(&samd21_port_a, 12, SAMD21_PORT_PMUX_FUNC_D);      /* MISO */
 320                 break;
 321 #endif
 322 #if HAS_SPI_5
 323         case AO_SPI_PIN_CONFIG(AO_SPI_5_PB22_PB23_PB03):
 324                 ao_enable_output(&samd21_port_b, 22, 1);
 325                 ao_enable_output(&samd21_port_b, 23, 1);
 326                 ao_enable_input(&samd21_port_b, 3, AO_MODE_PULL_NONE);
 327
 328                 samd21_port_pmux_set(&samd21_port_b, 22, SAMD21_PORT_PMUX_FUNC_D);      /* 5.2 MOSI */
 329                 samd21_port_pmux_set(&samd21_port_b, 23, SAMD21_PORT_PMUX_FUNC_D);      /* 5.3 SCLK */
 330                 samd21_port_pmux_set(&samd21_port_b, 3, SAMD21_PORT_PMUX_FUNC_D);       /* 5.1 MISO */
 331                 break;
 332 #endif
 333         default:
 334                 ao_panic(AO_PANIC_SPI);
 335                 break;
 336         }
 337 }
 338
 339 static void
 340 ao_spi_config(uint16_t spi_index, uint32_t baud)
 341 {
 342         uint16_t                spi_pin_config = AO_SPI_PIN_CONFIG(spi_index);
 343         uint8_t                 id = AO_SPI_INDEX(spi_index);
 344         struct samd21_sercom    *sercom = ao_spi_samd21_info[id].sercom;
 345
 346         if (spi_pin_config != ao_spi_pin_config[id]) {
 347                 ao_spi_disable_pin_config(ao_spi_pin_config[id]);
 348                 ao_spi_enable_pin_config(spi_pin_config);
 349                 ao_spi_pin_config[id] = spi_pin_config;
 350         }
 351
 352         sercom->baud = (uint16_t) baud;
 353
 354         /* Set spi mode */
 355         uint32_t ctrla = sercom->ctrla;
 356         ctrla &= ~((1UL << SAMD21_SERCOM_CTRLA_CPOL) |
 357                    (1UL << SAMD21_SERCOM_CTRLA_CPHA) |
 358                    (SAMD21_SERCOM_CTRLA_DOPO_MASK << SAMD21_SERCOM_CTRLA_DOPO) |
 359                    (SAMD21_SERCOM_CTRLA_DIPO_MASK << SAMD21_SERCOM_CTRLA_DIPO));
 360         ctrla |= ((AO_SPI_CPOL(spi_index) << SAMD21_SERCOM_CTRLA_CPOL) |
 361                   (AO_SPI_CPHA(spi_index) << SAMD21_SERCOM_CTRLA_CPHA) |
 362                   (AO_SPI_DOPO(spi_index) << SAMD21_SERCOM_CTRLA_DOPO) |
 363                   (AO_SPI_DIPO(spi_index) << SAMD21_SERCOM_CTRLA_DIPO));
 364
 365         /* finish setup and enable the hardware */
 366         ctrla |= (1 << SAMD21_SERCOM_CTRLA_ENABLE);
 367
 368 #if SPI_DEBUG
 369         printf("ctrla %08lx\n", ctrla);
 370 #endif
 371
 372         sercom->ctrla = ctrla;
 373
 374         while (sercom->syncbusy & (1 << SAMD21_SERCOM_SYNCBUSY_ENABLE))
 375                 ;
 376 }
 377
 378 void
 379 ao_spi_get(uint16_t spi_index, uint32_t speed)
 380 {
 381         uint8_t         id = AO_SPI_INDEX(spi_index);
 382
 383         ao_mutex_get(&ao_spi_mutex[id]);
 384         ao_spi_config(spi_index, speed);
 385 }
 386
 387 void
 388 ao_spi_put(uint16_t spi_index)
 389 {
 390         uint8_t                 id = AO_SPI_INDEX(spi_index);
 391         struct samd21_sercom    *sercom = ao_spi_samd21_info[id].sercom;
 392
 393         sercom->ctrla &= ~(1UL << SAMD21_SERCOM_CTRLA_ENABLE);
 394         while (sercom->syncbusy & (1 << SAMD21_SERCOM_SYNCBUSY_ENABLE))
 395                 ;
 396         ao_mutex_put(&ao_spi_mutex[id]);
 397 }
 398
 399 static void
 400 ao_spi_init_sercom(uint8_t id)
 401 {
 402         struct samd21_sercom *sercom = ao_spi_samd21_info[id].sercom;
 403
 404         /* Send a clock along */
 405         samd21_gclk_clkctrl(0, SAMD21_GCLK_CLKCTRL_ID_SERCOM0_CORE + id);
 406
 407         samd21_nvic_set_enable(SAMD21_NVIC_ISR_SERCOM0_POS + id);
 408         samd21_nvic_set_priority(SAMD21_NVIC_ISR_SERCOM0_POS + id, 4);
 409
 410         /* Enable */
 411         samd21_pm.apbcmask |= (1 << (SAMD21_PM_APBCMASK_SERCOM0 + id));
 412
 413         /* Reset */
 414         sercom->ctrla = (1 << SAMD21_SERCOM_CTRLA_SWRST);
 415
 416         while ((sercom->ctrla & (1 << SAMD21_SERCOM_CTRLA_SWRST)) ||
 417                (sercom->syncbusy & (1 << SAMD21_SERCOM_SYNCBUSY_SWRST)))
 418                 ;
 419
 420         /* set SPI mode */
 421         sercom->ctrla = ((SAMD21_SERCOM_CTRLA_DORD_MSB << SAMD21_SERCOM_CTRLA_DORD) |
 422                          (0 << SAMD21_SERCOM_CTRLA_CPOL) |
 423                          (0 << SAMD21_SERCOM_CTRLA_CPHA) |
 424                          (0 << SAMD21_SERCOM_CTRLA_FORM) |
 425                          (2 << SAMD21_SERCOM_CTRLA_DIPO) |
 426                          (0 << SAMD21_SERCOM_CTRLA_DOPO) |
 427                          (0 << SAMD21_SERCOM_CTRLA_IBON) |
 428                          (0 << SAMD21_SERCOM_CTRLA_RUNSTDBY) |
 429                          (SAMD21_SERCOM_CTRLA_MODE_SPI_HOST << SAMD21_SERCOM_CTRLA_MODE) |
 430                          (0 << SAMD21_SERCOM_CTRLA_ENABLE) |
 431                          (0 << SAMD21_SERCOM_CTRLA_SWRST));
 432
 433         sercom->ctrlb = ((1 << SAMD21_SERCOM_CTRLB_RXEN) |
 434                          (0 << SAMD21_SERCOM_CTRLB_AMODE) |
 435                          (0 << SAMD21_SERCOM_CTRLB_MSSEN) |
 436                          (0 << SAMD21_SERCOM_CTRLB_SSDE) |
 437                          (0 << SAMD21_SERCOM_CTRLB_PLOADEN) |
 438                          (SAMD21_SERCOM_CTRLB_CHSIZE_8 << SAMD21_SERCOM_CTRLB_CHSIZE));
 439
 440         ao_spi_pin_config[id] = 0xffff;
 441 }
 442
 443 void
 444 ao_spi_init(void)
 445 {
 446 #if HAS_SPI_0
 447         ao_spi_init_sercom(0);
 448 #endif
 449 #if HAS_SPI_1
 450         ao_spi_init_sercom(1);
 451 #endif
 452 #if HAS_SPI_2
 453         ao_spi_init_sercom(2);
 454 #endif
 455 #if HAS_SPI_3
 456         ao_spi_init_sercom(3);
 457 #endif
 458 #if HAS_SPI_4
 459         ao_spi_init_sercom(4);
 460 #endif
 461 #if HAS_SPI_5
 462         ao_spi_init_sercom(5);
 463 #endif
 464 }