2 * Copyright © 2019 Keith Packard <keithp@keithp.com>
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
12 * General Public License for more details.
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
19 #ifndef _AO_ARCH_FUNCS_H_
20 #define _AO_ARCH_FUNCS_H_
22 #define AO_MODE_PULL_NONE 0
23 #define AO_MODE_PULL_UP 1
24 #define AO_MODE_PULL_DOWN 2
26 static inline void ao_enable_port(struct samd21_port *port)
29 samd21_pm.apbbmask |= (1UL << SAMD21_PM_APBBMASK_PORT);
32 static inline void ao_disable_port(struct samd21_port *port)
35 samd21_pm.apbbmask &= ~(1UL << SAMD21_PM_APBBMASK_PORT);
39 ao_gpio_set(struct samd21_port *port, uint8_t bit, uint8_t v)
42 port->outset = (1 << bit);
44 port->outclr = (1 << bit);
48 ao_gpio_get(struct samd21_port *port, uint8_t bit)
50 return (port->in >> bit) & 1;
54 ao_gpio_dir_set(struct samd21_port *port, uint8_t bit, bool output)
57 port->dirset = (1 << bit);
59 port->dirclr = (1 << bit);
63 ao_gpio_set_mode(struct samd21_port *port, uint8_t bit, uint32_t mode)
67 if (mode != AO_MODE_PULL_NONE) {
68 pincfg |= (1 << SAMD21_PORT_PINCFG_PULLEN);
69 ao_gpio_set(port, bit, mode == AO_MODE_PULL_UP);
72 samd21_port_pincfg_set(port, bit,
73 (0 << SAMD21_PORT_PINCFG_DRVSTR) |
74 (1 << SAMD21_PORT_PINCFG_PULLEN) |
75 (0 << SAMD21_PORT_PINCFG_INEN) |
76 (0 << SAMD21_PORT_PINCFG_PMUXEN),
81 ao_enable_output(struct samd21_port *port, uint8_t pin, uint8_t v)
84 ao_gpio_set(port, pin, v);
85 samd21_port_dir_set(port, pin, SAMD21_PORT_DIR_OUT);
86 samd21_port_pincfg_set(port, pin,
87 (1 << SAMD21_PORT_PINCFG_DRVSTR) |
88 (1 << SAMD21_PORT_PINCFG_PULLEN) |
89 (1 << SAMD21_PORT_PINCFG_INEN),
90 (0 << SAMD21_PORT_PINCFG_DRVSTR) |
91 (0 << SAMD21_PORT_PINCFG_PULLEN) |
92 (0 << SAMD21_PORT_PINCFG_INEN));
96 ao_enable_input(struct samd21_port *port, uint8_t pin, uint32_t mode)
99 samd21_port_dir_set(port, pin, SAMD21_PORT_DIR_IN);
102 pincfg = ((0 << SAMD21_PORT_PINCFG_DRVSTR) |
103 (0 << SAMD21_PORT_PINCFG_PULLEN) |
104 (1 << SAMD21_PORT_PINCFG_INEN) |
105 (0 << SAMD21_PORT_PINCFG_PMUXEN));
107 if (mode != AO_MODE_PULL_NONE) {
108 pincfg |= (1 << SAMD21_PORT_PINCFG_PULLEN);
109 ao_gpio_set(port, pin, mode == AO_MODE_PULL_UP);
112 samd21_port_pincfg_set(port, pin,
113 (1 << SAMD21_PORT_PINCFG_DRVSTR) |
114 (1 << SAMD21_PORT_PINCFG_PULLEN) |
115 (1 << SAMD21_PORT_PINCFG_INEN) |
116 (1 << SAMD21_PORT_PINCFG_PMUXEN),
121 ao_enable_cs(struct samd21_port *port, uint8_t pin)
123 ao_enable_output(port, pin, 1);
126 /* ao_spi_samd21.c */
128 #define AO_SPI_INDEX_BIT 0
129 #define AO_SPI_INDEX_MASK 0x07
131 #define AO_SPI_CONFIG_BIT 4
132 #define AO_SPI_CONFIG_MASK (3 << AO_SPI_CONFIG_BIT)
134 #define AO_SPI_CPOL_BIT 6
135 #define AO_SPI_CPHA_BIT 7
137 #define AO_SPI_DOPO_BIT 8
138 #define AO_SPI_DOPO_MOSI_0_SCLK_1 (0 << AO_SPI_DOPO_BIT)
139 #define AO_SPI_DOPO_MOSI_2_SCLK_3 (1 << AO_SPI_DOPO_BIT)
140 #define AO_SPI_DOPO_MOSI_3_SCLK_1 (2 << AO_SPI_DOPO_BIT)
141 #define AO_SPI_DOPO_MOSI_0_SCLK_3 (3 << AO_SPI_DOPO_BIT)
142 #define AO_SPI_DOPO_MASK (3 << AO_SPI_DOPO_BIT)
144 #define AO_SPI_DIPO_BIT 10
145 #define AO_SPI_DIPO_MISO_0 (0 << AO_SPI_DIPO_BIT)
146 #define AO_SPI_DIPO_MISO_1 (1 << AO_SPI_DIPO_BIT)
147 #define AO_SPI_DIPO_MISO_2 (2 << AO_SPI_DIPO_BIT)
148 #define AO_SPI_DIPO_MISO_3 (3 << AO_SPI_DIPO_BIT)
149 #define AO_SPI_DIPO_MASK (3 << AO_SPI_DIPO_MASK)
151 #define AO_SPI_CONFIG_0 (0 << AO_SPI_CONFIG_BIT)
152 #define AO_SPI_CONFIG_1 (1 << AO_SPI_CONFIG_BIT)
153 #define AO_SPI_CONFIG_2 (2 << AO_SPI_CONFIG_BIT)
154 #define AO_SPI_CONFIG_3 (3 << AO_SPI_CONFIG_BIT)
157 * PA08 SERCOM0.0 -> MOSI (DOPO 0)
158 * PA09 SERCOM0.1 -> SCLK (DOPO 0)
159 * PA10 SERCOM0.2 -> MISO (DIPO 2)
161 #define AO_SPI_0_CONFIG_PA08_PA09_PA10 (AO_SPI_CONFIG_0 | \
162 AO_SPI_DOPO_MOSI_0_SCLK_1 | \
166 * PA04 SERCOM0.0 -> MOSI (DOPO 0)
167 * PA05 SERCOM0.1 -> SCLK (DOPO 0)
168 * PA16 SERCOM0.2 -> MISO (DIPO 2)
170 #define AO_SPI_0_CONFIG_PA04_PA05_PA06 (AO_SPI_CONFIG_1 | \
171 AO_SPI_DOPO_MOSI_0_SCLK_1 | \
175 * PB10 SERCOM4.2 -> MOSI (DOPO 1)
176 * PB11 SERCOM4.3 -> SCLK (DOPO 1)
177 * PA12 SERCOM4.0 -> MISO (DIPO 0)
179 #define AO_SPI_4_CONFIG_PB10_PB11_PA12 (AO_SPI_CONFIG_0 | \
180 AO_SPI_DOPO_MOSI_2_SCLK_3 | \
184 * PB22 SERCOM5.2 -> MOSI (DOPO 1)
185 * PB23 SERCOM5.3 -> SCLK (DOPO 1)
186 * PB03 SERCOM5.1 -> MISO (DIPO 1)
188 #define AO_SPI_5_CONFIG_PB22_PB23_PB03 (AO_SPI_CONFIG_3 | \
189 AO_SPI_DOPO_MOSI_2_SCLK_3 | \
192 #define AO_SPI_INDEX(id) ((uint8_t) ((id) & AO_SPI_INDEX_MASK))
193 #define AO_SPI_CONFIG(id) ((id) & AO_SPI_CONFIG_MASK)
194 #define AO_SPI_PIN_CONFIG(id) ((id) & (AO_SPI_INDEX_MASK | AO_SPI_CONFIG_MASK))
195 #define AO_SPI_CPOL(id) ((uint32_t) (((id) >> AO_SPI_CPOL_BIT) & 1))
196 #define AO_SPI_CPHA(id) ((uint32_t) (((id) >> AO_SPI_CPHA_BIT) & 1))
197 #define AO_SPI_DOPO(id) ((uint32_t) (((id) >> AO_SPI_DOPO_BIT) & 3))
198 #define AO_SPI_DIPO(id) ((uint32_t) (((id) >> AO_SPI_DIPO_BIT) & 3))
201 * We're not going to do any fancy SPI pin remapping, just use the first
202 * three PAD pins, which means:
209 #define AO_SPI_0_PA08_PA09_PA10 (0 | AO_SPI_0_CONFIG_PA08_PA09_PA10)
210 #define AO_SPI_0_PA04_PA05_PA06 (0 | AO_SPI_0_CONFIG_PA04_PA05_PA06)
212 #define AO_SPI_4_PB10_PB11_PA12 (4 | AO_SPI_4_CONFIG_PB10_PB11_PA12)
214 #define AO_SPI_5_PB22_PB23_PB03 (5 | AO_SPI_5_CONFIG_PB22_PB23_PB03)
217 ao_spi_send(const void *block, uint16_t len, uint16_t spi_index);
220 ao_spi_recv(void *block, uint16_t len, uint16_t spi_index);
223 ao_spi_duplex(const void *out, void *in, uint16_t len, uint16_t spi_index);
226 ao_spi_get(uint16_t spi_index, uint32_t speed);
229 ao_spi_put(uint16_t spi_index);
234 #define ao_spi_set_cs(reg,mask) do { \
235 reg->outclr = mask; \
238 #define ao_spi_clr_cs(reg,mask) do { \
239 reg->outset = mask; \
242 #define ao_spi_get_mask(reg,mask,spi_index, speed) do { \
243 ao_spi_get(spi_index, speed); \
244 ao_spi_set_cs(reg,mask); \
247 #define ao_spi_put_mask(reg,mask,spi_index) do { \
248 ao_spi_clr_cs(reg,mask); \
249 ao_spi_put(spi_index); \
253 ao_spi_get_bit(struct samd21_port *port, uint8_t bit, uint16_t spi_index, uint32_t speed)
255 ao_spi_get(spi_index, speed);
256 ao_gpio_set(port, bit, 0);
260 ao_spi_put_bit(struct samd21_port *port, uint8_t bit, uint16_t spi_index)
262 ao_gpio_set(port, bit, 1);
263 ao_spi_put(spi_index);
266 static inline uint8_t
267 ao_spi_speed(uint32_t hz)
269 int32_t baud = (int32_t) (AO_SYSCLK / (2 * hz)) - 1;
275 return (uint8_t) baud;
278 #define ao_spi_init_cs(port, mask) do { \
280 for (__bit__ = 0; __bit__ < 32; __bit__++) { \
281 if (mask & (1 << __bit__)) \
282 ao_enable_output(port, __bit__, 1); \
286 #define ARM_PUSH32(stack, val) (*(--(stack)) = (val))
288 typedef uint32_t ao_arch_irq_t;
290 static inline uint32_t
291 ao_arch_irqsave(void) {
293 asm("mrs %0,primask" : "=&r" (primask));
294 ao_arch_block_interrupts();
299 ao_arch_irqrestore(uint32_t primask) {
300 asm("msr primask,%0" : : "r" (primask));
304 ao_arch_memory_barrier(void) {
305 asm volatile("" ::: "memory");
310 ao_arch_init_stack(struct ao_task *task, uint32_t *sp, void *start)
312 uint32_t a = (uint32_t) start;
315 /* Return address (goes into LR) */
318 /* Clear register values r0-r7 */
326 /* PRIMASK with interrupts enabled */
332 static inline void ao_arch_save_regs(void) {
333 /* Save general registers */
334 asm("push {r0-r7,lr}\n");
341 asm("mrs r0,primask");
345 static inline void ao_arch_save_stack(void) {
347 asm("mov %0,sp" : "=&r" (sp) );
348 ao_cur_task->sp32 = (sp);
349 if (sp < &ao_cur_task->stack32[0])
350 ao_panic (AO_PANIC_STACK);
353 static inline void ao_arch_restore_stack(void) {
355 asm("mov sp, %0" : : "r" (ao_cur_task->sp32) );
357 /* Restore PRIMASK */
359 asm("msr primask,r0");
363 asm("msr apsr_nczvq,r0");
365 /* Restore general registers */
366 asm("pop {r0-r7,pc}\n");
369 #ifndef HAS_SAMPLE_PROFILE
370 #define HAS_SAMPLE_PROFILE 0
373 #if !HAS_SAMPLE_PROFILE
374 #define HAS_ARCH_START_SCHEDULER 1
376 static inline void ao_arch_start_scheduler(void) {
380 asm("mrs %0,msp" : "=&r" (sp));
381 asm("msr psp,%0" : : "r" (sp));
382 asm("mrs %0,control" : "=&r" (control));
384 asm("msr control,%0" : : "r" (control));
389 #define ao_arch_isr_stack()
393 #define ao_arch_wait_interrupt() do { \
395 ao_arch_release_interrupts(); \
396 asm(".global ao_idle_loc\nao_idle_loc:"); \
397 ao_arch_block_interrupts(); \
400 #define ao_arch_critical(b) do { \
401 uint32_t __mask = ao_arch_irqsave(); \
402 do { b } while (0); \
403 ao_arch_irqrestore(__mask); \
406 /* ao_serial_samd21.c */
408 #if USE_SERIAL_0_FLOW && USE_SERIAL_0_SW_FLOW || USE_SERIAL_1_FLOW && USE_SERIAL_1_SW_FLOW
409 #define HAS_SERIAL_SW_FLOW 1
411 #define HAS_SERIAL_SW_FLOW 0
414 #if USE_SERIAL_1_FLOW && !USE_SERIAL_1_SW_FLOW
415 #define USE_SERIAL_1_HW_FLOW 1
418 #if USE_SERIAL_0_FLOW && !USE_SERIAL_0_SW_FLOW
419 #define USE_SERIAL_0_HW_FLOW 1
422 #if USE_SERIAL_0_HW_FLOW || USE_SERIAL_1_HW_FLOW
423 #define HAS_SERIAL_HW_FLOW 1
425 #define HAS_SERIAL_HW_FLOW 0
428 struct ao_samd21_usart {
429 struct ao_fifo rx_fifo;
430 struct ao_fifo tx_fifo;
431 struct samd21_sercom *reg;
434 #if HAS_SERIAL_SW_FLOW
435 /* RTS - 0 if we have FIFO space, 1 if not
436 * CTS - 0 if we can send, 0 if not
438 struct samd21_port *gpio_rts;
439 struct samd21_port *gpio_cts;
447 extern struct ao_samd21_usart ao_samd21_usart0;
451 ao_serial_init(void);
453 /* ao_usb_samd21.c */
457 ao_usb_out_hook(uint8_t *buffer, uint16_t count);
462 #endif /* _AO_ARCH_FUNCS_H_ */