2 * Copyright © 2013 Keith Packard <keithp@keithp.com>
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; version 2 of the License.
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
11 * General Public License for more details.
13 * You should have received a copy of the GNU General Public License along
14 * with this program; if not, write to the Free Software Foundation, Inc.,
15 * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
21 #define CC115L_BURST 6
25 #define CC115L_IOCFG2 0x00 /* GDO2 Output Pin Configuration */
26 #define CC115L_IOCFG1 0x01 /* GDO1 Output Pin Configuration */
27 #define CC115L_IOCFG0 0x02 /* GDO0 Output Pin Configuration */
29 #define CC115L_IOCFG_GPIO1_DS 7
30 #define CC115L_IOCFG_GPIO_INV 6
32 #define CC115L_IOCFG_GPIO_CFG 0
33 #define CC115L_IOCFG_GPIO_CFG_TXFIFO_THR 2
34 #define CC115L_IOCFG_GPIO_CFG_TXFIFO_THR_PKT 3
35 #define CC115L_IOCFG_GPIO_CFG_TXFIFO_UNDERFLOW 5
36 #define CC115L_IOCFG_GPIO_CFG_PKT_SYNC_TX 6
37 #define CC115L_IOCFG_GPIO_CFG_PLL_LOCKED 10
38 #define CC115L_IOCFG_GPIO_CFG_SERIAL_CLK 11
39 #define CC115L_IOCFG_GPIO_CFG_SYNC_DATA 12
40 #define CC115L_IOCFG_GPIO_CFG_ASYNC_DATA 13
41 #define CC115L_IOCFG_GPIO_CFG_PA_PD 27
42 #define CC115L_IOCFG_GPIO_CFG_CHIP_RDYn 41
43 #define CC115L_IOCFG_GPIO_CFG_XOSC_STABLE 43
44 #define CC115L_IOCFG_GPIO_CFG_HIGHZ 46
45 #define CC115L_IOCFG_GPIO_CFG_HW_0 47
46 #define CC115L_IOCFG_GPIO_CFG_CLK_XOSC_1 48
47 #define CC115L_IOCFG_GPIO_CFG_CLK_XOSC_1_5 49
48 #define CC115L_IOCFG_GPIO_CFG_CLK_XOSC_2 50
49 #define CC115L_IOCFG_GPIO_CFG_CLK_XOSC_3 51
50 #define CC115L_IOCFG_GPIO_CFG_CLK_XOSC_4 52
51 #define CC115L_IOCFG_GPIO_CFG_CLK_XOSC_6 53
52 #define CC115L_IOCFG_GPIO_CFG_CLK_XOSC_8 54
53 #define CC115L_IOCFG_GPIO_CFG_CLK_XOSC_12 55
54 #define CC115L_IOCFG_GPIO_CFG_CLK_XOSC_16 56
55 #define CC115L_IOCFG_GPIO_CFG_CLK_XOSC_24 57
56 #define CC115L_IOCFG_GPIO_CFG_CLK_XOSC_32 58
57 #define CC115L_IOCFG_GPIO_CFG_CLK_XOSC_48 59
58 #define CC115L_IOCFG_GPIO_CFG_CLK_XOSC_64 60
59 #define CC115L_IOCFG_GPIO_CFG_CLK_XOSC_96 61
60 #define CC115L_IOCFG_GPIO_CFG_CLK_XOSC_128 62
61 #define CC115L_IOCFG_GPIO_CFG_CLK_XOSC_192 63
62 #define CC115L_IOCFG_GPIO_CFG_MASK 0x3f
64 #define CC115L_FIFOTHR 0x03 /* TX FIFO Thresholds */
65 #define CC115L_FIFOTHR_THR_MASK 0x0f
66 #define CC115L_FIFOTHR_THR_61 0
67 #define CC115L_FIFOTHR_THR_57 1
68 #define CC115L_FIFOTHR_THR_53 2
69 #define CC115L_FIFOTHR_THR_49 3
70 #define CC115L_FIFOTHR_THR_45 4
71 #define CC115L_FIFOTHR_THR_41 5
72 #define CC115L_FIFOTHR_THR_37 6
73 #define CC115L_FIFOTHR_THR_33 7
74 #define CC115L_FIFOTHR_THR_29 8
75 #define CC115L_FIFOTHR_THR_25 9
76 #define CC115L_FIFOTHR_THR_21 10
77 #define CC115L_FIFOTHR_THR_17 11
78 #define CC115L_FIFOTHR_THR_13 12
79 #define CC115L_FIFOTHR_THR_9 13
80 #define CC115L_FIFOTHR_THR_5 14
81 #define CC115L_FIFOTHR_THR_1 15
83 #define CC115L_SYNC1 0x04 /* Sync Word, High Byte */
84 #define CC115L_SYNC0 0x05 /* Sync Word, Low Byte */
85 #define CC115L_PKTLEN 0x06 /* Packet Length */
86 #define CC115L_PKTCTRL0 0x08 /* Packet Automation Control */
87 #define CC115L_PKTCTRL0_PKT_FORMAT 4
88 #define CC115L_PKTCTRL0_PKT_FORMAT_NORMAL 0
89 #define CC115L_PKTCTRL0_PKT_FORMAT_SYNC_SERIAL 1
90 #define CC115L_PKTCTRL0_PKT_FORMAT_RANDOM 2
91 #define CC115L_PKTCTRL0_PKT_FORMAT_ASYNC_SERIAL 3
92 #define CC115L_PKTCTRL0_PKT_FORMAT_MASK 3
93 #define CC115L_PKTCTRL0_PKT_CRC_EN 2
94 #define CC115L_PKTCTRL0_PKT_LENGTH_CONFIG 0
95 #define CC115L_PKTCTRL0_PKT_LENGTH_CONFIG_FIXED 0
96 #define CC115L_PKTCTRL0_PKT_LENGTH_CONFIG_VARIABLE 1
97 #define CC115L_PKTCTRL0_PKT_LENGTH_CONFIG_INFINITE 2
98 #define CC115L_PKTCTRL0_PKT_LENGTH_CONFIG_MASK 3
99 #define CC115L_CHANNR 0x0a /* Channel Number */
100 #define CC115L_FSCTRL0 0x0c /* Frequency Synthesizer Control */
101 #define CC115L_FREQ2 0x0d /* Frequency Control Word, High Byte */
102 #define CC115L_FREQ1 0x0e /* Frequency Control Word, Middle Byte */
103 #define CC115L_FREQ0 0x0f /* Frequency Control Word, Low Byte */
104 #define CC115L_MDMCFG4 0x10 /* Modem Configuration */
105 #define CC115L_MDMCFG4_DRATE_E 0
106 #define CC115L_MDMCFG3 0x11 /* Modem Configuration */
107 #define CC115L_MDMCFG2 0x12 /* Modem Configuration */
108 #define CC115L_MDMCFG2_MOD_FORMAT 4
109 #define CC115L_MDMCFG2_MOD_FORMAT_2FSK 0
110 #define CC115L_MDMCFG2_MOD_FORMAT_GFSK 1
111 #define CC115L_MDMCFG2_MOD_FORMAT_OOK 3
112 #define CC115L_MDMCFG2_MOD_FORMAT_4FSK 4
113 #define CC115L_MDMCFG2_MOD_FORMAT_MASK 7
114 #define CC115L_MDMCFG2_MANCHESTER_EN 3
115 #define CC115L_MDMCFG2_SYNC_MODE 0
116 #define CC115L_MDMCFG2_SYNC_MODE_NONE 0
117 #define CC115L_MDMCFG2_SYNC_MODE_16BITS 1
118 #define CC115L_MDMCFG2_SYNC_MODE_32BITS 3
119 #define CC115L_MDMCFG2_SYNC_MODE_MASK 3
120 #define CC115L_MDMCFG1 0x13 /* Modem Configuration */
121 #define CC115L_MDMCFG1_NUM_PREAMBLE 4
122 #define CC115L_MDMCFG1_NUM_PREAMBLE_2 0
123 #define CC115L_MDMCFG1_NUM_PREAMBLE_3 1
124 #define CC115L_MDMCFG1_NUM_PREAMBLE_4 2
125 #define CC115L_MDMCFG1_NUM_PREAMBLE_6 3
126 #define CC115L_MDMCFG1_NUM_PREAMBLE_8 4
127 #define CC115L_MDMCFG1_NUM_PREAMBLE_12 5
128 #define CC115L_MDMCFG1_NUM_PREAMBLE_16 6
129 #define CC115L_MDMCFG1_NUM_PREAMBLE_24 7
130 #define CC115L_MDMCFG1_NUM_PREAMBLE_MASK 7
131 #define CC115L_MDMCFG1_CHANSPC_E 0
132 #define CC115L_MDMCFG0 0x14 /* Modem Configuration */
133 #define CC115L_DEVIATN 0x15 /* Modem Deviation Setting */
134 #define CC115L_DEVIATN_DEVIATION_E 4
135 #define CC115L_DEVIATN_DEVIATION_E_MASK 7
136 #define CC115L_DEVIATN_DEVIATION_M 0
137 #define CC115L_DEVIATN_DEVIATION_M_MASK 7
138 #define CC115L_MCSM1 0x17 /* Main Radio Control State Machine Configuration */
139 #define CC115L_MCSM1_TXOFF_MODE 0
140 #define CC115L_MCSM1_TXOFF_MODE_IDLE 0
141 #define CC115L_MCSM1_TXOFF_MODE_FSTXON 1
142 #define CC115L_MCSM1_TXOFF_MODE_TX 2
143 #define CC115L_MCSM1_TXOFF_MODE_MASK 3
144 #define CC115L_MCSM0 0x18 /* Main Radio Control State Machine Configuration */
145 #define CC115L_MCSM0_FS_AUTOCAL 4
146 #define CC115L_MCSM0_FS_AUTOCAL_NEVER 0
147 #define CC115L_MCSM0_FS_AUTOCAL_IDLE_TO_TX 1
148 #define CC115L_MCSM0_FS_AUTOCAL_TX_TO_IDLE 2
149 #define CC115L_MCSM0_FS_AUTOCAL_4TH_TX_TO_IDLE 3
150 #define CC115L_MCSM0_FS_AUTOCAL_MASK 3
151 #define CC115L_MCSM0_PO_TIMEOUT 2
152 #define CC115L_MCSM0_PO_TIMEOUT_1 0
153 #define CC115L_MCSM0_PO_TIMEOUT_16 1
154 #define CC115L_MCSM0_PO_TIMEOUT_64 2
155 #define CC115L_MCSM0_PO_TIMEOUT_256 3
156 #define CC115L_MCSM0_PO_TIMEOUT_MASK 3
157 #define CC115L_MCSM0_XOSC_FORCE_ON 0
158 #define CC115L_RESERVED_0X20 0x20 /* Use setting from SmartRF Studio */
159 #define CC115L_FREND0 0x22 /* Front End TX Configuration */
160 #define CC115L_FSCAL3 0x23 /* Frequency Synthesizer Calibration */
161 #define CC115L_FSCAL2 0x24 /* Frequency Synthesizer Calibration */
162 #define CC115L_FSCAL1 0x25 /* Frequency Synthesizer Calibration */
163 #define CC115L_FSCAL0 0x26 /* Frequency Synthesizer Calibration */
164 #define CC115L_RESERVED_0X29 0x29 /* Use setting from SmartRF Studio */
165 #define CC115L_RESERVED_0X2A 0x2a /* Use setting from SmartRF Studio */
166 #define CC115L_RESERVED_0X2B 0x2b /* Use setting from SmartRF Studio */
167 #define CC115L_TEST2 0x2c /* Various Test Settings */
168 #define CC115L_TEST1 0x2d /* Various Test Settings */
169 #define CC115L_TEST0 0x2e /* Various Test Settings */
171 /* Status registers (use BURST bit to select these) */
172 #define CC115L_PARTNUM (0x30|(1<<CC115L_BURST)) /* Part number for CC115L */
173 #define CC115L_VERSION (0x31|(1<<CC115L_BURST)) /* Current version number */
174 #define CC115L_MARCSTATE (0x35|(1<<CC115L_BURST)) /* Control state machine state */
175 #define CC115L_MARCSTATE_MASK 0x1f
176 #define CC115L_MARCSTATE_SLEEP 0x00
177 #define CC115L_MARCSTATE_IDLE 0x01
178 #define CC115L_MARCSTATE_XOFF 0x02
179 #define CC115L_MARCSTATE_VCOON_MC 0x03
180 #define CC115L_MARCSTATE_REGON_MC 0x04
181 #define CC115L_MARCSTATE_MANCAL 0x05
182 #define CC115L_MARCSTATE_VCOON 0x06
183 #define CC115L_MARCSTATE_REGON 0x07
184 #define CC115L_MARCSTATE_STARTCAL 0x08
185 #define CC115L_MARCSTATE_BWBOOST 0x09
186 #define CC115L_MARCSTATE_FS_LOCK 0x0a
187 #define CC115L_MARCSTATE_ENDCAL 0x0c
188 #define CC115L_MARCSTATE_FSTXON 0x12
189 #define CC115L_MARCSTATE_TX 0x13
190 #define CC115L_MARCSTATE_TX_END 0x14
191 #define CC115L_MARCSTATE_TX_UNDERFLOW 0x16
192 #define CC115L_PKTSTATUS (0x38|(1<<CC115L_BURST)) /* Current GDOx status and packet status */
193 #define CC115L_TXBYTES (0x3a|(1<<CC115L_BURST)) /* Underflow and number of bytes in the TX FIFO */
194 #define CC115L_TXBYTES_TXFIFO_UNDERFLOW 7
195 #define CC115L_TXBYTES_NUM_TX_BYTES 0
196 #define CC115L_TXBYTES_NUM_TX_BYTES_MASK 0x7f
198 /* Command strobes (no BURST bit for these) */
199 #define CC115L_SRES 0x30
200 #define CC115L_SFSTXON 0x31
201 #define CC115L_SXOFF 0x32
202 #define CC115L_SCAL 0x33
203 #define CC115L_STX 0x35
204 #define CC115L_SIDLE 0x36
205 #define CC115L_SPWD 0x39
206 #define CC115L_SFTX 0x3b
207 #define CC115L_SNOP 0x3d
209 #define CC115L_PA 0x3e
210 #define CC115L_FIFO 0x3f
212 #define CC115L_FIFO_SIZE 64
215 #define CC115L_STATUS_CHIP_RDY 7
216 #define CC115L_STATUS_STATE 4
217 #define CC115L_STATUS_STATE_IDLE 0
218 #define CC115L_STATUS_STATE_TX 2
219 #define CC115L_STATUS_STATE_FSTXON 3
220 #define CC115L_STATUS_STATE_CALIBRATE 4
221 #define CC115L_STATUS_STATE_SETTLING 5
222 #define CC115L_STATUS_STATE_TX_FIFO_UNDERFLOW 7
223 #define CC115L_STATUS_STATE_MASK 7
225 #define CC115L_STATUS_FIFO_BYTES_AVAILABLE 0
226 #endif /* _AO_CC115L_H_ */
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