1 /* RX filter BW = 100.000000 */
\r
2 /* Address config = No address check */
\r
3 /* Packet length = 255 */
\r
4 /* Symbol rate = 38.3606 */
\r
5 /* PA ramping = false */
\r
6 /* Carrier frequency = 434.549988 */
\r
7 /* Bit rate = 38.3606 */
\r
8 /* Whitening = true */
\r
9 /* Manchester enable = false */
\r
10 /* Modulation format = 2-GFSK */
\r
11 /* Packet length mode = Variable */
\r
12 /* Device address = 0 */
\r
14 /* Deviation = 20.507812 */
\r
15 /***************************************************************
\r
16 * SmartRF Studio(tm) Export
\r
18 * Radio register settings specifed with address, value
\r
22 ***************************************************************/
\r
24 CC1120_SYNC3, 0xD3, /* Sync Word Configuration [31:24] */
\r
25 CC1120_SYNC2, 0x91, /* Sync Word Configuration [23:16] */
\r
26 CC1120_SYNC1, 0xD3, /* Sync Word Configuration [15:8] */
\r
27 CC1120_SYNC0, 0x91, /* Sync Word Configuration [7:0] */
\r
29 CC1120_SYNC_CFG1, /* Sync Word Detection Configuration */
\r
30 (CC1120_SYNC_CFG1_DEM_CFG_PQT_GATING_ENABLED << CC1120_SYNC_CFG1_DEM_CFG) |
\r
31 (0x07 << CC1120_SYNC_CFG1_SYNC_THR),
\r
33 (CC1120_SYNC_CFG0_SYNC_MODE_16_BITS << CC1120_SYNC_CFG0_SYNC_MODE) |
\r
34 (CC1120_SYNC_CFG0_SYNC_NUM_ERROR_2 << CC1120_SYNC_CFG0_SYNC_NUM_ERROR),
\r
35 CC1120_DCFILT_CFG, 0x1c, /* Digital DC Removal Configuration */
\r
36 CC1120_PREAMBLE_CFG1, /* Preamble Length Configuration */
\r
37 (CC1120_PREAMBLE_CFG1_NUM_PREAMBLE_4_BYTES << CC1120_PREAMBLE_CFG1_NUM_PREAMBLE) |
\r
38 (CC1120_PREAMBLE_CFG1_PREAMBLE_WORD_AA << CC1120_PREAMBLE_CFG1_PREAMBLE_WORD),
\r
39 CC1120_PREAMBLE_CFG0,
\r
40 (1 << CC1120_PREAMBLE_CFG0_PQT_EN) |
\r
41 (0x6 << CC1120_PREAMBLE_CFG0_PQT),
\r
42 CC1120_FREQ_IF_CFG, 0x40, /* RX Mixer Frequency Configuration */
\r
43 CC1120_IQIC, 0x46, /* Digital Image Channel Compensation Configuration */
\r
44 CC1120_CHAN_BW, 0x02, /* Channel Filter Configuration */
\r
46 CC1120_MDMCFG1, /* General Modem Parameter Configuration */
\r
47 (0 << CC1120_MDMCFG1_CARRIER_SENSE_GATE) |
\r
48 (1 << CC1120_MDMCFG1_FIFO_EN) |
\r
49 (0 << CC1120_MDMCFG1_MANCHESTER_EN) |
\r
50 (0 << CC1120_MDMCFG1_INVERT_DATA_EN) |
\r
51 (0 << CC1120_MDMCFG1_COLLISION_DETECT_EN) |
\r
52 (CC1120_MDMCFG1_DVGA_GAIN_9 << CC1120_MDMCFG1_DVGA_GAIN) |
\r
53 (0 << CC1120_MDMCFG1_SINGLE_ADC_EN),
\r
54 CC1120_MDMCFG0, 0x05, /* General Modem Parameter Configuration */
\r
56 CC1120_AGC_REF, 0x20, /* AGC Reference Level Configuration */
\r
57 CC1120_AGC_CS_THR, 0x19, /* Carrier Sense Threshold Configuration */
\r
58 CC1120_AGC_GAIN_ADJUST, 0x00, /* RSSI Offset Configuration */
\r
59 CC1120_AGC_CFG3, 0x91, /* AGC Configuration */
\r
60 CC1120_AGC_CFG2, 0x20, /* AGC Configuration */
\r
61 CC1120_AGC_CFG1, 0xa9, /* AGC Configuration */
\r
62 CC1120_AGC_CFG0, 0xcf, /* AGC Configuration */
\r
63 CC1120_FIFO_CFG, /* FIFO Configuration */
\r
64 (0 << CC1120_FIFO_CFG_CRC_AUTOFLUSH) |
\r
65 (0x40 << CC1120_FIFO_CFG_FIFO_THR),
\r
66 CC1120_DEV_ADDR, 0x00, /* Device Address Configuration */
\r
67 CC1120_SETTLING_CFG, /* Frequency Synthesizer Calibration and Settling Configuration */
\r
68 (CC1120_SETTLING_CFG_FS_AUTOCAL_IDLE_TO_ON << CC1120_SETTLING_CFG_FS_AUTOCAL) |
\r
69 (CC1120_SETTLING_CFG_LOCK_TIME_50_20 << CC1120_SETTLING_CFG_LOCK_TIME) |
\r
70 (CC1120_SETTLING_CFG_FSREG_TIME_60 << CC1120_SETTLING_CFG_FSREG_TIME),
\r
71 CC1120_FS_CFG, /* Frequency Synthesizer Configuration */
\r
72 (1 << CC1120_FS_CFG_LOCK_EN) |
\r
73 (CC1120_FS_CFG_FSD_BANDSELECT_410_480 << CC1120_FS_CFG_FSD_BANDSELECT),
\r
74 CC1120_WOR_CFG1, 0x08, /* eWOR Configuration, Reg 1 */
\r
75 CC1120_WOR_CFG0, 0x21, /* eWOR Configuration, Reg 0 */
\r
76 CC1120_WOR_EVENT0_MSB, 0x00, /* Event 0 Configuration */
\r
77 CC1120_WOR_EVENT0_LSB, 0x00, /* Event 0 Configuration */
\r
79 CC1120_PKT_CFG2, 0x04, /* Packet Configuration, Reg 2 */
\r
80 CC1120_PKT_CFG1, 0x45, /* Packet Configuration, Reg 1 */
\r
81 CC1120_PKT_CFG0, 0x00, /* Packet Configuration, Reg 0 */
\r
83 CC1120_RFEND_CFG1, 0x0f, /* RFEND Configuration, Reg 1 */
\r
84 CC1120_RFEND_CFG0, 0x00, /* RFEND Configuration, Reg 0 */
\r
85 // CC1120_PA_CFG2, 0x3f, /* Power Amplifier Configuration, Reg 2 */
\r
86 CC1120_PA_CFG2, 0x3f, /* Power Amplifier Configuration, Reg 2 */
\r
87 CC1120_PA_CFG1, 0x56, /* Power Amplifier Configuration, Reg 1 */
\r
88 CC1120_PA_CFG0, 0x7b, /* Power Amplifier Configuration, Reg 0 */
\r
89 CC1120_PKT_LEN, 0xff, /* Packet Length Configuration */
\r
90 CC1120_IF_MIX_CFG, 0x00, /* IF Mix Configuration */
\r
91 CC1120_FREQOFF_CFG, 0x22, /* Frequency Offset Correction Configuration */
\r
92 CC1120_TOC_CFG, 0x0b, /* Timing Offset Correction Configuration */
\r
93 CC1120_MARC_SPARE, 0x00, /* MARC Spare */
\r
94 CC1120_ECG_CFG, 0x00, /* External Clock Frequency Configuration */
\r
95 CC1120_SOFT_TX_DATA_CFG, 0x00, /* Soft TX Data Configuration */
\r
96 CC1120_EXT_CTRL, 0x00, /* External Control Configuration */
\r
97 CC1120_RCCAL_FINE, 0x00, /* RC Oscillator Calibration (fine) */
\r
98 CC1120_RCCAL_COARSE, 0x00, /* RC Oscillator Calibration (coarse) */
\r
99 CC1120_RCCAL_OFFSET, 0x00, /* RC Oscillator Calibration Clock Offset */
\r
100 CC1120_FREQOFF1, 0x00, /* Frequency Offset (MSB) */
\r
101 CC1120_FREQOFF0, 0x00, /* Frequency Offset (LSB) */
\r
102 CC1120_IF_ADC2, 0x02, /* Analog to Digital Converter Configuration, Reg 2 */
\r
103 CC1120_IF_ADC1, 0xa6, /* Analog to Digital Converter Configuration, Reg 1 */
\r
104 CC1120_IF_ADC0, 0x04, /* Analog to Digital Converter Configuration, Reg 0 */
\r
105 CC1120_FS_DIG1, 0x00, /* */
\r
106 CC1120_FS_DIG0, 0x5f, /* */
\r
107 CC1120_FS_CAL3, 0x00, /* */
\r
108 CC1120_FS_CAL2, 0x20, /* */
\r
109 CC1120_FS_CAL1, 0x40, /* */
\r
110 CC1120_FS_CAL0, 0x0e, /* */
\r
111 CC1120_FS_CHP, 0x28, /* Charge Pump Configuration */
\r
112 CC1120_FS_DIVTWO, 0x03, /* Divide by 2 */
\r
113 CC1120_FS_DSM1, 0x00, /* Digital Synthesizer Module Configuration, Reg 1 */
\r
114 CC1120_FS_DSM0, 0x33, /* Digital Synthesizer Module Configuration, Reg 0 */
\r
115 CC1120_FS_DVC1, 0xff, /* Divider Chain Configuration, Reg 1 */
\r
116 CC1120_FS_DVC0, 0x17, /* Divider Chain Configuration, Reg 0 */
\r
117 CC1120_FS_LBI, 0x00, /* Local Bias Configuration */
\r
118 CC1120_FS_PFD, 0x50, /* Phase Frequency Detector Configuration */
\r
119 CC1120_FS_PRE, 0x6e, /* Prescaler Configuration */
\r
120 CC1120_FS_REG_DIV_CML, 0x14, /* */
\r
121 CC1120_FS_SPARE, 0xac, /* */
\r
122 CC1120_FS_VCO4, 0x14, /* VCO Configuration, Reg 4 */
\r
123 CC1120_FS_VCO3, 0x00, /* VCO Configuration, Reg 3 */
\r
124 CC1120_FS_VCO2, 0x00, /* VCO Configuration, Reg 2 */
\r
125 CC1120_FS_VCO1, 0x00, /* VCO Configuration, Reg 1 */
\r
126 CC1120_FS_VCO0, 0xb4, /* VCO Configuration, Reg 0 */
\r
127 CC1120_GBIAS6, 0x00, /* Global Bias Configuration, Reg 6 */
\r
128 CC1120_GBIAS5, 0x02, /* Global Bias Configuration, Reg 5 */
\r
129 CC1120_GBIAS4, 0x00, /* Global Bias Configuration, Reg 4 */
\r
130 CC1120_GBIAS3, 0x00, /* Global Bias Configuration, Reg 3 */
\r
131 CC1120_GBIAS2, 0x10, /* Global Bias Configuration, Reg 2 */
\r
132 CC1120_GBIAS1, 0x00, /* Global Bias Configuration, Reg 1 */
\r
133 CC1120_GBIAS0, 0x00, /* Global Bias Configuration, Reg 0 */
\r
134 CC1120_IFAMP, 0x01, /* Intermediate Frequency Amplifier Configuration */
\r
135 CC1120_LNA, 0x01, /* Low Noise Amplifier Configuration */
\r
136 CC1120_RXMIX, 0x01, /* RX Mixer Configuration */
\r
137 CC1120_XOSC5, 0x0e, /* Crystal Oscillator Configuration, Reg 5 */
\r
138 CC1120_XOSC4, 0xa0, /* Crystal Oscillator Configuration, Reg 4 */
\r
139 CC1120_XOSC3, 0x03, /* Crystal Oscillator Configuration, Reg 3 */
\r
140 CC1120_XOSC2, 0x04, /* Crystal Oscillator Configuration, Reg 2 */
\r
141 CC1120_XOSC1, 0x01, /* Crystal Oscillator Configuration, Reg 1 */
\r
142 CC1120_XOSC0, 0x00, /* Crystal Oscillator Configuration, Reg 0 */
\r
143 CC1120_ANALOG_SPARE, 0x00, /* */
\r
144 CC1120_PA_CFG3, 0x00, /* Power Amplifier Configuration, Reg 3 */
\r
145 CC1120_WOR_TIME1, 0x00, /* eWOR Timer Status (MSB) */
\r
146 CC1120_WOR_TIME0, 0x00, /* eWOR Timer Status (LSB) */
\r
147 CC1120_WOR_CAPTURE1, 0x00, /* eWOR Timer Capture (MSB) */
\r
148 CC1120_WOR_CAPTURE0, 0x00, /* eWOR Timer Capture (LSB) */
\r
149 CC1120_BIST, 0x00, /* MARC BIST */
\r
150 CC1120_DCFILTOFFSET_I1, 0x00, /* DC Filter Offset I (MSB) */
\r
151 CC1120_DCFILTOFFSET_I0, 0x00, /* DC Filter Offset I (LSB) */
\r
152 CC1120_DCFILTOFFSET_Q1, 0x00, /* DC Filter Offset Q (MSB) */
\r
153 CC1120_DCFILTOFFSET_Q0, 0x00, /* DC Filter Offset Q (LSB) */
\r
154 CC1120_IQIE_I1, 0x00, /* IQ Imbalance Value I (MSB) */
\r
155 CC1120_IQIE_I0, 0x00, /* IQ Imbalance Value I (LSB) */
\r
156 CC1120_IQIE_Q1, 0x00, /* IQ Imbalance Value Q (MSB) */
\r
157 CC1120_IQIE_Q0, 0x00, /* IQ Imbalance Value Q (LSB) */
\r
158 CC1120_RSSI1, 0x80, /* Received Signal Strength Indicator (MSB) */
\r
159 CC1120_RSSI0, 0x00, /* Received Signal Strength Indicator (LSB) */
\r
160 CC1120_MARCSTATE, 0x41, /* MARC State */
\r
161 CC1120_LQI_VAL, 0x00, /* Link Quality Indicator Value */
\r
162 CC1120_PQT_SYNC_ERR, 0xff, /* Preamble and Sync Word Error */
\r
163 CC1120_DEM_STATUS, 0x00, /* Demodulator Status */
\r
164 CC1120_FREQOFF_EST1, 0x00, /* Frequency Offset Estimate (MSB) */
\r
165 CC1120_FREQOFF_EST0, 0x00, /* Frequency Offset Estimate (LSB) */
\r
166 CC1120_AGC_GAIN3, 0x00, /* AGC Gain, Reg 3 */
\r
167 CC1120_AGC_GAIN2, 0xd1, /* AGC Gain, Reg 2 */
\r
168 CC1120_AGC_GAIN1, 0x00, /* AGC Gain, Reg 1 */
\r
169 CC1120_AGC_GAIN0, 0x3f, /* AGC Gain, Reg 0 */
\r
170 CC1120_SOFT_RX_DATA_OUT, 0x00, /* Soft Decision Symbol Data */
\r
171 CC1120_SOFT_TX_DATA_IN, 0x00, /* Soft TX Data Input Register */
\r
172 CC1120_ASK_SOFT_RX_DATA, 0x30, /* AGC ASK Soft Decision Output */
\r
173 CC1120_RNDGEN, 0x7f, /* Random Number Value */
\r
174 CC1120_MAGN2, 0x00, /* Signal Magnitude after CORDIC [16] */
\r
175 CC1120_MAGN1, 0x00, /* Signal Magnitude after CORDIC [15:8] */
\r
176 CC1120_MAGN0, 0x00, /* Signal Magnitude after CORDIC [7:0] */
\r
177 CC1120_ANG1, 0x00, /* Signal Angular after CORDIC [9:8] */
\r
178 CC1120_ANG0, 0x00, /* Signal Angular after CORDIC [7:0] */
\r
179 CC1120_CHFILT_I2, 0x08, /* Channel Filter Data Real Part [18:16] */
\r
180 CC1120_CHFILT_I1, 0x00, /* Channel Filter Data Real Part [15:8] */
\r
181 CC1120_CHFILT_I0, 0x00, /* Channel Filter Data Real Part [7:0] */
\r
182 CC1120_CHFILT_Q2, 0x00, /* Channel Filter Data Imaginary Part [18:16] */
\r
183 CC1120_CHFILT_Q1, 0x00, /* Channel Filter Data Imaginary Part [15:8] */
\r
184 CC1120_CHFILT_Q0, 0x00, /* Channel Filter Data Imaginary Part [7:0] */
\r
185 CC1120_GPIO_STATUS, 0x00, /* GPIO Status */
\r
186 CC1120_FSCAL_CTRL, 0x01, /* */
\r
187 CC1120_PHASE_ADJUST, 0x00, /* */
\r
188 CC1120_PARTNUMBER, 0x00, /* Part Number */
\r
189 CC1120_PARTVERSION, 0x00, /* Part Revision */
\r
190 CC1120_SERIAL_STATUS, 0x00, /* Serial Status */
\r
191 CC1120_RX_STATUS, 0x01, /* RX Status */
\r
192 CC1120_TX_STATUS, 0x00, /* TX Status */
\r
193 CC1120_MARC_STATUS1, 0x00, /* MARC Status, Reg 1 */
\r
194 CC1120_MARC_STATUS0, 0x00, /* MARC Status, Reg 0 */
\r
195 CC1120_PA_IFAMP_TEST, 0x00, /* */
\r
196 CC1120_FSRF_TEST, 0x00, /* */
\r
197 CC1120_PRE_TEST, 0x00, /* */
\r
198 CC1120_PRE_OVR, 0x00, /* */
\r
199 CC1120_ADC_TEST, 0x00, /* ADC Test */
\r
200 CC1120_DVC_TEST, 0x0b, /* DVC Test */
\r
201 CC1120_ATEST, 0x40, /* */
\r
202 CC1120_ATEST_LVDS, 0x00, /* */
\r
203 CC1120_ATEST_MODE, 0x00, /* */
\r
204 CC1120_XOSC_TEST1, 0x3c, /* */
\r
205 CC1120_XOSC_TEST0, 0x00, /* */
\r
206 CC1120_RXFIRST, 0x00, /* RX FIFO Pointer (first entry) */
\r
207 CC1120_TXFIRST, 0x00, /* TX FIFO Pointer (first entry) */
\r
208 CC1120_RXLAST, 0x00, /* RX FIFO Pointer (last entry) */
\r
209 CC1120_TXLAST, 0x00, /* TX FIFO Pointer (last entry) */
\r
projects / fw / altos / blob