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   1 /*
   2  * Copyright © 2012 Keith Packard <keithp@keithp.com>
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; version 2 of the License.
   7  *
   8  * This program is distributed in the hope that it will be useful, but
   9  * WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  11  * General Public License for more details.
  12  *
  13  * You should have received a copy of the GNU General Public License along
  14  * with this program; if not, write to the Free Software Foundation, Inc.,
  15  * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
  16  */
  17
  18 #include <ao.h>
  19 #include <ao_cc1120.h>
  20 #include <ao_exti.h>
  21
  22 uint8_t ao_radio_done;
  23 uint8_t ao_radio_mutex;
  24 uint8_t ao_radio_abort;
  25
  26 #define CC1120_DEBUG    1
  27
  28 uint32_t        ao_radio_cal = 1186611;
  29
  30 #define ao_radio_select()       ao_spi_get_mask(AO_CC1120_SPI_CS_PORT,(1 << AO_CC1120_SPI_CS_PIN),AO_CC1120_SPI_BUS)
  31 #define ao_radio_deselect()     ao_spi_put_mask(AO_CC1120_SPI_CS_PORT,(1 << AO_CC1120_SPI_CS_PIN),AO_CC1120_SPI_BUS)
  32 #define ao_radio_spi_send(d,l)  ao_spi_send((d), (l), AO_CC1120_SPI_BUS)
  33 #define ao_radio_spi_send_fixed(d,l) ao_spi_send_fixed((d), (l), AO_CC1120_SPI_BUS)
  34 #define ao_radio_spi_recv(d,l)  ao_spi_recv((d), (l), AO_CC1120_SPI_BUS)
  35 #define ao_radio_duplex(o,i,l)  ao_spi_duplex((o), (i), (l), AO_CC1120_SPI_BUS)
  36
  37 static uint8_t
  38 ao_radio_reg_read(uint16_t addr)
  39 {
  40         uint8_t data[2];
  41         uint8_t d;
  42
  43 #if CC1120_DEBUG
  44         printf("ao_radio_reg_read (%04x): ", addr); flush();
  45 #endif
  46         if (CC1120_IS_EXTENDED(addr)) {
  47                 data[0] = ((1 << CC1120_READ)  |
  48                            (0 << CC1120_BURST) |
  49                            CC1120_EXTENDED);
  50                 data[1] = addr;
  51                 d = 2;
  52         } else {
  53                 data[0] = ((1 << CC1120_READ)  |
  54                            (0 << CC1120_BURST) |
  55                            addr);
  56                 d = 1;
  57         }
  58         ao_radio_select();
  59         ao_radio_spi_send(data, d);
  60         ao_radio_spi_recv(data, 1);
  61         ao_radio_deselect();
  62 #if CC1120_DEBUG
  63         printf (" %02x\n", data[0]);
  64 #endif
  65         return data[0];
  66 }
  67
  68 static void
  69 ao_radio_reg_write(uint16_t addr, uint8_t value)
  70 {
  71         uint8_t data[3];
  72         uint8_t d;
  73
  74 #if CC1120_DEBUG
  75         printf("ao_radio_reg_write (%04x): %02x\n", addr, value);
  76 #endif
  77         if (CC1120_IS_EXTENDED(addr)) {
  78                 data[0] = ((1 << CC1120_READ)  |
  79                            (0 << CC1120_BURST) |
  80                            CC1120_EXTENDED);
  81                 data[1] = addr;
  82                 d = 2;
  83         } else {
  84                 data[0] = ((1 << CC1120_READ)  |
  85                            (0 << CC1120_BURST) |
  86                            addr);
  87                 d = 1;
  88         }
  89         data[d] = value;
  90         ao_radio_select();
  91         ao_radio_spi_send(data, d+1);
  92         ao_radio_deselect();
  93 }
  94
  95 static uint8_t
  96 ao_radio_strobe(uint8_t addr)
  97 {
  98         uint8_t in;
  99
 100         ao_radio_select();
 101         ao_radio_duplex(&addr, &in, 1);
 102         ao_radio_deselect();
 103         return in;
 104 }
 105
 106 static uint8_t
 107 ao_radio_fifo_read(uint8_t *data, uint8_t len)
 108 {
 109         uint8_t addr = ((1 << CC1120_READ)  |
 110                         (1 << CC1120_BURST) |
 111                         CC1120_FIFO);
 112         uint8_t status;
 113
 114         ao_radio_select();
 115         ao_radio_duplex(&addr, &status, 1);
 116         ao_radio_spi_recv(data, len);
 117         ao_radio_deselect();
 118         return status;
 119 }
 120
 121 static uint8_t
 122 ao_radio_fifo_write(uint8_t *data, uint8_t len)
 123 {
 124         uint8_t addr = ((0 << CC1120_READ)  |
 125                         (1 << CC1120_BURST) |
 126                         CC1120_FIFO);
 127         uint8_t status;
 128
 129         ao_radio_select();
 130         ao_radio_duplex(&addr, &status, 1);
 131         ao_radio_spi_send(data, len);
 132         ao_radio_deselect();
 133         return status;
 134 }
 135
 136 static uint8_t
 137 ao_radio_fifo_write_fixed(uint8_t data, uint8_t len)
 138 {
 139         uint8_t addr = ((0 << CC1120_READ)  |
 140                         (1 << CC1120_BURST) |
 141                         CC1120_FIFO);
 142         uint8_t status;
 143
 144         ao_radio_select();
 145         ao_radio_duplex(&addr, &status, 1);
 146         ao_radio_spi_send_fixed(data, len);
 147         ao_radio_deselect();
 148         return status;
 149 }
 150
 151 static uint8_t
 152 ao_radio_status(void)
 153 {
 154         return ao_radio_strobe (CC1120_SNOP);
 155 }
 156
 157 void
 158 ao_radio_recv_abort(void)
 159 {
 160         ao_radio_abort = 1;
 161         ao_wakeup(&ao_radio_done);
 162 }
 163
 164 #define ao_radio_rdf_value 0x55
 165
 166 static const uint16_t   rdf_setup[] = {
 167 };
 168
 169 void
 170 ao_radio_rdf(uint8_t len)
 171 {
 172         int i;
 173
 174         ao_radio_abort = 0;
 175         ao_radio_get(len);
 176         ao_radio_done = 0;
 177         for (i = 0; i < sizeof (rdf_setup) / sizeof (rdf_setup[0]); i += 2)
 178                 ao_radio_reg_write(rdf_setup[i], rdf_setup[i+1]);
 179         ao_radio_fifo_write_fixed(ao_radio_rdf_value, len);
 180         ao_radio_reg_write(CC1120_IOCFG2, CC1120_IOCFG_GPIO_CFG_RX0TX1_CFG);
 181         ao_exti_enable(&AO_CC1120_INT_PORT, AO_CC1120_INT_PIN);
 182         ao_radio_strobe(CC1120_STX);
 183         cli();
 184         while (!ao_radio_done)
 185                 ao_sleep(&ao_radio_done);
 186         sei();
 187         ao_radio_set_packet();
 188         ao_radio_put();
 189 }
 190
 191 void
 192 ao_radio_rdf_abort(void)
 193 {
 194 }
 195
 196 static void
 197 ao_radio_test(void)
 198 {
 199         uint8_t mode = 2;
 200         uint8_t radio_on;
 201         ao_cmd_white();
 202         if (ao_cmd_lex_c != '\n') {
 203                 ao_cmd_decimal();
 204                 mode = (uint8_t) ao_cmd_lex_u32;
 205         }
 206         mode++;
 207         if ((mode & 2) && !radio_on) {
 208 #if HAS_MONITOR
 209                 ao_monitor_disable();
 210 #endif
 211 #if PACKET_HAS_SLAVE
 212                 ao_packet_slave_stop();
 213 #endif
 214                 ao_radio_get(0xff);
 215                 ao_radio_strobe(CC1120_STX);
 216                 radio_on = 1;
 217         }
 218         if (mode == 3) {
 219                 printf ("Hit a character to stop..."); flush();
 220                 getchar();
 221                 putchar('\n');
 222         }
 223         if ((mode & 1) && radio_on) {
 224                 ao_radio_idle();
 225                 ao_radio_put();
 226                 radio_on = 0;
 227 #if HAS_MONITOR
 228                 ao_monitor_enable();
 229 #endif
 230         }
 231 }
 232
 233 void
 234 ao_radio_send(void *d, uint8_t size)
 235 {
 236         ao_radio_get(size);
 237         ao_radio_done = 0;
 238         ao_radio_fifo_write(d, size);
 239         ao_radio_reg_write(CC1120_IOCFG2, CC1120_IOCFG_GPIO_CFG_RX0TX1_CFG);
 240         ao_exti_enable(&AO_CC1120_INT_PORT, AO_CC1120_INT_PIN);
 241         ao_radio_strobe(CC1120_STX);
 242         cli();
 243         while (!ao_radio_done)
 244                 ao_sleep(&ao_radio_done);
 245         sei();
 246         ao_radio_put();
 247 }
 248
 249 uint8_t
 250 ao_radio_recv(__xdata void *d, uint8_t size)
 251 {
 252         /* configure interrupt pin */
 253         ao_radio_get(size);
 254         ao_radio_done = 0;
 255         ao_radio_reg_write(CC1120_IOCFG2, CC1120_IOCFG_GPIO_CFG_RXFIFO_THR_PKT);
 256         ao_exti_enable(&AO_CC1120_INT_PORT, AO_CC1120_INT_PIN);
 257         ao_radio_strobe(CC1120_SRX);
 258         cli();
 259         while (!ao_radio_done && !ao_radio_abort)
 260                 ao_sleep(&ao_radio_done);
 261         sei();
 262         if (ao_radio_done)
 263                 ao_radio_fifo_read(d, size);
 264         ao_radio_put();
 265         return 0;
 266 }
 267
 268 static const uint16_t packet_setup[] = {
 269 };
 270
 271 void
 272 ao_radio_set_packet(void)
 273 {
 274         int i;
 275
 276         for (i = 0; i < sizeof (rdf_setup) / sizeof (rdf_setup[0]); i += 2)
 277                 ao_radio_reg_write(packet_setup[i], packet_setup[i+1]);
 278 }
 279
 280 void
 281 ao_radio_idle(void)
 282 {
 283         for (;;) {
 284                 uint8_t state = ao_radio_strobe(CC1120_SIDLE);
 285                 if ((state >> CC1120_STATUS_STATE) == CC1120_STATUS_STATE_IDLE)
 286                         break;
 287         }
 288 }
 289
 290 static const uint16_t radio_setup[] = {
 291 #include "ao_cc1120_CC1120.h"
 292 };
 293
 294 static uint8_t  ao_radio_configured = 0;
 295
 296 static void
 297 ao_radio_isr(void)
 298 {
 299         ao_exti_disable(&AO_CC1120_INT_PORT, AO_CC1120_INT_PIN);
 300         ao_radio_done = 1;
 301         ao_wakeup(&ao_radio_done);
 302 }
 303
 304 static void
 305 ao_radio_setup(void)
 306 {
 307         int     i;
 308
 309         for (i = 0; i < sizeof (radio_setup) / sizeof (radio_setup[0]); i += 2)
 310                 ao_radio_reg_write(radio_setup[i], radio_setup[i+1]);
 311
 312         /* Disable GPIO2 pin (radio_int) */
 313         ao_radio_reg_write(CC1120_IOCFG2, CC1120_IOCFG_GPIO_CFG_HIGHZ);
 314
 315         /* Enable the EXTI interrupt for the appropriate pin */
 316         ao_enable_port(AO_CC1120_INT_PORT);
 317         ao_exti_setup(&AO_CC1120_INT_PORT, AO_CC1120_INT_PIN, AO_EXTI_MODE_RISING, ao_radio_isr);
 318
 319         ao_radio_set_packet();
 320         ao_radio_configured = 1;
 321 }
 322
 323 void
 324 ao_radio_get(uint8_t len)
 325 {
 326         ao_mutex_get(&ao_radio_mutex);
 327         if (!ao_radio_configured)
 328                 ao_radio_setup();
 329         ao_radio_reg_write(CC1120_PKT_LEN, len);
 330 }
 331
 332 #if CC1120_DEBUG
 333 static char *cc1120_state_name[] = {
 334         [CC1120_STATUS_STATE_IDLE] = "IDLE",
 335         [CC1120_STATUS_STATE_RX] = "RX",
 336         [CC1120_STATUS_STATE_TX] = "TX",
 337         [CC1120_STATUS_STATE_FSTXON] = "FSTXON",
 338         [CC1120_STATUS_STATE_CALIBRATE] = "CALIBRATE",
 339         [CC1120_STATUS_STATE_SETTLING] = "SETTLING",
 340         [CC1120_STATUS_STATE_RX_FIFO_ERROR] = "RX_FIFO_ERROR",
 341         [CC1120_STATUS_STATE_TX_FIFO_ERROR] = "TX_FIFO_ERROR",
 342 };
 343
 344 struct ao_cc1120_reg {
 345         uint16_t        addr;
 346         char            *name;
 347 };
 348
 349 const static struct ao_cc1120_reg ao_cc1120_reg[] = {
 350         { .addr = CC1120_IOCFG3,        .name = "IOCFG3" },
 351         { .addr = CC1120_IOCFG2,        .name = "IOCFG2" },
 352         { .addr = CC1120_IOCFG1,        .name = "IOCFG1" },
 353         { .addr = CC1120_IOCFG0,        .name = "IOCFG0" },
 354         { .addr = CC1120_SYNC3, .name = "SYNC3" },
 355         { .addr = CC1120_SYNC2, .name = "SYNC2" },
 356         { .addr = CC1120_SYNC1, .name = "SYNC1" },
 357         { .addr = CC1120_SYNC0, .name = "SYNC0" },
 358         { .addr = CC1120_SYNC_CFG1,     .name = "SYNC_CFG1" },
 359         { .addr = CC1120_SYNC_CFG0,     .name = "SYNC_CFG0" },
 360         { .addr = CC1120_DEVIATION_M,   .name = "DEVIATION_M" },
 361         { .addr = CC1120_MODCFG_DEV_E,  .name = "MODCFG_DEV_E" },
 362         { .addr = CC1120_DCFILT_CFG,    .name = "DCFILT_CFG" },
 363         { .addr = CC1120_PREAMBLE_CFG1, .name = "PREAMBLE_CFG1" },
 364         { .addr = CC1120_PREAMBLE_CFG0, .name = "PREAMBLE_CFG0" },
 365         { .addr = CC1120_FREQ_IF_CFG,   .name = "FREQ_IF_CFG" },
 366         { .addr = CC1120_IQIC,  .name = "IQIC" },
 367         { .addr = CC1120_CHAN_BW,       .name = "CHAN_BW" },
 368         { .addr = CC1120_MDMCFG1,       .name = "MDMCFG1" },
 369         { .addr = CC1120_MDMCFG0,       .name = "MDMCFG0" },
 370         { .addr = CC1120_DRATE2,        .name = "DRATE2" },
 371         { .addr = CC1120_DRATE1,        .name = "DRATE1" },
 372         { .addr = CC1120_DRATE0,        .name = "DRATE0" },
 373         { .addr = CC1120_AGC_REF,       .name = "AGC_REF" },
 374         { .addr = CC1120_AGC_CS_THR,    .name = "AGC_CS_THR" },
 375         { .addr = CC1120_AGC_GAIN_ADJUST,       .name = "AGC_GAIN_ADJUST" },
 376         { .addr = CC1120_AGC_CFG3,      .name = "AGC_CFG3" },
 377         { .addr = CC1120_AGC_CFG2,      .name = "AGC_CFG2" },
 378         { .addr = CC1120_AGC_CFG1,      .name = "AGC_CFG1" },
 379         { .addr = CC1120_AGC_CFG0,      .name = "AGC_CFG0" },
 380         { .addr = CC1120_FIFO_CFG,      .name = "FIFO_CFG" },
 381         { .addr = CC1120_DEV_ADDR,      .name = "DEV_ADDR" },
 382         { .addr = CC1120_SETTLING_CFG,  .name = "SETTLING_CFG" },
 383         { .addr = CC1120_FS_CFG,        .name = "FS_CFG" },
 384         { .addr = CC1120_WOR_CFG1,      .name = "WOR_CFG1" },
 385         { .addr = CC1120_WOR_CFG0,      .name = "WOR_CFG0" },
 386         { .addr = CC1120_WOR_EVENT0_MSB,        .name = "WOR_EVENT0_MSB" },
 387         { .addr = CC1120_WOR_EVENT0_LSB,        .name = "WOR_EVENT0_LSB" },
 388         { .addr = CC1120_PKT_CFG2,      .name = "PKT_CFG2" },
 389         { .addr = CC1120_PKT_CFG1,      .name = "PKT_CFG1" },
 390         { .addr = CC1120_PKT_CFG0,      .name = "PKT_CFG0" },
 391         { .addr = CC1120_RFEND_CFG1,    .name = "RFEND_CFG1" },
 392         { .addr = CC1120_RFEND_CFG0,    .name = "RFEND_CFG0" },
 393         { .addr = CC1120_PA_CFG2,       .name = "PA_CFG2" },
 394         { .addr = CC1120_PA_CFG1,       .name = "PA_CFG1" },
 395         { .addr = CC1120_PA_CFG0,       .name = "PA_CFG0" },
 396         { .addr = CC1120_PKT_LEN,       .name = "PKT_LEN" },
 397         { .addr = CC1120_IF_MIX_CFG,    .name = "IF_MIX_CFG" },
 398         { .addr = CC1120_FREQOFF_CFG,   .name = "FREQOFF_CFG" },
 399         { .addr = CC1120_TOC_CFG,       .name = "TOC_CFG" },
 400         { .addr = CC1120_MARC_SPARE,    .name = "MARC_SPARE" },
 401         { .addr = CC1120_ECG_CFG,       .name = "ECG_CFG" },
 402         { .addr = CC1120_SOFT_TX_DATA_CFG,      .name = "SOFT_TX_DATA_CFG" },
 403         { .addr = CC1120_EXT_CTRL,      .name = "EXT_CTRL" },
 404         { .addr = CC1120_RCCAL_FINE,    .name = "RCCAL_FINE" },
 405         { .addr = CC1120_RCCAL_COARSE,  .name = "RCCAL_COARSE" },
 406         { .addr = CC1120_RCCAL_OFFSET,  .name = "RCCAL_OFFSET" },
 407         { .addr = CC1120_FREQOFF1,      .name = "FREQOFF1" },
 408         { .addr = CC1120_FREQOFF0,      .name = "FREQOFF0" },
 409         { .addr = CC1120_FREQ2, .name = "FREQ2" },
 410         { .addr = CC1120_FREQ1, .name = "FREQ1" },
 411         { .addr = CC1120_FREQ0, .name = "FREQ0" },
 412         { .addr = CC1120_IF_ADC2,       .name = "IF_ADC2" },
 413         { .addr = CC1120_IF_ADC1,       .name = "IF_ADC1" },
 414         { .addr = CC1120_IF_ADC0,       .name = "IF_ADC0" },
 415         { .addr = CC1120_FS_DIG1,       .name = "FS_DIG1" },
 416         { .addr = CC1120_FS_DIG0,       .name = "FS_DIG0" },
 417         { .addr = CC1120_FS_CAL3,       .name = "FS_CAL3" },
 418         { .addr = CC1120_FS_CAL2,       .name = "FS_CAL2" },
 419         { .addr = CC1120_FS_CAL1,       .name = "FS_CAL1" },
 420         { .addr = CC1120_FS_CAL0,       .name = "FS_CAL0" },
 421         { .addr = CC1120_FS_CHP,        .name = "FS_CHP" },
 422         { .addr = CC1120_FS_DIVTWO,     .name = "FS_DIVTWO" },
 423         { .addr = CC1120_FS_DSM1,       .name = "FS_DSM1" },
 424         { .addr = CC1120_FS_DSM0,       .name = "FS_DSM0" },
 425         { .addr = CC1120_FS_DVC1,       .name = "FS_DVC1" },
 426         { .addr = CC1120_FS_DVC0,       .name = "FS_DVC0" },
 427         { .addr = CC1120_FS_LBI,        .name = "FS_LBI" },
 428         { .addr = CC1120_FS_PFD,        .name = "FS_PFD" },
 429         { .addr = CC1120_FS_PRE,        .name = "FS_PRE" },
 430         { .addr = CC1120_FS_REG_DIV_CML,        .name = "FS_REG_DIV_CML" },
 431         { .addr = CC1120_FS_SPARE,      .name = "FS_SPARE" },
 432         { .addr = CC1120_FS_VCO4,       .name = "FS_VCO4" },
 433         { .addr = CC1120_FS_VCO3,       .name = "FS_VCO3" },
 434         { .addr = CC1120_FS_VCO2,       .name = "FS_VCO2" },
 435         { .addr = CC1120_FS_VCO1,       .name = "FS_VCO1" },
 436         { .addr = CC1120_FS_VCO0,       .name = "FS_VCO0" },
 437         { .addr = CC1120_GBIAS6,        .name = "GBIAS6" },
 438         { .addr = CC1120_GBIAS5,        .name = "GBIAS5" },
 439         { .addr = CC1120_GBIAS4,        .name = "GBIAS4" },
 440         { .addr = CC1120_GBIAS3,        .name = "GBIAS3" },
 441         { .addr = CC1120_GBIAS2,        .name = "GBIAS2" },
 442         { .addr = CC1120_GBIAS1,        .name = "GBIAS1" },
 443         { .addr = CC1120_GBIAS0,        .name = "GBIAS0" },
 444         { .addr = CC1120_IFAMP, .name = "IFAMP" },
 445         { .addr = CC1120_LNA,   .name = "LNA" },
 446         { .addr = CC1120_RXMIX, .name = "RXMIX" },
 447         { .addr = CC1120_XOSC5, .name = "XOSC5" },
 448         { .addr = CC1120_XOSC4, .name = "XOSC4" },
 449         { .addr = CC1120_XOSC3, .name = "XOSC3" },
 450         { .addr = CC1120_XOSC2, .name = "XOSC2" },
 451         { .addr = CC1120_XOSC1, .name = "XOSC1" },
 452         { .addr = CC1120_XOSC0, .name = "XOSC0" },
 453         { .addr = CC1120_ANALOG_SPARE,  .name = "ANALOG_SPARE" },
 454         { .addr = CC1120_PA_CFG3,       .name = "PA_CFG3" },
 455         { .addr = CC1120_WOR_TIME1,     .name = "WOR_TIME1" },
 456         { .addr = CC1120_WOR_TIME0,     .name = "WOR_TIME0" },
 457         { .addr = CC1120_WOR_CAPTURE1,  .name = "WOR_CAPTURE1" },
 458         { .addr = CC1120_WOR_CAPTURE0,  .name = "WOR_CAPTURE0" },
 459         { .addr = CC1120_BIST,  .name = "BIST" },
 460         { .addr = CC1120_DCFILTOFFSET_I1,       .name = "DCFILTOFFSET_I1" },
 461         { .addr = CC1120_DCFILTOFFSET_I0,       .name = "DCFILTOFFSET_I0" },
 462         { .addr = CC1120_DCFILTOFFSET_Q1,       .name = "DCFILTOFFSET_Q1" },
 463         { .addr = CC1120_DCFILTOFFSET_Q0,       .name = "DCFILTOFFSET_Q0" },
 464         { .addr = CC1120_IQIE_I1,       .name = "IQIE_I1" },
 465         { .addr = CC1120_IQIE_I0,       .name = "IQIE_I0" },
 466         { .addr = CC1120_IQIE_Q1,       .name = "IQIE_Q1" },
 467         { .addr = CC1120_IQIE_Q0,       .name = "IQIE_Q0" },
 468         { .addr = CC1120_RSSI1, .name = "RSSI1" },
 469         { .addr = CC1120_RSSI0, .name = "RSSI0" },
 470         { .addr = CC1120_MARCSTATE,     .name = "MARCSTATE" },
 471         { .addr = CC1120_LQI_VAL,       .name = "LQI_VAL" },
 472         { .addr = CC1120_PQT_SYNC_ERR,  .name = "PQT_SYNC_ERR" },
 473         { .addr = CC1120_DEM_STATUS,    .name = "DEM_STATUS" },
 474         { .addr = CC1120_FREQOFF_EST1,  .name = "FREQOFF_EST1" },
 475         { .addr = CC1120_FREQOFF_EST0,  .name = "FREQOFF_EST0" },
 476         { .addr = CC1120_AGC_GAIN3,     .name = "AGC_GAIN3" },
 477         { .addr = CC1120_AGC_GAIN2,     .name = "AGC_GAIN2" },
 478         { .addr = CC1120_AGC_GAIN1,     .name = "AGC_GAIN1" },
 479         { .addr = CC1120_AGC_GAIN0,     .name = "AGC_GAIN0" },
 480         { .addr = CC1120_SOFT_RX_DATA_OUT,      .name = "SOFT_RX_DATA_OUT" },
 481         { .addr = CC1120_SOFT_TX_DATA_IN,       .name = "SOFT_TX_DATA_IN" },
 482         { .addr = CC1120_ASK_SOFT_RX_DATA,      .name = "ASK_SOFT_RX_DATA" },
 483         { .addr = CC1120_RNDGEN,        .name = "RNDGEN" },
 484         { .addr = CC1120_MAGN2, .name = "MAGN2" },
 485         { .addr = CC1120_MAGN1, .name = "MAGN1" },
 486         { .addr = CC1120_MAGN0, .name = "MAGN0" },
 487         { .addr = CC1120_ANG1,  .name = "ANG1" },
 488         { .addr = CC1120_ANG0,  .name = "ANG0" },
 489         { .addr = CC1120_CHFILT_I2,     .name = "CHFILT_I2" },
 490         { .addr = CC1120_CHFILT_I1,     .name = "CHFILT_I1" },
 491         { .addr = CC1120_CHFILT_I0,     .name = "CHFILT_I0" },
 492         { .addr = CC1120_CHFILT_Q2,     .name = "CHFILT_Q2" },
 493         { .addr = CC1120_CHFILT_Q1,     .name = "CHFILT_Q1" },
 494         { .addr = CC1120_CHFILT_Q0,     .name = "CHFILT_Q0" },
 495         { .addr = CC1120_GPIO_STATUS,   .name = "GPIO_STATUS" },
 496         { .addr = CC1120_FSCAL_CTRL,    .name = "FSCAL_CTRL" },
 497         { .addr = CC1120_PHASE_ADJUST,  .name = "PHASE_ADJUST" },
 498         { .addr = CC1120_PARTNUMBER,    .name = "PARTNUMBER" },
 499         { .addr = CC1120_PARTVERSION,   .name = "PARTVERSION" },
 500         { .addr = CC1120_SERIAL_STATUS, .name = "SERIAL_STATUS" },
 501         { .addr = CC1120_RX_STATUS,     .name = "RX_STATUS" },
 502         { .addr = CC1120_TX_STATUS,     .name = "TX_STATUS" },
 503         { .addr = CC1120_MARC_STATUS1,  .name = "MARC_STATUS1" },
 504         { .addr = CC1120_MARC_STATUS0,  .name = "MARC_STATUS0" },
 505         { .addr = CC1120_PA_IFAMP_TEST, .name = "PA_IFAMP_TEST" },
 506         { .addr = CC1120_FSRF_TEST,     .name = "FSRF_TEST" },
 507         { .addr = CC1120_PRE_TEST,      .name = "PRE_TEST" },
 508         { .addr = CC1120_PRE_OVR,       .name = "PRE_OVR" },
 509         { .addr = CC1120_ADC_TEST,      .name = "ADC_TEST" },
 510         { .addr = CC1120_DVC_TEST,      .name = "DVC_TEST" },
 511         { .addr = CC1120_ATEST, .name = "ATEST" },
 512         { .addr = CC1120_ATEST_LVDS,    .name = "ATEST_LVDS" },
 513         { .addr = CC1120_ATEST_MODE,    .name = "ATEST_MODE" },
 514         { .addr = CC1120_XOSC_TEST1,    .name = "XOSC_TEST1" },
 515         { .addr = CC1120_XOSC_TEST0,    .name = "XOSC_TEST0" },
 516         { .addr = CC1120_RXFIRST,       .name = "RXFIRST" },
 517         { .addr = CC1120_TXFIRST,       .name = "TXFIRST" },
 518         { .addr = CC1120_RXLAST,        .name = "RXLAST" },
 519         { .addr = CC1120_TXLAST,        .name = "TXLAST" },
 520         { .addr = CC1120_NUM_TXBYTES,   .name = "NUM_TXBYTES" },
 521         { .addr = CC1120_NUM_RXBYTES,   .name = "NUM_RXBYTES" },
 522         { .addr = CC1120_FIFO_NUM_TXBYTES,      .name = "FIFO_NUM_TXBYTES" },
 523         { .addr = CC1120_FIFO_NUM_RXBYTES,      .name = "FIFO_NUM_RXBYTES" },
 524 };
 525
 526 #define AO_NUM_CC1120_REG       (sizeof ao_cc1120_reg / sizeof ao_cc1120_reg[0])
 527
 528 static void ao_radio_show(void) {
 529         uint8_t status = ao_radio_status();
 530         int     i;
 531
 532         ao_radio_get(0xff);
 533         status = ao_radio_status();
 534         printf ("Status:   %02x\n", status);
 535         printf ("CHIP_RDY: %d\n", (status >> CC1120_STATUS_CHIP_RDY) & 1);
 536         printf ("STATE:    %s\n", cc1120_state_name[(status >> CC1120_STATUS_STATE) & CC1120_STATUS_STATE_MASK]);
 537
 538         for (i = 0; i < AO_NUM_CC1120_REG; i++)
 539                 printf ("\t%02x %-20.20s\n", ao_radio_reg_read(ao_cc1120_reg[i].addr), ao_cc1120_reg[i].name);
 540         ao_radio_put();
 541 }
 542 #endif
 543
 544 static const struct ao_cmds ao_radio_cmds[] = {
 545         { ao_radio_test,        "C <1 start, 0 stop, none both>\0Radio carrier test" },
 546 #if CC1120_DEBUG
 547         { ao_radio_show,        "R\0Show CC1120 status" },
 548 #endif
 549         { 0, NULL }
 550 };
 551
 552 void
 553 ao_radio_init(void)
 554 {
 555         ao_radio_configured = 0;
 556         ao_spi_init_cs (AO_CC1120_SPI_CS_PORT, (1 << AO_CC1120_SPI_CS_PIN));
 557
 558         ao_cmd_register(&ao_radio_cmds[0]);
 559 }