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   1 /*
   2  * Copyright © 2009 Keith Packard <keithp@keithp.com>
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful, but
  10  * WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  12  * General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along
  15  * with this program; if not, write to the Free Software Foundation, Inc.,
  16  * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
  17  */
  18
  19 #include "ao.h"
  20 #include "25lc1024.h"
  21
  22 /*
  23  * Using SPI on USART 0, with P1_2 as the chip select
  24  */
  25
  26 #define EE_CS           P1_2
  27 #define EE_CS_INDEX     2
  28
  29 __xdata uint8_t ao_ee_dma_in_done;
  30 __xdata uint8_t ao_ee_dma_out_done;
  31 __xdata uint8_t ao_ee_mutex;
  32
  33 uint8_t ao_ee_dma_out_id;
  34 uint8_t ao_ee_dma_in_id;
  35
  36 static __xdata uint8_t  ao_ee_const = 0xff;
  37
  38 #define ao_ee_delay() do { \
  39         _asm nop _endasm; \
  40         _asm nop _endasm; \
  41         _asm nop _endasm; \
  42 } while(0)
  43
  44 void ao_ee_cs_low(void)
  45 {
  46         ao_ee_delay();
  47         EE_CS = 0;
  48         ao_ee_delay();
  49 }
  50
  51 void ao_ee_cs_high(void)
  52 {
  53         ao_ee_delay();
  54         EE_CS = 1;
  55         ao_ee_delay();
  56 }
  57
  58 /* Send bytes over SPI.
  59  *
  60  * This sets up two DMA engines, one writing the data and another reading
  61  * bytes coming back.  We use the bytes coming back to tell when the transfer
  62  * is complete, as the transmit register is double buffered and hence signals
  63  * completion one byte before the transfer is actually complete
  64  */
  65 static void
  66 ao_ee_send(void __xdata *block, uint16_t len)
  67 {
  68         ao_dma_set_transfer(ao_ee_dma_in_id,
  69                             &U0DBUFXADDR,
  70                             &ao_ee_const,
  71                             len,
  72                             DMA_CFG0_WORDSIZE_8 |
  73                             DMA_CFG0_TMODE_SINGLE |
  74                             DMA_CFG0_TRIGGER_URX0,
  75                             DMA_CFG1_SRCINC_0 |
  76                             DMA_CFG1_DESTINC_0 |
  77                             DMA_CFG1_PRIORITY_NORMAL);
  78
  79         ao_dma_set_transfer(ao_ee_dma_out_id,
  80                             block,
  81                             &U0DBUFXADDR,
  82                             len,
  83                             DMA_CFG0_WORDSIZE_8 |
  84                             DMA_CFG0_TMODE_SINGLE |
  85                             DMA_CFG0_TRIGGER_UTX0,
  86                             DMA_CFG1_SRCINC_1 |
  87                             DMA_CFG1_DESTINC_0 |
  88                             DMA_CFG1_PRIORITY_NORMAL);
  89
  90         ao_dma_start(ao_ee_dma_in_id);
  91         ao_dma_start(ao_ee_dma_out_id);
  92         ao_dma_trigger(ao_ee_dma_out_id);
  93         __critical while (!ao_ee_dma_in_done)
  94                 ao_sleep(&ao_ee_dma_in_done);
  95 }
  96
  97 /* Receive bytes over SPI.
  98  *
  99  * This sets up tow DMA engines, one reading the data and another
 100  * writing constant values to the SPI transmitter as that is what
 101  * clocks the data coming in.
 102  */
 103 static void
 104 ao_ee_recv(void __xdata *block, uint16_t len)
 105 {
 106         ao_dma_set_transfer(ao_ee_dma_in_id,
 107                             &U0DBUFXADDR,
 108                             block,
 109                             len,
 110                             DMA_CFG0_WORDSIZE_8 |
 111                             DMA_CFG0_TMODE_SINGLE |
 112                             DMA_CFG0_TRIGGER_URX0,
 113                             DMA_CFG1_SRCINC_0 |
 114                             DMA_CFG1_DESTINC_1 |
 115                             DMA_CFG1_PRIORITY_NORMAL);
 116
 117         ao_dma_set_transfer(ao_ee_dma_out_id,
 118                             &ao_ee_const,
 119                             &U0DBUFXADDR,
 120                             len,
 121                             DMA_CFG0_WORDSIZE_8 |
 122                             DMA_CFG0_TMODE_SINGLE |
 123                             DMA_CFG0_TRIGGER_UTX0,
 124                             DMA_CFG1_SRCINC_0 |
 125                             DMA_CFG1_DESTINC_0 |
 126                             DMA_CFG1_PRIORITY_NORMAL);
 127
 128         ao_dma_start(ao_ee_dma_in_id);
 129         ao_dma_start(ao_ee_dma_out_id);
 130         ao_dma_trigger(ao_ee_dma_out_id);
 131         __critical while (!ao_ee_dma_in_done)
 132                 ao_sleep(&ao_ee_dma_in_done);
 133 }
 134
 135 #define EE_BLOCK        256
 136
 137 struct ao_ee_instruction {
 138         uint8_t instruction;
 139         uint8_t address[3];
 140 } __xdata ao_ee_instruction;
 141
 142 static void
 143 ao_ee_write_enable(void)
 144 {
 145         ao_ee_cs_low();
 146         ao_ee_instruction.instruction = EE_WREN;
 147         ao_ee_send(&ao_ee_instruction, 1);
 148         ao_ee_cs_high();
 149 }
 150
 151 static uint8_t
 152 ao_ee_rdsr(void)
 153 {
 154         ao_ee_cs_low();
 155         ao_ee_instruction.instruction = EE_RDSR;
 156         ao_ee_send(&ao_ee_instruction, 1);
 157         ao_ee_recv(&ao_ee_instruction, 1);
 158         ao_ee_cs_high();
 159         return ao_ee_instruction.instruction;
 160 }
 161
 162 static void
 163 ao_ee_wrsr(uint8_t status)
 164 {
 165         ao_ee_cs_low();
 166         ao_ee_instruction.instruction = EE_WRSR;
 167         ao_ee_instruction.address[0] = status;
 168         ao_ee_send(&ao_ee_instruction, 2);
 169         ao_ee_cs_high();
 170 }
 171
 172 #define EE_BLOCK_NONE   0xffff
 173
 174 __xdata uint8_t ao_ee_data[EE_BLOCK];
 175 __data uint16_t ao_ee_block = EE_BLOCK_NONE;
 176 __data uint8_t  ao_ee_block_dirty;
 177
 178 /* Write the current block to the EEPROM */
 179 static void
 180 ao_ee_write_block(void)
 181 {
 182         uint8_t status;
 183
 184         status = ao_ee_rdsr();
 185         if (status & (EE_STATUS_BP0|EE_STATUS_BP1|EE_STATUS_WPEN)) {
 186                 status &= ~(EE_STATUS_BP0|EE_STATUS_BP1|EE_STATUS_WPEN);
 187                 ao_ee_wrsr(status);
 188         }
 189         ao_ee_write_enable();
 190         ao_ee_cs_low();
 191         ao_ee_instruction.instruction = EE_WRITE;
 192         ao_ee_instruction.address[0] = ao_ee_block >> 8;
 193         ao_ee_instruction.address[1] = ao_ee_block;
 194         ao_ee_instruction.address[2] = 0;
 195         ao_ee_send(&ao_ee_instruction, 4);
 196         ao_ee_send(ao_ee_data, EE_BLOCK);
 197         ao_ee_cs_high();
 198         for (;;) {
 199                 uint8_t status = ao_ee_rdsr();
 200                 if ((status & EE_STATUS_WIP) == 0)
 201                         break;
 202         }
 203 }
 204
 205 /* Read the current block from the EEPROM */
 206 static void
 207 ao_ee_read_block(void)
 208 {
 209         ao_ee_cs_low();
 210         ao_ee_instruction.instruction = EE_READ;
 211         ao_ee_instruction.address[0] = ao_ee_block >> 8;
 212         ao_ee_instruction.address[1] = ao_ee_block;
 213         ao_ee_instruction.address[2] = 0;
 214         ao_ee_send(&ao_ee_instruction, 4);
 215         ao_ee_recv(ao_ee_data, EE_BLOCK);
 216         ao_ee_cs_high();
 217 }
 218
 219 static void
 220 ao_ee_flush_internal(void)
 221 {
 222         if (ao_ee_block_dirty) {
 223                 ao_ee_write_block();
 224                 ao_ee_block_dirty = 0;
 225         }
 226 }
 227
 228 static void
 229 ao_ee_fill(uint16_t block)
 230 {
 231         if (block != ao_ee_block) {
 232                 ao_ee_flush_internal();
 233                 ao_ee_block = block;
 234                 ao_ee_read_block();
 235         }
 236 }
 237
 238 uint8_t
 239 ao_ee_write(uint32_t pos, uint8_t *buf, uint16_t len) __reentrant
 240 {
 241         uint16_t block;
 242         uint16_t this_len;
 243         uint8_t this_off;
 244
 245         if (pos >= AO_EE_DATA_SIZE || pos + len > AO_EE_DATA_SIZE)
 246                 return 0;
 247         while (len) {
 248
 249                 /* Compute portion of transfer within
 250                  * a single block
 251                  */
 252                 this_off = pos;
 253                 this_len = 256 - (uint16_t) this_off;
 254                 block = (uint16_t) (pos >> 8);
 255                 if (this_len > len)
 256                         this_len = len;
 257                 if (this_len & 0xff00)
 258                         ao_panic(AO_PANIC_EE);
 259
 260                 /* Transfer the data */
 261                 ao_mutex_get(&ao_ee_mutex); {
 262                         if (this_len != 256)
 263                                 ao_ee_fill(block);
 264                         else {
 265                                 ao_ee_flush_internal();
 266                                 ao_ee_block = block;
 267                         }
 268                         memcpy(ao_ee_data + this_off, buf, this_len);
 269                         ao_ee_block_dirty = 1;
 270                 } ao_mutex_put(&ao_ee_mutex);
 271
 272                 /* See how much is left */
 273                 buf += this_len;
 274                 len -= this_len;
 275         }
 276         return 1;
 277 }
 278
 279 uint8_t
 280 ao_ee_read(uint32_t pos, uint8_t *buf, uint16_t len) __reentrant
 281 {
 282         uint16_t block;
 283         uint16_t this_len;
 284         uint8_t this_off;
 285
 286         if (pos >= AO_EE_DATA_SIZE || pos + len > AO_EE_DATA_SIZE)
 287                 return 0;
 288         while (len) {
 289
 290                 /* Compute portion of transfer within
 291                  * a single block
 292                  */
 293                 this_off = pos;
 294                 this_len = 256 - (uint16_t) this_off;
 295                 block = (uint16_t) (pos >> 8);
 296                 if (this_len > len)
 297                         this_len = len;
 298                 if (this_len & 0xff00)
 299                         ao_panic(AO_PANIC_EE);
 300
 301                 /* Transfer the data */
 302                 ao_mutex_get(&ao_ee_mutex); {
 303                         ao_ee_fill(block);
 304                         memcpy(buf, ao_ee_data + this_off, this_len);
 305                 } ao_mutex_put(&ao_ee_mutex);
 306
 307                 /* See how much is left */
 308                 buf += this_len;
 309                 len -= this_len;
 310         }
 311         return 1;
 312 }
 313
 314 void
 315 ao_ee_flush(void) __reentrant
 316 {
 317         ao_mutex_get(&ao_ee_mutex); {
 318                 ao_ee_flush_internal();
 319         } ao_mutex_put(&ao_ee_mutex);
 320 }
 321
 322 /*
 323  * Read/write the config block, which is in
 324  * the last block of the ao_eeprom
 325  */
 326 uint8_t
 327 ao_ee_write_config(uint8_t *buf, uint16_t len) __reentrant
 328 {
 329         if (len > AO_EE_BLOCK_SIZE)
 330                 return 0;
 331         ao_mutex_get(&ao_ee_mutex); {
 332                 ao_ee_fill(AO_EE_CONFIG_BLOCK);
 333                 memcpy(ao_ee_data, buf, len);
 334                 ao_ee_block_dirty = 1;
 335         } ao_mutex_put(&ao_ee_mutex);
 336         return 1;
 337 }
 338
 339 uint8_t
 340 ao_ee_read_config(uint8_t *buf, uint16_t len) __reentrant
 341 {
 342         if (len > AO_EE_BLOCK_SIZE)
 343                 return 0;
 344         ao_mutex_get(&ao_ee_mutex); {
 345                 ao_ee_fill(AO_EE_CONFIG_BLOCK);
 346                 memcpy(buf, ao_ee_data, len);
 347         } ao_mutex_put(&ao_ee_mutex);
 348         return 1;
 349 }
 350
 351 /*
 352  * To initialize the chip, set up the CS line and
 353  * the SPI interface
 354  */
 355 void
 356 ao_ee_init(void)
 357 {
 358         /* set up CS */
 359         EE_CS = 1;
 360         P1DIR |= (1 << EE_CS_INDEX);
 361         P1SEL &= ~(1 << EE_CS_INDEX);
 362
 363         /* Set up the USART pin assignment */
 364         PERCFG = (PERCFG & ~PERCFG_U0CFG_ALT_MASK) | PERCFG_U0CFG_ALT_2;
 365
 366         /* Ensure that USART0 takes precidence over USART1 for pins that
 367          * they share
 368          */
 369         P2SEL = (P2SEL & ~P2SEL_PRI3P1_MASK) | P2SEL_PRI3P1_USART0;
 370
 371         /* Make the SPI pins be controlled by the USART peripheral */
 372         P1SEL |= ((1 << 5) | (1 << 4) | (1 << 3));
 373
 374         /* Set up OUT DMA */
 375         ao_ee_dma_out_id = ao_dma_alloc(&ao_ee_dma_out_done);
 376
 377         /* Set up IN DMA */
 378         ao_ee_dma_in_id = ao_dma_alloc(&ao_ee_dma_in_done);
 379
 380         /* Set up the USART.
 381          *
 382          * SPI master mode
 383          */
 384         U0CSR = (UxCSR_MODE_SPI | UxCSR_RE | UxCSR_MASTER);
 385
 386         /* Set the baud rate and signal parameters
 387          *
 388          * The cc1111 is limited to a 24/8 MHz SPI clock,
 389          * while the 25LC1024 is limited to 20MHz. So,
 390          * use the 3MHz clock (BAUD_E 17, BAUD_M 0)
 391          */
 392         U0BAUD = 0;
 393         U0GCR = (UxGCR_CPOL_NEGATIVE |
 394                  UxGCR_CPHA_FIRST_EDGE |
 395                  UxGCR_ORDER_MSB |
 396                  (17 << UxGCR_BAUD_E_SHIFT));
 397 }