2 * Copyright © 2009 Keith Packard <keithp@keithp.com>
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
12 * General Public License for more details.
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
23 * Using SPI on USART 0, with P1_2 as the chip select
29 __xdata uint8_t ao_ee_dma_in_done;
30 __xdata uint8_t ao_ee_dma_out_done;
31 __xdata uint8_t ao_ee_mutex;
33 uint8_t ao_ee_dma_out_id;
34 uint8_t ao_ee_dma_in_id;
36 static __xdata uint8_t ao_ee_const = 0xff;
38 #define ao_ee_delay() do { \
44 void ao_ee_cs_low(void)
51 void ao_ee_cs_high(void)
58 /* Send bytes over SPI.
60 * This sets up two DMA engines, one writing the data and another reading
61 * bytes coming back. We use the bytes coming back to tell when the transfer
62 * is complete, as the transmit register is double buffered and hence signals
63 * completion one byte before the transfer is actually complete
66 ao_ee_send(void __xdata *block, uint16_t len)
68 ao_dma_set_transfer(ao_ee_dma_in_id,
73 DMA_CFG0_TMODE_SINGLE |
74 DMA_CFG0_TRIGGER_URX0,
77 DMA_CFG1_PRIORITY_NORMAL);
79 ao_dma_set_transfer(ao_ee_dma_out_id,
84 DMA_CFG0_TMODE_SINGLE |
85 DMA_CFG0_TRIGGER_UTX0,
88 DMA_CFG1_PRIORITY_NORMAL);
90 ao_dma_start(ao_ee_dma_in_id);
91 ao_dma_start(ao_ee_dma_out_id);
92 ao_dma_trigger(ao_ee_dma_out_id);
93 __critical while (!ao_ee_dma_in_done)
94 ao_sleep(&ao_ee_dma_in_done);
97 /* Receive bytes over SPI.
99 * This sets up tow DMA engines, one reading the data and another
100 * writing constant values to the SPI transmitter as that is what
101 * clocks the data coming in.
104 ao_ee_recv(void __xdata *block, uint16_t len)
106 ao_dma_set_transfer(ao_ee_dma_in_id,
110 DMA_CFG0_WORDSIZE_8 |
111 DMA_CFG0_TMODE_SINGLE |
112 DMA_CFG0_TRIGGER_URX0,
115 DMA_CFG1_PRIORITY_NORMAL);
117 ao_dma_set_transfer(ao_ee_dma_out_id,
121 DMA_CFG0_WORDSIZE_8 |
122 DMA_CFG0_TMODE_SINGLE |
123 DMA_CFG0_TRIGGER_UTX0,
126 DMA_CFG1_PRIORITY_NORMAL);
128 ao_dma_start(ao_ee_dma_in_id);
129 ao_dma_start(ao_ee_dma_out_id);
130 ao_dma_trigger(ao_ee_dma_out_id);
131 __critical while (!ao_ee_dma_in_done)
132 ao_sleep(&ao_ee_dma_in_done);
137 struct ao_ee_instruction {
140 } __xdata ao_ee_instruction;
143 ao_ee_write_enable(void)
146 ao_ee_instruction.instruction = EE_WREN;
147 ao_ee_send(&ao_ee_instruction, 1);
155 ao_ee_instruction.instruction = EE_RDSR;
156 ao_ee_send(&ao_ee_instruction, 1);
157 ao_ee_recv(&ao_ee_instruction, 1);
159 return ao_ee_instruction.instruction;
163 ao_ee_wrsr(uint8_t status)
166 ao_ee_instruction.instruction = EE_WRSR;
167 ao_ee_instruction.address[0] = status;
168 ao_ee_send(&ao_ee_instruction, 2);
172 #define EE_BLOCK_NONE 0xffff
174 __xdata uint8_t ao_ee_data[EE_BLOCK];
175 __data uint16_t ao_ee_block = EE_BLOCK_NONE;
176 __data uint8_t ao_ee_block_dirty;
178 /* Write the current block to the EEPROM */
180 ao_ee_write_block(void)
184 status = ao_ee_rdsr();
185 if (status & (EE_STATUS_BP0|EE_STATUS_BP1|EE_STATUS_WPEN)) {
186 status &= ~(EE_STATUS_BP0|EE_STATUS_BP1|EE_STATUS_WPEN);
189 ao_ee_write_enable();
191 ao_ee_instruction.instruction = EE_WRITE;
192 ao_ee_instruction.address[0] = ao_ee_block >> 8;
193 ao_ee_instruction.address[1] = ao_ee_block;
194 ao_ee_instruction.address[2] = 0;
195 ao_ee_send(&ao_ee_instruction, 4);
196 ao_ee_send(ao_ee_data, EE_BLOCK);
199 uint8_t status = ao_ee_rdsr();
200 if ((status & EE_STATUS_WIP) == 0)
205 /* Read the current block from the EEPROM */
207 ao_ee_read_block(void)
210 ao_ee_instruction.instruction = EE_READ;
211 ao_ee_instruction.address[0] = ao_ee_block >> 8;
212 ao_ee_instruction.address[1] = ao_ee_block;
213 ao_ee_instruction.address[2] = 0;
214 ao_ee_send(&ao_ee_instruction, 4);
215 ao_ee_recv(ao_ee_data, EE_BLOCK);
220 ao_ee_flush_internal(void)
222 if (ao_ee_block_dirty) {
224 ao_ee_block_dirty = 0;
229 ao_ee_fill(uint16_t block)
231 if (block != ao_ee_block) {
232 ao_ee_flush_internal();
239 ao_ee_write(uint32_t pos, uint8_t *buf, uint16_t len) __reentrant
245 if (pos >= AO_EE_DATA_SIZE || pos + len > AO_EE_DATA_SIZE)
249 /* Compute portion of transfer within
253 this_len = 256 - (uint16_t) this_off;
254 block = (uint16_t) (pos >> 8);
257 if (this_len & 0xff00)
258 ao_panic(AO_PANIC_EE);
260 /* Transfer the data */
261 ao_mutex_get(&ao_ee_mutex); {
265 ao_ee_flush_internal();
268 memcpy(ao_ee_data + this_off, buf, this_len);
269 ao_ee_block_dirty = 1;
270 } ao_mutex_put(&ao_ee_mutex);
272 /* See how much is left */
280 ao_ee_read(uint32_t pos, uint8_t *buf, uint16_t len) __reentrant
286 if (pos >= AO_EE_DATA_SIZE || pos + len > AO_EE_DATA_SIZE)
290 /* Compute portion of transfer within
294 this_len = 256 - (uint16_t) this_off;
295 block = (uint16_t) (pos >> 8);
298 if (this_len & 0xff00)
299 ao_panic(AO_PANIC_EE);
301 /* Transfer the data */
302 ao_mutex_get(&ao_ee_mutex); {
304 memcpy(buf, ao_ee_data + this_off, this_len);
305 } ao_mutex_put(&ao_ee_mutex);
307 /* See how much is left */
315 ao_ee_flush(void) __reentrant
317 ao_mutex_get(&ao_ee_mutex); {
318 ao_ee_flush_internal();
319 } ao_mutex_put(&ao_ee_mutex);
323 * Read/write the config block, which is in
324 * the last block of the ao_eeprom
327 ao_ee_write_config(uint8_t *buf, uint16_t len) __reentrant
329 if (len > AO_EE_BLOCK_SIZE)
331 ao_mutex_get(&ao_ee_mutex); {
332 ao_ee_fill(AO_EE_CONFIG_BLOCK);
333 memcpy(ao_ee_data, buf, len);
334 ao_ee_block_dirty = 1;
335 } ao_mutex_put(&ao_ee_mutex);
340 ao_ee_read_config(uint8_t *buf, uint16_t len) __reentrant
342 if (len > AO_EE_BLOCK_SIZE)
344 ao_mutex_get(&ao_ee_mutex); {
345 ao_ee_fill(AO_EE_CONFIG_BLOCK);
346 memcpy(buf, ao_ee_data, len);
347 } ao_mutex_put(&ao_ee_mutex);
352 * To initialize the chip, set up the CS line and
360 P1DIR |= (1 << EE_CS_INDEX);
361 P1SEL &= ~(1 << EE_CS_INDEX);
363 /* Set up the USART pin assignment */
364 PERCFG = (PERCFG & ~PERCFG_U0CFG_ALT_MASK) | PERCFG_U0CFG_ALT_2;
366 /* Ensure that USART0 takes precidence over USART1 for pins that
369 P2SEL = (P2SEL & ~P2SEL_PRI3P1_MASK) | P2SEL_PRI3P1_USART0;
371 /* Make the SPI pins be controlled by the USART peripheral */
372 P1SEL |= ((1 << 5) | (1 << 4) | (1 << 3));
375 ao_ee_dma_out_id = ao_dma_alloc(&ao_ee_dma_out_done);
378 ao_ee_dma_in_id = ao_dma_alloc(&ao_ee_dma_in_done);
384 U0CSR = (UxCSR_MODE_SPI | UxCSR_RE | UxCSR_MASTER);
386 /* Set the baud rate and signal parameters
388 * The cc1111 is limited to a 24/8 MHz SPI clock,
389 * while the 25LC1024 is limited to 20MHz. So,
390 * use the 3MHz clock (BAUD_E 17, BAUD_M 0)
393 U0GCR = (UxGCR_CPOL_NEGATIVE |
394 UxGCR_CPHA_FIRST_EDGE |
396 (17 << UxGCR_BAUD_E_SHIFT));