stm32f1x: use async algorithm in flash programming routine
Let the target algorithm be running in the background and buffer data
continuously through a FIFO. This reduces or removes the effect of latency
because only a very small number of queue executions needs to be done per
buffer fill. Previously, the many repeated target state changes, register
accesses (really inefficient) and algorithm uploads caused the flash
programming to be latency bound in many cases. Now it should scale better
with increased throughput.
Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
stm32f1x: use register base instead of register offset
Access the different flash banks' registers using a bank specific register
base and a register specific offset. This is equivalent but feels more
natural.
Some accesses were discovered that maybe should not be hard coded to bank0
registers. Add a note about that.
Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Split armv7m_run_algorithm into two pieces and use them to reimplement it.
The arch_info parameter is used to keep context between the two calls, so
both calls must refer to the same armv7m_algorithm struct. Ugly but works
for a proof-of-concept.
Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
target: add async algorithm entries to the target type
On supported targets, this may be used to start a long running algorithm in
the background so the target may be interacted with during execution and
later wait for its completion.
The most obvious use case is a double buffered flash algorithm that can
upload the next block of data while the algorithm is flashing the current.
Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Ash Charles [Fri, 30 Sep 2011 23:17:21 +0000 (16:17 -0700)]
Verdex: Add support for Gumstix Verdex boards.
Gumstix Verdex is a PXA270-based series of computer-on-modules. This
configuration file is based off the voipac.cfg configuration with
a different flash memory configuration. This has been tested flyswatter
adapter to reflash a Gumstix Verdex XL6P board.
The missing value for ES1.2 silicon revision is mentioned in
sprugn4m.pdf, and the recent TI Beagleboard XM is powered by it,
so let support the revision.
Mathias K [Wed, 21 Sep 2011 17:18:26 +0000 (19:18 +0200)]
add target events, run algorithm and default r/w buffer api
Target events are added to get better gdb support. The run
algorithm functionality are implemented to support feature
fast flash write functionality. The new r/w buffer api is now
used to support the special memory address handling. The output
of the md command was fixed.
Luca Bruno [Tue, 13 Sep 2011 13:11:01 +0000 (15:11 +0200)]
contrib: fix udev rules for tty based adaptors
Most serial adaptors are identified by udev with SUBSYSTEM=tty and
without DEVTYPE. This patch fix udev rules to work with any listed
tty-based adaptor. It has been tested with a FTDI-based Bus Pirate.
Mathias K [Mon, 12 Sep 2011 19:24:17 +0000 (21:24 +0200)]
kinetis auto mass erase on secured devices
This is a proof of concept to get access to the debug port of a
secured kinetis cpu. On full flash erase the cpu is automatically
secured and the debug port is not accessible.
To get this to work the srst line is needed and the necessary
configuration should be added to the configuration file.
Richard Uhler [Thu, 25 Aug 2011 20:29:33 +0000 (13:29 -0700)]
Implementation of a new jtag remote_bitbang driver.
The driver sends ascii encoded bitbang commands over unix sockets or TCP to
another process. This driver is useful for debugging software running on
processors which are being simulated.
Martin Schmölzer [Wed, 31 Aug 2011 14:51:41 +0000 (16:51 +0200)]
ULINK driver: Remove typedefs in OpenULINK firmware: Use typedefs from stdint.h (uint8_t, uint16_t) instead of custom typedefs in shorttypes.h (u8, u16, ...)
Signed-off-by: Martin Schmölzer <martin.schmoelzer@student.tuwien.ac.at>
Rodrigo L. Rosa [Wed, 31 Aug 2011 19:32:14 +0000 (12:32 -0700)]
speed up, relocate function
added an attempt to use the non-reseting halting sequence. if it fails, then the full sequence will be attempted. this makes things a bit faster most of the time.
changed the location of a function, avoiding a forward def
Rodrigo L. Rosa [Wed, 31 Aug 2011 04:08:59 +0000 (21:08 -0700)]
fix enter debug mode for locking
added an alternative way to enter debug mode, which does not require restarting the chip.
this will not always work, but in general it will (failure 0.3%), and failure is not a dramatic issue, simply have to use the full sequence.
the user can only access "halt", which uses the full sequence, so the user should not have any problems.
restarting the chip requires reconfiguring the flash module. the doc is very poor, so i'd rather have the two methods, and live with the 0.3%.
Rodrigo L. Rosa [Tue, 30 Aug 2011 21:46:20 +0000 (14:46 -0700)]
fix irlen handling
sometimes the master tap will be enabled, since tap switching is required during halt/lock/unlocking procedures.
now irscan handles this, avoiding unnecessary warnings and preventing errors.
Rodrigo L. Rosa [Tue, 30 Aug 2011 22:13:49 +0000 (15:13 -0700)]
fix debug mode,lock,unlock
got new info regarding setting the chip to debug mode, and locking/unlocking flash memory.
the newer implementation is a bit slower, but always works.
the previous implementation would randomly (as once every 25k-70k times) get the chip into a state where the freescale tool would be necessary. this is fixed now.
added functions to play around with the jtag state machine. they are not the happiest, but are necessary to be able to execute the halting/locking/unlocking sequences.
Rodrigo L. Rosa [Tue, 30 Aug 2011 21:26:05 +0000 (14:26 -0700)]
fix error handling during halt
the user can execute halt, but no enter_debug_mode. modified the error handling to suite this.
the new implementation of unlocking will use enter_debug_mode, and should not get the same errors as the user would, because not being able to enter debug mode is actually success when checking for locked flash.
Rodrigo L. Rosa [Tue, 30 Aug 2011 21:19:09 +0000 (14:19 -0700)]
optional crc for flash writing
crc check was always performed on newly flashed data, now it is optional
flash mem can be locked by writing a specific word to a specific address in flash.
to verify flash, target must be halted, and this will (when the new halt sequence is implemented) require reseting the chip. if the target is reset after writing the lock words, then it will lock, hence the CRC will fail because it is not possible to read stuff from the target.
also added a function that resets the jtag state machine.
this is not used yet, but will be soon.
it is implemented to allow strict control over JTAG state machine, necessary to implement to halt and unlocking sequences.
Jim Paris [Mon, 22 Aug 2011 20:48:14 +0000 (16:48 -0400)]
Fix redbee config files
Currently the board/redbee-*.cfg files incorrectly include the
interface definition. Move the interfaces to interface/,
and create a single board/redbee.cfg that is common to both boards.
Intended usage is now:
openocd -f interface/redbee-econotag.cfg -f board/redbee.cfg
Spencer Oliver [Wed, 10 Aug 2011 21:23:29 +0000 (22:23 +0100)]
ftd2xx: fix build warnings
Due to build warnings introduced in newer versions of ftd2xx we
use strings to report errors rather than result codes. This also
gives us the same behaviour as libftdi.
Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
Rodrigo L. Rosa [Fri, 5 Aug 2011 18:38:12 +0000 (11:38 -0700)]
renamed for clarity
i had started my code from dsp5683xx, i renamed a bunch of stuff to names i consider to be better.
i believe no one is using this code, so nobody should be affected. (it's not too late to do this change)
After correcting the reply size counter, it should be safe to rely on it
for the number of bytes expected in the USB read, instead of reading the
endpoint maximum. This doesn't make things go any faster but it's nicer and
removes the local buffer.
Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
rlink: simplify and optimize queue fill level checks
Add a helper function for running the queue if it would overflow otherwise.
Use it to simplify the queue fill level checks and optimize in a few cases
that would previously run the queue prematurely.
Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
rlink: fix reply counter to enable sending full buffers
dtc_queue.reply_index was wrongly being increased during out scans, causing
the queue to be sent before the out buffer was full. This patch increases
raw upload speed by 50% or so.
Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Function mips_m4k_write_memory() does endianess byte swap,
but this procedure break one byte access (temporary array
overwrites content in buffer).
As a fix, this endianess swap and buffer affecting
is preformed only on hword and word accesses (not on byte access).
mips32: Sync Caches to Make Instr Writes Effective
Pprogram that loads another program into memory is actually writing the
D- side cache.
The instructions it has loaded can't be executed until they reach the
I-cache.
After the instructions have been written, the loader should arrange to
write back any containing D-cache line and invalidate any locations
already in the I-cache.
For the MIPS Architecture Release2 cores, we can use synci command
that does this job.
For Release1 we must use "cache" instruction.
projects / fw / openocd / log