Nishanth Menon [Sat, 2 Oct 2021 03:48:34 +0000 (22:48 -0500)]
tcl/target/ti_k3: Add a gdb-attach event hook for m3 and m4
Add gdb-attach event to call the "up" function of m3 and m4 allowing for
more seamless integration with gdb for end users. We still retain _up
functions for non-gdb functionality.
NOTE: we add a halt 1000 to retain the default gdb-attach hook behavior
Suggested-by: Antonio Borneo <borneo.antonio@gmail.com> Signed-off-by: Nishanth Menon <nm@ti.com>
Change-Id: I2e51fdbd8756f156551e589c748c3a338afa655c
Reviewed-on: https://review.openocd.org/c/openocd/+/6615 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
The current implementation crashes when executing 'tpiu create'
without an object name due to an invalid memory access. Pass 'argv'
instead 'goi.argv' to fix the problem.
While at it, match the style of the error message to the style used for
other Tcl commands. Especially, make the 'name' parameter mandatory.
Change-Id: Ib2b233f8556934af61608ae93d6405585c2c40b7 Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: https://review.openocd.org/c/openocd/+/6329 Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Tested-by: jenkins
Antonio Borneo [Sat, 19 Feb 2022 15:56:42 +0000 (16:56 +0100)]
gdb_server: check target examined while combining reg list
Commit 6541233aa78d ("Combine register lists of smp targets.")
assumes that all the targets in the SMP cluster are already
examined and unconditionally call target_get_gdb_reg_list_noread()
that will in turn return error if the target is not examined yet.
Skip targets not examined yet.
Add an additional check in case the register list cannot be built,
e.g. because no target in the SMP cluster is examined. This should
never happen, but it's better to play safe.
Change-Id: I8609815c3d5144790fb05a870cb0c931540aef8a Fixes: 6541233aa78d ("Combine register lists of smp targets.") Reported-by: Michele Bisogno <michele.bisogno.ct@renesas.com> Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6853 Tested-by: jenkins Reviewed-by: Michele Bisogno <michele.bisogno.ct@renesas.com> Reviewed-by: Tim Newsome <tim@sifive.com>
Antonio Borneo [Sat, 19 Feb 2022 15:16:31 +0000 (16:16 +0100)]
gdb_server: fix double free
Commit 6541233aa78d ("Combine register lists of smp targets.")
unconditionally assigns the output pointers of the function
smp_reg_list_noread(), even if the function fails and returns
error.
This causes a double free from the caller, that has assigned NULL
to the pointers to simplify the error handling.
Use local variables in smp_reg_list_noread() and assign the output
pointers only on success.
Change-Id: Ic0fd2f26520566cf322f0190780e15637c01cfae Fixes: 6541233aa78d ("Combine register lists of smp targets.") Reported-by: Michele Bisogno <michele.bisogno.ct@renesas.com> Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6852 Tested-by: jenkins Reviewed-by: Michele Bisogno <michele.bisogno.ct@renesas.com> Reviewed-by: Tim Newsome <tim@sifive.com>
Sean Anderson [Fri, 11 Feb 2022 22:50:09 +0000 (17:50 -0500)]
board: Add NXP LS1088ARDB
This adds a board file for the NXP LS1088ARDB. This only covers the
"primary" JTAG header J55, and not the PCIe header (J91). The only
oddity is that the LS1088A and CPLD are muxed by adding/removing a
jumper from J48. Unfortunately, it doesn't look like OpenOCD supports
this CPLD beyond determining the irlen, so it's not very useful. Those
who are interested in experimenting can define CWTAP to access the CPLD,
but the default is to access the CPU.
Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Change-Id: Ia07436a534f86bd907aa5fe2a78a326a27855a24
Reviewed-on: https://review.openocd.org/c/openocd/+/6849 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Sean Anderson [Mon, 14 Feb 2022 22:53:11 +0000 (17:53 -0500)]
target: ls1088a: Add service processor
Normally the service processor is not necessary for debugging. However,
if you are using the hard-coded RCW or your boot source is otherwise
corrupt, then the general purpose processors will never be released from
hold-off. This will cause GDB to become confused if it tries to attach,
since they will appear to be running arm32 processors. To deal with
this, we can release the CPUs manually with the BRRL register. This
register cannot be written to from the axi target, so we need to do it
from the service processor target. This involves halting the service
processor, modifying the register, and then resuming it again. We try
and determine what state the service processor was in to avoid resuming
it if it was already halted.
The reset vector for the general purpose processors is determined by the
boot logation pointer registers in the device configuration unit.
Normally these are set using pre-boot initialization commands, but if
they are not set then they default to 0. This will cause the CPU to
almost immediately hit an illegal instruction. This is fine because we
will almost certainly want to attach to the processor and load a program
anyway.
I considered adding this as an event handler for either gdb-attach or
reset-init. However, this command shouldn't be necessary most of the
time, and so I don't think we should run it automatically.
Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Change-Id: I1b725292d8a11274d03af5313dc83678e10e944c
Reviewed-on: https://review.openocd.org/c/openocd/+/6850 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Sean Anderson [Fri, 11 Feb 2022 22:45:32 +0000 (17:45 -0500)]
target: Add support for ls1088a
The LS1088A is an octo-core aarch64 processor from NXP in the layerscape
family. The JTAG is undocumented, but I was able to figure things out
from the output of `dap info`. This is the first in-tree example of
using the hwthread rtos (as far as I know), so hopefully it can serve as
an example to other developers. There are some ETMs, but I was unable to
try them out because I got 'invalid command name "etm"' when trying to
test things out.
Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Change-Id: I9b0791d27d8c41170a413a8d86431107a85feba2
Reviewed-on: https://review.openocd.org/c/openocd/+/6848 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Sean Anderson [Fri, 11 Feb 2022 22:43:30 +0000 (17:43 -0500)]
cpld: altera-epm240: Increase adapter speed
According to the datasheet, the minimum clock period with Vccio1 = 1.5V
(the lowest voltage supported) is 143ns, or around 6MHz. Set the default
adapter speed to 5 MHz.
Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Change-Id: I21cad33fa7f1e25e81f43b5d2214d1fa4ec924de
Reviewed-on: https://review.openocd.org/c/openocd/+/6847 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Sean Anderson [Fri, 11 Feb 2022 22:40:24 +0000 (17:40 -0500)]
cpld: altera-epm240: Add additional IDCODEs
This adds some additional IDCODEs from the datasheet. It also adds
support for customizing the tap name.
Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Change-Id: I7cda10b92c229b61836c12cd9ca410de358ede2e
Reviewed-on: https://review.openocd.org/c/openocd/+/6846 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tomas Vanek [Thu, 25 Nov 2021 05:24:52 +0000 (06:24 +0100)]
flash/nor/stm32xx: fix segfault accessing Cortex-M part number
Some of STM32 flash drivers read Cortex-M part number from
cortex_m->core_info.
In corner cases the core_info pointer was observed uninitialised
even if target_was_examined() returned true. See also [1]
Use the new and safe helper to get Cortex-M part number.
While on it switch also target_to_cm()/target_to_armv7m() to the safe
versions. This prevents a crash when the flash bank is misconfigured
with non-Cortex-M target.
Add missing checks for target_was_examined() to flash probes.
[1] 6545: fix crash in case cortex_m->core_info is not set
https://review.openocd.org/c/openocd/+/6545
Change-Id: If2471af74ebfe22f14442f48ae109b2e1bb5fa3b Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Fixes: f5898bd93ff8 (flash/stm32fxx.c: do not read CPUID as this info is stored in cortex_m_common)
Reviewed-on: https://review.openocd.org/c/openocd/+/6752 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Simon Johansson [Mon, 17 Jan 2022 12:30:59 +0000 (13:30 +0100)]
flash/nor/stm32f2x: Fix erase of bank 2 sectors
This commit corrects the erase function for stm32f2x when dealing with
sectors in bank 2, for STM32F42x/43x devices with 1MB flash.
On STM32F42x/43x with 1MB flash in dual bank configuration, the sector
numbering is not consecutive. The last sector in bank 1 is number 7, and
the first sector in bank 2 is number 12.
The sector indices used by openocd, however, _are_ consecutive (0 to 15
in this case). The arguments "first" and "last" to stm32x_erase() are of
this type, and so the logic surrounding sector numbers needed to be
corrected.
Since the two banks in dual bank mode have the same number of sectors, a
sector index in bank 2 is larger than or equal to half the total number
of sectors.
Change-Id: I15260f8a86d9002769a1ae1c40ebdf62142dae18 Signed-off-by: Simon Johansson <ampleyfly@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6810 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Antonio Borneo [Wed, 2 Feb 2022 12:46:46 +0000 (13:46 +0100)]
.gitmodules: switch away from repo.or.cz
The host repo.or.cz is often offline, creating issues for cloning
and building OpenOCD from scratch.
Already 'jimtcl' developer has dropped repo.or.cz, triggering the
OpenOCD commit 861e75f54efb ("jimtcl: switch to github").
Change also the link of the remaining submodules 'git2cl' and
'libjaylink' to their respective main repository.
Antonio Borneo [Wed, 2 Feb 2022 22:55:50 +0000 (23:55 +0100)]
server: remove remaining crust from dropped eCos code
Commit 39650e2273bc ("ecosboard: delete bit-rotted eCos code") has
removed eCos code but has left some empty function that was used
during non-eCos build to replace eCos mutex.
Drop the functions and the file that contain them.
Change-Id: I31bc0237ea699c11bd70921660f960ee406ffa80 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6835 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Tim Newsome [Thu, 16 Dec 2021 11:54:35 +0000 (12:54 +0100)]
target/riscv: revive 'riscv resume_order'
This functionality was lost in [1], which was merged as commit 615709d14049 ("Upstream a whole host of RISC-V changes.").
Now it works as expected again.
Antonio Borneo [Thu, 16 Dec 2021 00:59:14 +0000 (01:59 +0100)]
target/smp: use a struct list_head to hold the smp targets
Instead of reinventing a simply linked list, reuse the list helper
for the list of targets in a smp cluster.
Using the existing helper, that implements a double linked list,
makes trivial going through the list in reverse order.
Change-Id: Ib36ad2955f15cd2a601b0b9e36ca6d948b12d00f Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6783 Tested-by: jenkins
Zoltán Dudás [Wed, 24 Nov 2021 16:13:50 +0000 (17:13 +0100)]
semihosting: User defined operation, Tcl command exec on host
Enabling a portion (0x100 - 0x107) of the user defined semihosting
operation number range (0x100 - 0x1FF) to be processed with the help of
the existing target event mechanism, to implement a general-purpose Tcl
interface for the target available on the host, via semihosting
interface.
Example usage:
- The user configures a Tcl command as a callback for one of the newly
defined events (semihosting-user-cmd-0x10X) in the configuration
file.
- The target can make a semihosting call with <opnum>, passing optional
parameters for the call.
If there is no callback registered to the user defined operation number,
nothing happens.
Example usage: Configure RTT automatically with the exact, linked
control block location from target.
Signed-off-by: Zoltán Dudás <zedudi@gmail.com>
Change-Id: I10e1784b1fecd4e630d78df81cb44bf1aa2fc247
Reviewed-on: https://review.openocd.org/c/openocd/+/6748 Tested-by: jenkins Reviewed-by: Oleksij Rempel <linux@rempel-privat.de> Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Pavel Kirienko [Sun, 9 Jan 2022 21:18:13 +0000 (23:18 +0200)]
semihosting: use open mode flags from GDB, not from sys/stat.h
Values defined in sys/stat.h are not guaranteed to match
the constants defined by the GDB remote protocol, which are defined in
https://sourceware.org/gdb/onlinedocs/gdb/Open-Flags.html#Open-Flags.
On my local system (Manjaro 21.2.1 x86_64), for example, O_TRUNC is
defined as 0x40, whereas GDB requires it to be 0x400,
causing all "w" file open modes to misbehave.
This patch has been tested with STM32F446.
Change-Id: Ifb2c740fd689e71d6f1a4bde1edaecd76fdca910 Signed-off-by: Pavel Kirienko <pavel.kirienko@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6804 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tim Newsome [Fri, 9 Jul 2021 00:43:00 +0000 (17:43 -0700)]
Combine register lists of smp targets.
This is helpful when you want to pretend to gdb that your heterogeneous
multicore system is homogeneous, because gdb cannot handle heterogeneous
systems. This won't always works, but works fine if e.g. one of the
cores has an FPU while the other does not. (Specifically, HiFive
Unleashed has 1 core with no FPU, plus 4 cores with an FPU.)
Signed-off-by: Tim Newsome <tim@sifive.com>
Change-Id: I05ff4c28646778fbc00327bc510be064bfe6c9f0
Reviewed-on: https://review.openocd.org/c/openocd/+/6362 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Adrien Grassein [Thu, 6 Jan 2022 18:06:47 +0000 (19:06 +0100)]
jtag: Add an option to ignore the bypass bit
Some CPU wrongly indicate the bypas bit in the codeid.
It's the case of the NanoXplore NG-ULTRA chip that export a
configurable (and potentially invalid) ID for one of
its component.
Add an option to ignore it.
Antonio Borneo [Fri, 24 Dec 2021 14:15:18 +0000 (15:15 +0100)]
log: fix memory leak when log to file is enabled
When log to file is enabled, the file is not closed by OpenOCD at
exit. This is reported by Valgrind as a memory leak that is still
reachable, as the internal buffers of 'FILE *log_output' are freed
by the automatic fclose() at exit.
Close the log file before exit.
Change-Id: Id472c0d04462035254a9b49ecb0a4037263c6f6f Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6789 Tested-by: jenkins
Antonio Borneo [Wed, 12 Jan 2022 16:59:12 +0000 (17:59 +0100)]
doc: use the new jimtcl syntax for 'expr'
With jimtcl 0.81 the syntax of the TCL command 'expr' requires the
multiple arguments to be within curly brackets.
Update the examples in the documentation to follow the new syntax.
While there, split one example to avoid it to exceed the line size
during pdf document generation.
Change-Id: I91cca419f8273415ccb0c2ce369fc6ac476e34e5 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6809 Tested-by: jenkins
Doug Brunner [Mon, 25 Oct 2021 17:15:07 +0000 (10:15 -0700)]
flash/nor/efr32: fixed lockbits and user data
Changed flash driver to support writing to the user data page, as well as to any portion of the lockbits page above 512 bytes (the amount used for the actual page lock words). The top part of the lockbits page is used on at least the EFR32xG1 chips for the SiLabs bootloader encryption keys.
As presented to the user, the lockbits page is the same size as the other pages, but any attempt to write to its low 512 bytes is an error. To enforce this, efr32x_write is renamed to efm32x_priv_write and a wrapper function is provided in its place. If the user erases the lockbits page, the driver rewrites the cached lock words after the erase. When the driver erases the lockbits page in order to update the lock words, it first takes a copy of anything stored in the top part of the page, and re-programs it after the erase operation.
There are now multiple instances of flash_bank for each target, and the flash_bank instances must share their cached lock words to operate as intended. Therefore, when a bank is created, the global flash bank list is used to find any other banks that share the same target. Since some banks in the global list are invalid at the time free_driver_priv is called, reference counting is used to decide when to free driver_priv.
To avoid the need to find the lockbits flash_bank from another flash_bank, efm32x_priv_write and efm32x_erase_page now take an absolute address.
There didn't seem to be any reason to prohibit unprotecting individual flash pages, so that limitation is removed from efm32x_protect().
This addresses ticket #185.
Valgrind-clean, except for 2x 4kiB not freed/still reachable blocks that were allocated by libudev.
No new Clang analyzer warnings, no new sanitizer warnings.
Signed-off-by: Doug Brunner <doug.a.brunner@gmail.com>
Change-Id: Ifb22e6149939d893f386706e99b928691ec1d41b
Reviewed-on: https://review.openocd.org/c/openocd/+/6665 Tested-by: jenkins Reviewed-by: Fredrik Hederstierna <fredrik.hederstierna@gmail.com> Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Tim Newsome [Tue, 2 Nov 2021 16:55:07 +0000 (09:55 -0700)]
target/riscv: calloc() memory per register.
This replaces a static array with 8 bytes per register. When there are
vector registers larger than 8 bytes, they would end up clobbering each
other's values. I can't believe I didn't catch this earlier.
See https://github.com/riscv/riscv-openocd/pull/658
Change-Id: I9df4eaf05617a2c8df3140fff9fe53f61ab2b261 Signed-off-by: Tim Newsome <tim@sifive.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6775 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Antonio Borneo [Sat, 4 Dec 2021 17:38:56 +0000 (18:38 +0100)]
gdb_server: fix a comment in gdb_new_connection()
On 2008-03-05, before git's age, commit 6d9501467441 adds a
comment about unobserved ACK supposedly sent by GDB at connection.
The ACK is sent since GDB 3.95 (1999-05-04), but a bug introduced
in GDB 6.5 (2006-06-21) and fixed in GDB 7.0 (2009-10-06) makes
GDB sending the query for "supported packets" before sending the
ACK. Due to the bug, the author of the commit failed to see the
ACK.
Change-Id: I574a8013e7d159d1c71087af83b7c2ce92be86bd Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6769 Tested-by: jenkins
Tomas Vanek [Wed, 8 Dec 2021 21:11:32 +0000 (22:11 +0100)]
target/cortex_m: minor refactoring in cortex_m_store_core_reg_u32()
Unlike cortex_m_load_core_reg_u32() storing core register uses
the same code pattern around DHCSR read as offered by the convenience
helper cortex_m_read_dhcsr_atomic_sticky().
Use the helper.
Change-Id: Ia947204944a8b549f3c2be7fb2f717aad18970c4
SeeAlso: 65d762918328 (cortex_m: poll S_REGRDY on register r/w)
SeeAlso: 0dcf95c7171b (target/cortex_m: cumulate DHCSR sticky bits) Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/6767 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Bohdan Tymkiv [Thu, 2 Dec 2021 08:08:33 +0000 (10:08 +0200)]
target/arm_jtag.h: fix wrong comparison in arm_jtag_set_instr
Change [1] introduced a regression that results in comparison
in arm_jtag_set_instr() to be always true if the length of the
IR register is not 8 bit. The value on the left side
of the != operator contains only tap->ir_length number of
bits while value on the right is full 8-bit instruction code.
This forces OpenOCD to update the JTAG IR register on each
transaction even if the instruction in the JTAG IR register
is correct. This causes noticeable performance degradation,
especially with slow JTAG adapters.
Laszlo Sitzer [Thu, 18 Nov 2021 12:10:39 +0000 (13:10 +0100)]
linuxgpiod: Allow using multiple GPIO chips.
Allow passing optional gpiochip number before gpio number.
If no optional chip number is passed, the one from the 'gpiochip'
configuration directive is used.
Joerg Wunsch [Tue, 23 Nov 2021 19:49:30 +0000 (20:49 +0100)]
Add Microchip SAME51 Curiosity Nano board
This board is (software wise) similar to the existing SAME54 Xplained
Pro board, with just a slightly different MCU. (Hardware wise, it
features a vastly different form factor.)
Signed-off-by: Jörg Wunsch <openocd@uriah.heep.sax.de>
Change-Id: I5e5435d49d333fb74471994ee84de59ed983153c
Reviewed-on: https://review.openocd.org/c/openocd/+/6747 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-by: Axel W. Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Jan Matyas [Mon, 22 Nov 2021 09:16:27 +0000 (10:16 +0100)]
doc: Update doc for commands "riscv expose_csrs" and "riscv expose_custom"
These commands were extended/improved in the last drop
of RISC-V target updates. Update also the documentation
to properly describe how the commands should be used now.
Change-Id: I9e2ba6adbe1a4c032b96f5f8ff2d4791fa4c2527 Signed-off-by: Jan Matyas <matyas@codasip.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6738 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-by: Tim Newsome <tim@sifive.com>
Yasushi SHOJI [Sun, 21 Nov 2021 23:48:26 +0000 (08:48 +0900)]
doc/openocd.texi: Document find and ocd_find command
Document both find and ocd_find command under Config File Guidelines
-> Interface Config Files. find command is used in the previous
section as well but the previous section is more about using OpenOCD.
The section added is "aimed at any user who needs to write a config
file".
Yasushi SHOJI [Sun, 21 Nov 2021 23:23:32 +0000 (08:23 +0900)]
doc/openocd.texi: Document command mode command
Document "command mode" command Server Configuration -> Configuration
Stage. The text is taken from command's help string.
In addition to the help string, this commit explain the words
mismatch, the doc uses "stage" but the command and source code uses
"mode" to describe the same thing.
Antonio Borneo [Thu, 11 Nov 2021 22:28:33 +0000 (23:28 +0100)]
adi_v5_swd: add jtag-to-swd through dormant
ARM IHI 0031A does not support SWJ-DP, so no switch between JTAG
and SWD is considered.
ARM IHI 0031B is not publicly available and it's reported as
"Confidential Beta" in the history list in following doc versions.
From ARM IHI 0031C the direct switch between JTAG and SWD is
already deprecated in favor of passing through dormant mode. With
no access to IHI 0031B we haven't info if any device strictly
requires the direct switch.
OpenOCD implements only the deprecated direct switch, so changing
it could cause regression on devices that do not implement dormant
mode.
Plus, not all the adapters support dormant mode.
Nevertheless there are already target devices that only allow
entering in SWD by passing through dormant.
Let the code try both method, alternating one tentative with the
deprecated legacy direct switch, then another tentative passing
through dormant, and repeat till timeout.
This would work on any device that don't support dormant, on new
devices that require switch through dormant and will work with
adapters that don't support dormant.
Change-Id: Ib8619635277d497872079a33fa4e38be9beb84a0 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6695 Tested-by: jenkins
Antonio Borneo [Thu, 11 Nov 2021 22:11:03 +0000 (23:11 +0100)]
cortex_m: remove last references to debugport_init()
The function debugport_init() has never existed in OpenOCD code,
but few comments erroneously references it in place of the
existing function ahbap_debugport_init().
Commit 00dbc185ee56 ("arm_adi_v5: Split ahbap_debugport_init")
splits the function ahbap_debugport_init() in dap_dp_init() and
mem_ap_init(), but did not removed all the incorrect comments
about debugport_init(). Few of such comments has been removed in
later patches.
Remove the last comment that references debugport_init().
Change-Id: Ibd1f125475386e5653340fedf706903a0ee15897 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6694 Tested-by: jenkins
Tim Newsome [Mon, 8 Nov 2021 17:26:51 +0000 (09:26 -0800)]
flash/nor/fespi: algorithm, large address, errors
* Move more smarts into the target algorithm code, and rewrite that in C
so it's easier to understand/maintain.
* Support >24-bit addresses.
* Check for errors.
Change-Id: I3b1a143589fe6defafb8f95820aa682acc9646e7 Signed-off-by: Tim Newsome <tim@sifive.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6679 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Antonio Borneo [Tue, 19 Oct 2021 11:09:25 +0000 (13:09 +0200)]
drivers: call adapter_get_required_serial() in jtag_libusb_open()
Now that adapter serial is handled independently from the adapter
drivers, move inside jtag_libusb_open() the call to
adapter_get_required_serial(), so every adapter that uses libusb
will automagically get USB serial support.
Extend the documentation to list the adapters involved.
Change-Id: I75b3482d38f8ed3418329f3106c5e8b689fd460b Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6663 Tested-by: jenkins
Antonio Borneo [Fri, 8 Oct 2021 10:37:19 +0000 (12:37 +0200)]
jtag/hla, jtag/stlink: switch to command 'adapter serial'
The driver hla defines the command 'hla_serial' to specify the
serial string of the adapter.
The driver st-link defines the command 'st-link serial' to specify
the serial string of the adapter.
Remove and deprecate the driver commands and use 'adapter serial'.
Change-Id: I9505c398a77125b1ebf4ba71da7baf4d663b75be Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6657 Tested-by: jenkins
Antonio Borneo [Fri, 8 Oct 2021 09:53:56 +0000 (11:53 +0200)]
jtag/jlink: switch to command 'adapter serial'
The driver jlink defines the command 'jlink serial' to specify the
serial string of the adapter.
Remove and deprecate the driver command, and use 'adapter serial'.
Note: in former code the commands 'jlink serial' and 'jlink usb'
were mutually exclusive; running one of them would invalidate the
effect of a previous execution of the other. The new code gives
priority to 'adapter serial', even if executed before 'jlink usb'.
Antonio Borneo [Thu, 7 Oct 2021 21:03:23 +0000 (23:03 +0200)]
jtag/xds110: switch to command 'adapter serial'
The driver xds110 defines the command 'xds110 serial' to specify
the serial string of the adapter.
Remove and deprecate the driver command, and use 'adapter serial'.
Note: the original command 'xds110 serial' used a complex and
undocumented conversion of the serial number through multibyte
string, wide-character string and C cast. The XDS110 I can access
and the lsusb dumps available through Google don't show any
exotic USB serial that require such conversion. The original
developer doesn't remember any constraint that mandates such
conversion (see comments in https://review.openocd.org/4322/).
The conversion is removed by this patch.
Change-Id: I38909918079b2c1797ad85ebec2fea1b33743606 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6655 Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Tested-by: jenkins
Antonio Borneo [Thu, 18 Nov 2021 10:30:08 +0000 (11:30 +0100)]
doc: remove non-existing command swd wcr
The commands has been dropped in commit 150b7d26f213 ("arm_adi_v5:
Update DP (Debug Port) registers defined in ADIv5.2.") but the
documentation still keeps it.
Remove it!
Change-Id: I4e88f481d943f064d919f8065562052244122bf0 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Fixes: 150b7d26f213 ("arm_adi_v5: Update DP (Debug Port) registers defined in ADIv5.2.")
Reviewed-on: https://review.openocd.org/c/openocd/+/6722 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
The command was proposed in http://review.openocd.org/#/c/4578/2
and dropped in favor on existing work area commands.
Nevertheless the command landed in documentation.
Remove it!
Change-Id: I6e18124256f29be15d8593c07d96f61d19e983f8 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Fixes: a51ab8ddf63a ("Add RISC-V support.")
Reviewed-on: https://review.openocd.org/c/openocd/+/6721 Tested-by: jenkins Reviewed-by: Jan Matyas <matyas@codasip.com>