target: ls1088a: Add service processor

Normally the service processor is not necessary for debugging. However,
if you are using the hard-coded RCW or your boot source is otherwise
corrupt, then the general purpose processors will never be released from
hold-off. This will cause GDB to become confused if it tries to attach,
since they will appear to be running arm32 processors. To deal with
this, we can release the CPUs manually with the BRRL register. This
register cannot be written to from the axi target, so we need to do it
from the service processor target. This involves halting the service
processor, modifying the register, and then resuming it again. We try
and determine what state the service processor was in to avoid resuming
it if it was already halted.

The reset vector for the general purpose processors is determined by the
boot logation pointer registers in the device configuration unit.
Normally these are set using pre-boot initialization commands, but if
they are not set then they default to 0. This will cause the CPU to
almost immediately hit an illegal instruction. This is fine because we
will almost certainly want to attach to the processor and load a program
anyway.

I considered adding this as an event handler for either gdb-attach or
reset-init. However, this command shouldn't be necessary most of the
time, and so I don't think we should run it automatically.

Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Change-Id: I1b725292d8a11274d03af5313dc83678e10e944c
Reviewed-on: https://review.openocd.org/c/openocd/+/6850
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>

diff --git a/tcl/target/ls1088a.cfg b/tcl/target/ls1088a.cfg
index 136ee77a3d52f13a95c45f1413dddca9a22715a6..f9ae9a134ad6774d95c9e86ed21624ef64c8062b 100644 (file)
--- a/tcl/target/ls1088a.cfg
+++ b/tcl/target/ls1088a.cfg
@@ -36,6 +36,38 @@ for {set i 0} {$i < 8} {incr i} {
 
 target smp {*}$_TARGETS
 
+# Service processor
+target create $_CHIPNAME.sp cortex_a -dap $_CHIPNAME.dap -ap-num 0 -dbgbase 0x80138000
+
+# Normally you will not need to call this, but if you are using the hard-coded
+# Reset Configuration Word (RCW) you will need to call this manually. The CPU's
+# reset vector is 0, and the boot ROM at that location contains ARMv7-A 32-bit
+# instructions. This will cause the CPU to almost immediately execute an
+# illegal instruction.
+#
+# This code is idempotent; releasing a released CPU has no effect, although it
+# will halt/resume the service processor.
+add_help_text release_cpu "Release a cpu which is held off"
+proc release_cpu {cpu} {
+       set RST_BRRL 0x1e60060
+
+       set old [target current]
+       targets $::_CHIPNAME.sp
+       set not_halted [string compare halted [$::_CHIPNAME.sp curstate]]
+       if {$not_halted} {
+               halt
+       }
+
+       # Release the cpu; it will start executing something bogus
+       mem2array regs 32 $RST_BRRL 1
+       mww $RST_BRRL [expr {$regs(0) | 1 << $cpu}]
+
+       if {$not_halted} {
+               resume
+       }
+       targets $old
+}
+
 targets $_CHIPNAME.cpu0
 
 # Seems to work OK in testing