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make sure all silk elements are within pcb outline
[hw/lipocharger]
/
lipocharger.pcb
2010-11-23
Bdale Garbee
make sure all silk elements are within pcb outline
fab-v0.1
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2010-11-23
Bdale Garbee
tweaking silk and attributes
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2010-11-18
Bdale Garbee
new footprint for the IC with vias, DRC clean again
origin/master
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2010-11-18
Bdale Garbee
add explicit netlist connection for exposed ground...
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2010-11-18
Bdale Garbee
move vias outside the battery connector pads
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2010-11-11
Bdale Garbee
fix layout name
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2010-11-11
Bdale Garbee
fix DFM identified soldermask issues
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2010-11-11
Bdale Garbee
tweaks based on freedfm.com output
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2010-11-05
Bdale Garbee
ground prog2, fatten supply and output traces
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2010-11-05
Bdale Garbee
enabling outline layer causes bogus drc errors, so...
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2010-11-04
Bdale Garbee
initial capture of LiPo charger
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