+C 46800 50900 1 90 0 resistor.sym
+{
+T 46400 51200 5 10 0 0 90 0 1
+device=RESISTOR
+T 46800 51400 5 10 1 1 0 0 1
+refdes=R1
+T 46800 51100 5 10 1 1 0 0 1
+value=100k
+T 46800 50900 5 10 0 1 0 0 1
+footprint=0402
+}
+C 47500 50900 1 90 0 resistor.sym
+{
+T 47100 51200 5 10 0 0 90 0 1
+device=RESISTOR
+T 47500 51400 5 10 1 1 0 0 1
+refdes=R2
+T 47500 51100 5 10 1 1 0 0 1
+value=100k
+T 47500 50900 5 10 0 1 0 0 1
+footprint=0402
+}
+N 46700 51800 46700 52300 4
+N 47400 51800 47400 52300 4
+N 47400 50900 47400 49500 4
+N 46700 50900 46700 50300 4
+T 54900 40800 9 10 1 0 0 0 2
+ Copyright 2023 by Bdale Garbee <bdale@gag.com>
+Licensed under the TAPR Open Hardware License, http://www.tapr.org/OHL
+C 44500 51800 1 0 0 nc-right.sym
+{
+T 44600 52300 5 10 0 0 0 0 1
+value=NoConnection
+T 44600 52500 5 10 0 0 0 0 1
+device=DRC_Directive
+}
+C 44500 51000 1 0 0 nc-right.sym
+{
+T 44600 51500 5 10 0 0 0 0 1
+value=NoConnection
+T 44600 51700 5 10 0 0 0 0 1
+device=DRC_Directive
+}
+C 44500 48600 1 0 0 nc-right.sym
+{
+T 44600 49100 5 10 0 0 0 0 1
+value=NoConnection
+T 44600 49300 5 10 0 0 0 0 1
+device=DRC_Directive
+}
+C 44500 46200 1 0 0 nc-right.sym
+{
+T 44600 46700 5 10 0 0 0 0 1
+value=NoConnection
+T 44600 46900 5 10 0 0 0 0 1
+device=DRC_Directive
+}
+C 49000 51400 1 0 0 gnd.sym
+C 49200 53200 1 180 0 gnd.sym