-#define MOV_A_data 0x74
-#define MOVX_atDPTR_A 0xf0
-#define MOVX_A_atDPTR 0xe0
-#define INC_DPTR 0xa3
-#define TRAP 0xa5
-
-#define SJMP 0x80
-
-#define FWT 0xAB
-#define FADDRL 0xAC
-#define FADDRH 0xAD
-#define FCTL 0xAE
-# define FCTL_BUSY 0x80
-# define FCTL_BUSY_BIT 7
-# define FCTL_SWBSY 0x40
-# define FCTL_SWBSY_BIT 6
-# define FCTL_CONTRD 0x10
-# define FCTL_WRITE 0x02
-# define FCTL_ERASE 0x01
-#define FWDATA 0xAF
-
-#define CLKCON 0xC6
-#define CLKCON_OSC32K 0x80
-#define CLKCON_OSC 0x40
-#define CLKCON_TICKSPD 0x38
-#define CLKCON_CLKSPD 0x07
-
-#define P0 0x80
-#define P1 0x90
-#define P2 0xA0
-#define P0DIR 0xFD
-#define P1DIR 0xFE
-#define P2DIR 0xFF
-
-#define SLEEP 0xBE
-
-#define JB 0x20
-
-#define ACC(bit) (0xE0 | (bit))
+#define MOV_A_data 0x74
+#define MOVX_atDPTR_A 0xf0
+#define MOVX_A_atDPTR 0xe0
+#define INC_DPTR 0xa3
+#define TRAP 0xa5
+#define SJMP 0x80
+#define JB 0x20
+
+/* 8051 special function registers
+ */
+
+#define SFR_P0 0x80
+#define SFR_SP 0x81
+#define SFR_DPL0 0x82
+#define SFR_DPH0 0x83
+#define SFR_DPL1 0x84
+#define SFR_DPH1 0x85
+
+/* flash controller */
+#define FWT 0xAB
+#define FADDRL 0xAC
+#define FADDRH 0xAD
+#define FCTL 0xAE
+# define FCTL_BUSY 0x80
+# define FCTL_BUSY_BIT 7
+# define FCTL_SWBSY 0x40
+# define FCTL_SWBSY_BIT 6
+# define FCTL_CONTRD 0x10
+# define FCTL_WRITE 0x02
+# define FCTL_ERASE 0x01
+#define FWDATA 0xAF
+
+#define SLEEP 0xBE
+
+/* clock controller */
+#define CLKCON 0xC6
+#define CLKCON_OSC32K 0x80
+#define CLKCON_OSC 0x40
+#define CLKCON_TICKSPD 0x38
+#define CLKCON_CLKSPD 0x07
+
+/* I/O pins */
+#define P0 0x80
+#define P1 0x90
+#define P2 0xA0
+#define P0DIR 0xFD
+#define P1DIR 0xFE
+#define P2DIR 0xFF
+
+/* Bit-addressable accumulator */
+#define ACC(bit) (0xE0 | (bit))
+
+#define CP_USB_ASYNC