2 * Copyright © 2019 Bdale Garbee <bdale@gag.com>
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
12 * General Public License for more details.
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
23 #define HAS_RADIO_RATE 1
24 #define HAS_TELEMETRY 0
30 #define HAS_SERIAL_1 0
36 #define IGNITE_ON_P0 0
37 #define PACKET_HAS_MASTER 0
38 #define PACKET_HAS_SLAVE 0
39 #define AO_DATA_RING 32
40 #define HAS_FIXED_PAD_BOX 1
42 #define AO_CONFIG_DEFAULT_FLIGHT_LOG_MAX (512 * 1024)
43 #define AO_CONFIG_MAX_SIZE 1024
44 #define LOG_ERASE_MARK 0x55
45 #define LOG_MAX_ERASE 128
46 #define AO_LOG_FORMAT AO_LOG_FORMAT_TELEMETRUM
48 /* 8MHz High speed external crystal */
49 #define AO_HSE 8000000
51 /* PLLVCO = 96MHz (so that USB will work) */
53 #define AO_RCC_CFGR_PLLMUL (STM_RCC_CFGR_PLLMUL_12)
55 #define AO_CC1200_FOSC 40000000
57 /* SYSCLK = 32MHz (no need to go faster than CPU) */
59 #define AO_RCC_CFGR_PLLDIV (STM_RCC_CFGR_PLLDIV_3)
61 /* HCLK = 32MHz (CPU clock) */
62 #define AO_AHB_PRESCALER 1
63 #define AO_RCC_CFGR_HPRE_DIV STM_RCC_CFGR_HPRE_DIV_1
65 /* Run APB1 at 16MHz (HCLK/2) */
66 #define AO_APB1_PRESCALER 2
67 #define AO_RCC_CFGR_PPRE1_DIV STM_RCC_CFGR_PPRE2_DIV_2
69 /* Run APB2 at 16MHz (HCLK/2) */
70 #define AO_APB2_PRESCALER 2
71 #define AO_RCC_CFGR_PPRE2_DIV STM_RCC_CFGR_PPRE2_DIV_2
74 #define USE_INTERNAL_FLASH 0
75 #define USE_EEPROM_CONFIG 1
76 #define USE_STORAGE_CONFIG 0
79 #define HAS_RADIO_RATE 1
80 #define HAS_TELEMETRY 0
83 #define HAS_SPI_1 1 /* ADS124S0X */
84 #define SPI_1_PA5_PA6_PA7 1
85 #define SPI_1_PB3_PB4_PB5 0
86 #define SPI_1_PE13_PE14_PE15 0
87 #define SPI_1_OSPEEDR STM_OSPEEDR_10MHz
89 #define HAS_SPI_2 1 /* CC1200 */
90 #define SPI_2_PB13_PB14_PB15 1
91 #define SPI_2_PD1_PD3_PD4 0
92 #define SPI_2_GPIO (&stm_gpiob)
96 #define SPI_2_OSPEEDR STM_OSPEEDR_10MHz
102 #define PACKET_HAS_SLAVE 0
103 #define PACKET_HAS_MASTER 0
105 #define FAST_TIMER_FREQ 10000 /* .1ms for debouncing */
108 * ADS124S0X analog to digital converter
111 #define AO_ADS124S0X_SPI_CS_PORT (&stm_gpioa)
112 #define AO_ADS124S0X_SPI_CS_PIN 4
113 #define AO_ADS124S0X_SPI_CS_MASK (1 << AO_ADS124S0X_SPI_CS_PIN)
114 #define AO_ADS124S0X_SPI_BUS (AO_SPI_1_PA5_PA6_PA7 | AO_SPI_MODE_1)
115 #define AO_ADS124S0X_SPI_SPEED AO_SPI_SPEED_8MHz
117 #define AO_ADS124S0X_DRDY_PORT (&stm_gpioc)
118 #define AO_ADS124S0X_DRDY_PIN 13
120 #define AO_ADS124S0X_START_PORT (&stm_gpioc)
121 #define AO_ADS124S0X_START_PIN 14
123 #define AO_ADS124S0X_RESET_PORT (&stm_gpioc)
124 #define AO_ADS124S0X_RESET_PIN 15
126 #define AO_ADS124S0X_CHANNELS 4 /* how many inputs in use */
132 #define M25_MAX_CHIPS 1
133 #define AO_M25_SPI_CS_PORT (&stm_gpioa)
134 #define AO_M25_SPI_CS_MASK (1 << 15)
135 #define AO_M25_SPI_BUS AO_SPI_2_PB13_PB14_PB15
138 * Radio is a cc1200 connected via SPI
141 #define AO_RADIO_CAL_DEFAULT 5695733
143 #define AO_FEC_DEBUG 0
144 #define AO_CC1200_SPI_CS_PORT (&stm_gpioa)
145 #define AO_CC1200_SPI_CS_PIN 3
146 #define AO_CC1200_SPI_BUS AO_SPI_2_PB13_PB14_PB15
147 #define AO_CC1200_SPI stm_spi2
148 #define AO_CC1200_SPI_SPEED AO_SPI_SPEED_FAST
150 #define AO_CC1200_INT_PORT (&stm_gpiob)
151 #define AO_CC1200_INT_PIN (11)
153 #define AO_CC1200_INT_GPIO 2
154 #define AO_CC1200_INT_GPIO_IOCFG CC1200_IOCFG2
156 #define LED_PORT_0 (&stm_gpioa)
157 #define LED_PORT_1 (&stm_gpiob)
159 #define LED_PORT_0_ENABLE STM_RCC_AHBENR_GPIOAEN
160 #define LED_PORT_1_ENABLE STM_RCC_AHBENR_GPIOBEN
162 /* Port A, pins 8-10 */
163 #define LED_PORT_0_SHIFT 8
164 #define LED_PORT_0_MASK 0x7
165 #define LED_PIN_GREEN 0
166 #define LED_PIN_AMBER 1
167 #define LED_PIN_RED 2
168 #define AO_LED_RED (1 << LED_PIN_RED)
169 #define AO_LED_AMBER (1 << LED_PIN_AMBER)
170 #define AO_LED_GREEN (1 << LED_PIN_GREEN)
172 /* Port B, pins 5-6 */
173 #define LED_PORT_1_SHIFT 0
174 #define LED_PORT_1_MASK (0x3 << 5)
175 #define LED_PIN_CONT_0 5
176 #define LED_PIN_ARMED 6
178 #define AO_LED_ARMED (1 << LED_PIN_ARMED)
179 #define AO_LED_CONTINUITY(c) (1 << (4 - (c)))
180 #define AO_LED_CONTINUITY_MASK (0x1 << 4)
182 #define LEDS_AVAILABLE (LED_PORT_0_MASK|LED_PORT_1_MASK)
186 #define AO_SIREN_PORT (&stm_gpiob)
187 #define AO_SIREN_PIN 8
191 #define AO_STROBE_PORT (&stm_gpiob)
192 #define AO_STROBE_PIN 9
194 #define SPI_CONST 0x00
197 * ADC reference in decivolts
199 #define AO_ADC_REFERENCE_DV 33
202 #define AO_PAD_PORT (&stm_gpioa)
204 #define AO_PAD_PIN_0 1
205 #define AO_PAD_ADC_0 0
207 #define AO_PAD_ALL_PINS ((1 << AO_PAD_PIN_0))
208 #define AO_PAD_ALL_CHANNELS ((1 << 0))
210 /* test these values with real igniters */
211 #define AO_PAD_RELAY_CLOSED 3524
212 #define AO_PAD_NO_IGNITER 16904
213 #define AO_PAD_GOOD_IGNITER 22514
215 #define AO_PAD_ADC_PYRO 2
216 #define AO_PAD_ADC_BATT 8
218 // #define AO_PAD_ADC_THRUST 3 /* FIXME - external ADC now! */
219 // #define AO_PAD_ADC_PRESSURE 18 /* FIXME - external ADC now! */
221 #define AO_ADC_FIRST_PIN 0
225 #define AO_ADC_SQ1 AO_PAD_ADC_0
226 #define AO_ADC_SQ2 AO_PAD_ADC_PYRO
227 #define AO_ADC_SQ3 AO_PAD_ADC_BATT
228 // #define AO_ADC_SQ4 AO_PAD_ADC_THRUST
229 // #define AO_ADC_SQ5 AO_PAD_ADC_PRESSURE
231 #define AO_PAD_R_V_BATT_BATT_SENSE 200
232 #define AO_PAD_R_BATT_SENSE_GND 22
234 #define AO_PAD_R_V_BATT_V_PYRO 200
235 #define AO_PAD_R_V_PYRO_PYRO_SENSE 200
236 #define AO_PAD_R_PYRO_SENSE_GND 22
238 #undef AO_PAD_R_V_PYRO_IGNITER
239 #define AO_PAD_R_IGNITER_IGNITER_SENSE 200
240 #define AO_PAD_R_IGNITER_SENSE_GND 22
242 #define HAS_ADC_TEMP 0
245 int16_t sense[AO_PAD_NUM];
252 #define AO_ADC_DUMP(p) \
253 printf ("tick: %5u 0: %5d pyro: %5d batt %5d\n", \
259 #define AO_ADC_PINS ((1 << AO_PAD_ADC_0) | \
260 (1 << AO_PAD_ADC_PYRO) | \
261 (1 << AO_PAD_ADC_BATT))
263 #endif /* _AO_PINS_H_ */