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   1 /*
   2  * Copyright © 2015 Keith Packard <keithp@keithp.com>
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful, but
  10  * WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  12  * General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along
  15  * with this program; if not, write to the Free Software Foundation, Inc.,
  16  * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
  17  */
  18
  19 #ifndef _STM32F0_H_
  20 #define _STM32F0_H_
  21
  22 #include <stdint.h>
  23
  24 typedef volatile uint32_t       vuint32_t;
  25 typedef volatile void *         vvoid_t;
  26 typedef volatile uint16_t       vuint16_t;
  27 typedef volatile uint8_t        vuint8_t;
  28
  29 struct stm_gpio {
  30         vuint32_t       moder;
  31         vuint32_t       otyper;
  32         vuint32_t       ospeedr;
  33         vuint32_t       pupdr;
  34
  35         vuint32_t       idr;
  36         vuint32_t       odr;
  37         vuint32_t       bsrr;
  38         vuint32_t       lckr;
  39
  40         vuint32_t       afrl;
  41         vuint32_t       afrh;
  42         vuint32_t       brr;
  43 };
  44
  45 #define STM_MODER_SHIFT(pin)            ((pin) << 1)
  46 #define STM_MODER_MASK                  3
  47 #define STM_MODER_INPUT                 0
  48 #define STM_MODER_OUTPUT                1
  49 #define STM_MODER_ALTERNATE             2
  50 #define STM_MODER_ANALOG                3
  51
  52 static inline void
  53 stm_moder_set(struct stm_gpio *gpio, int pin, vuint32_t value) {
  54         gpio->moder = ((gpio->moder &
  55                         ~(STM_MODER_MASK << STM_MODER_SHIFT(pin))) |
  56                        value << STM_MODER_SHIFT(pin));
  57 }
  58
  59 static inline uint32_t
  60 stm_moder_get(struct stm_gpio *gpio, int pin) {
  61         return (gpio->moder >> STM_MODER_SHIFT(pin)) & STM_MODER_MASK;
  62 }
  63
  64 #define STM_OTYPER_SHIFT(pin)           (pin)
  65 #define STM_OTYPER_MASK                 1
  66 #define STM_OTYPER_PUSH_PULL            0
  67 #define STM_OTYPER_OPEN_DRAIN           1
  68
  69 static inline void
  70 stm_otyper_set(struct stm_gpio *gpio, int pin, vuint32_t value) {
  71         gpio->otyper = ((gpio->otyper &
  72                          ~(STM_OTYPER_MASK << STM_OTYPER_SHIFT(pin))) |
  73                         value << STM_OTYPER_SHIFT(pin));
  74 }
  75
  76 static inline uint32_t
  77 stm_otyper_get(struct stm_gpio *gpio, int pin) {
  78         return (gpio->otyper >> STM_OTYPER_SHIFT(pin)) & STM_OTYPER_MASK;
  79 }
  80
  81 #define STM_OSPEEDR_SHIFT(pin)          ((pin) << 1)
  82 #define STM_OSPEEDR_MASK                3
  83 #define STM_OSPEEDR_LOW                 0       /* 2MHz */
  84 #define STM_OSPEEDR_MEDIUM              1       /* 10MHz */
  85 #define STM_OSPEEDR_HIGH                3       /* 10-50MHz */
  86
  87 static inline void
  88 stm_ospeedr_set(struct stm_gpio *gpio, int pin, vuint32_t value) {
  89         gpio->ospeedr = ((gpio->ospeedr &
  90                         ~(STM_OSPEEDR_MASK << STM_OSPEEDR_SHIFT(pin))) |
  91                        value << STM_OSPEEDR_SHIFT(pin));
  92 }
  93
  94 static inline uint32_t
  95 stm_ospeedr_get(struct stm_gpio *gpio, int pin) {
  96         return (gpio->ospeedr >> STM_OSPEEDR_SHIFT(pin)) & STM_OSPEEDR_MASK;
  97 }
  98
  99 #define STM_PUPDR_SHIFT(pin)            ((pin) << 1)
 100 #define STM_PUPDR_MASK                  3
 101 #define STM_PUPDR_NONE                  0
 102 #define STM_PUPDR_PULL_UP               1
 103 #define STM_PUPDR_PULL_DOWN             2
 104 #define STM_PUPDR_RESERVED              3
 105
 106 static inline void
 107 stm_pupdr_set(struct stm_gpio *gpio, int pin, uint32_t value) {
 108         gpio->pupdr = ((gpio->pupdr &
 109                         ~(STM_PUPDR_MASK << STM_PUPDR_SHIFT(pin))) |
 110                        value << STM_PUPDR_SHIFT(pin));
 111 }
 112
 113 static inline uint32_t
 114 stm_pupdr_get(struct stm_gpio *gpio, int pin) {
 115         return (gpio->pupdr >> STM_PUPDR_SHIFT(pin)) & STM_PUPDR_MASK;
 116 }
 117
 118 #define STM_AFR_SHIFT(pin)              ((pin) << 2)
 119 #define STM_AFR_MASK                    0xf
 120 #define STM_AFR_NONE                    0
 121 #define STM_AFR_AF0                     0x0
 122 #define STM_AFR_AF1                     0x1
 123 #define STM_AFR_AF2                     0x2
 124 #define STM_AFR_AF3                     0x3
 125 #define STM_AFR_AF4                     0x4
 126 #define STM_AFR_AF5                     0x5
 127 #define STM_AFR_AF6                     0x6
 128 #define STM_AFR_AF7                     0x7
 129
 130 static inline void
 131 stm_afr_set(struct stm_gpio *gpio, int pin, uint32_t value) {
 132         /*
 133          * Set alternate pin mode too
 134          */
 135         stm_moder_set(gpio, pin, STM_MODER_ALTERNATE);
 136         if (pin < 8)
 137                 gpio->afrl = ((gpio->afrl &
 138                                ~(STM_AFR_MASK << STM_AFR_SHIFT(pin))) |
 139                               value << STM_AFR_SHIFT(pin));
 140         else {
 141                 pin -= 8;
 142                 gpio->afrh = ((gpio->afrh &
 143                                ~(STM_AFR_MASK << STM_AFR_SHIFT(pin))) |
 144                               value << STM_AFR_SHIFT(pin));
 145         }
 146 }
 147
 148 static inline uint32_t
 149 stm_afr_get(struct stm_gpio *gpio, int pin) {
 150         if (pin < 8)
 151                 return (gpio->afrl >> STM_AFR_SHIFT(pin)) & STM_AFR_MASK;
 152         else {
 153                 pin -= 8;
 154                 return (gpio->afrh >> STM_AFR_SHIFT(pin)) & STM_AFR_MASK;
 155         }
 156 }
 157
 158 static inline void
 159 stm_gpio_set(struct stm_gpio *gpio, int pin, uint8_t value) {
 160         /* Use the bit set/reset register to do this atomically */
 161         gpio->bsrr = ((uint32_t) (value ^ 1) << (pin + 16)) | ((uint32_t) value << pin);
 162 }
 163
 164 static inline uint8_t
 165 stm_gpio_get(struct stm_gpio *gpio, int pin) {
 166         return (gpio->idr >> pin) & 1;
 167 }
 168
 169 static inline uint16_t
 170 stm_gpio_get_all(struct stm_gpio *gpio) {
 171         return gpio->idr;
 172 }
 173
 174 /*
 175  * We can't define these in registers.ld or our fancy
 176  * ao_enable_gpio macro will expand into a huge pile of code
 177  * as the compiler won't do correct constant folding and
 178  * dead-code elimination
 179  */
 180
 181 extern struct stm_gpio stm_gpioa;
 182 extern struct stm_gpio stm_gpiob;
 183 extern struct stm_gpio stm_gpioc;
 184 extern struct stm_gpio stm_gpiof;
 185
 186 #define stm_gpiof  (*((struct stm_gpio *) 0x48001400))
 187 #define stm_gpioc  (*((struct stm_gpio *) 0x48000800))
 188 #define stm_gpiob  (*((struct stm_gpio *) 0x48000400))
 189 #define stm_gpioa  (*((struct stm_gpio *) 0x48000000))
 190
 191 /* Flash interface */
 192
 193 struct stm_flash {
 194         vuint32_t       acr;
 195         vuint32_t       keyr;
 196         vuint32_t       optkeyr;
 197         vuint32_t       sr;
 198
 199         vuint32_t       cr;
 200         vuint32_t       ar;
 201         vuint32_t       unused_0x18;
 202         vuint32_t       obr;
 203
 204         vuint32_t       wrpr;
 205 };
 206
 207 extern struct stm_flash stm_flash;
 208
 209 #define STM_FLASH_ACR_PRFTBS    (5)
 210 #define STM_FLASH_ACR_PRFTBE    (4)
 211 #define STM_FLASH_ACR_LATENCY   (0)
 212 #define  STM_FLASH_ACR_LATENCY_0                0
 213 #define  STM_FLASH_ACR_LATENCY_1                1
 214
 215 #define STM_FLASH_PECR_OBL_LAUNCH       18
 216 #define STM_FLASH_PECR_ERRIE            17
 217 #define STM_FLASH_PECR_EOPIE            16
 218 #define STM_FLASH_PECR_FPRG             10
 219 #define STM_FLASH_PECR_ERASE            9
 220 #define STM_FLASH_PECR_FTDW             8
 221 #define STM_FLASH_PECR_DATA             4
 222 #define STM_FLASH_PECR_PROG             3
 223 #define STM_FLASH_PECR_OPTLOCK          2
 224 #define STM_FLASH_PECR_PRGLOCK          1
 225 #define STM_FLASH_PECR_PELOCK           0
 226
 227 #define STM_FLASH_SR_EOP                5
 228 #define STM_FLASH_SR_WRPRTERR           4
 229 #define STM_FLASH_SR_PGERR              2
 230 #define STM_FLASH_SR_BSY                0
 231
 232 #define STM_FLASH_CR_OBL_LAUNCH         13
 233 #define STM_FLASH_CR_EOPIE              12
 234 #define STM_FLASH_CR_ERRIE              10
 235 #define STM_FLASH_CR_OPTWRE             9
 236 #define STM_FLASH_CR_LOCK               7
 237 #define STM_FLASH_CR_STRT               6
 238 #define STM_FLASH_CR_OPTER              5
 239 #define STM_FLASH_CR_OPTPG              4
 240 #define STM_FLASH_CR_MER                2
 241 #define STM_FLASH_CR_PER                1
 242 #define STM_FLASH_CR_PG                 0
 243
 244 #define STM_FLASH_OBR_DATA1             24
 245 #define STM_FLASH_OBR_DATA0             16
 246 #define STM_FLASH_OBR_BOOT_SEL          15
 247 #define STM_FLASH_OBR_RAM_PARITY_CHECK  14
 248 #define STM_FLASH_OBR_VDDA_MONITOR      13
 249 #define STM_FLASH_OBR_NBOOT1            12
 250 #define STM_FLASH_OBR_NBOOT0            11
 251 #define STM_FLASH_OBR_NRST_STDBY        10
 252 #define STM_FLASH_OBR_NRST_STOP         9
 253 #define STM_FLASH_OBR_WDG_SW            8
 254 #define STM_FLASH_OBR_RDPRT             1
 255 #define  STM_FLASH_OBR_RDPRT_LEVEL0             0
 256 #define  STM_FLASH_OBR_RDPRT_LEVEL1             1
 257 #define  STM_FLASH_OBR_RDPRT_LEVEL2             3
 258 #define STM_FLASH_OBR_OPTERR            0
 259
 260 #define STM_FLASH_KEYR_KEY1     0x45670123
 261 #define STM_FLASH_KEYR_KEY2     0xcdef89ab
 262
 263 struct stm_rcc {
 264         vuint32_t       cr;
 265         vuint32_t       cfgr;
 266         vuint32_t       cir;
 267         vuint32_t       apb2rstr;
 268
 269         vuint32_t       apb1rstr;
 270         vuint32_t       ahbenr;
 271         vuint32_t       apb2enr;
 272         vuint32_t       apb1enr;
 273
 274         vuint32_t       bdcr;
 275         vuint32_t       csr;
 276         vuint32_t       ahbrstr;
 277         vuint32_t       cfgr2;
 278
 279         vuint32_t       cfgr3;
 280         vuint32_t       cr2;
 281 };
 282
 283 extern struct stm_rcc stm_rcc;
 284
 285 /* Nominal high speed internal oscillator frequency is 8MHz */
 286 #define STM_HSI_FREQ            8000000
 287
 288 #define STM_RCC_CR_PLLRDY       (25)
 289 #define STM_RCC_CR_PLLON        (24)
 290 #define STM_RCC_CR_CSSON        (19)
 291 #define STM_RCC_CR_HSEBYP       (18)
 292 #define STM_RCC_CR_HSERDY       (17)
 293 #define STM_RCC_CR_HSEON        (16)
 294 #define STM_RCC_CR_HSICAL       (8)
 295 #define STM_RCC_CR_HSITRIM      (3)
 296 #define STM_RCC_CR_HSIRDY       (1)
 297 #define STM_RCC_CR_HSION        (0)
 298
 299 #define STM_RCC_CFGR_PLL_NODIV  (31)
 300 #define  STM_RCC_CFGR_PLL_NODIV_DIV_1   1
 301 #define  STM_RCC_CFGR_PLL_NODIV_DIV_2   0
 302
 303 #define STM_RCC_CFGR_MCOPRE     (28)
 304 #define  STM_RCC_CFGR_MCOPRE_DIV_1      0
 305 #define  STM_RCC_CFGR_MCOPRE_DIV_2      1
 306 #define  STM_RCC_CFGR_MCOPRE_DIV_4      2
 307 #define  STM_RCC_CFGR_MCOPRE_DIV_8      3
 308 #define  STM_RCC_CFGR_MCOPRE_DIV_16     4
 309 #define  STM_RCC_CFGR_MCOPRE_DIV_32     5
 310 #define  STM_RCC_CFGR_MCOPRE_DIV_64     6
 311 #define  STM_RCC_CFGR_MCOPRE_DIV_128    7
 312 #define  STM_RCC_CFGR_MCOPRE_DIV_MASK   7
 313
 314 #define STM_RCC_CFGR_MCO        (24)
 315 # define STM_RCC_CFGR_MCO_DISABLE       0
 316 # define STM_RCC_CFGR_MCO_RC            1
 317 # define STM_RCC_CFGR_MCO_LSI           2
 318 # define STM_RCC_CFGR_MCO_LSE           3
 319 # define STM_RCC_CFGR_MCO_SYSCLK        4
 320 # define STM_RCC_CFGR_MCO_HSI           5
 321 # define STM_RCC_CFGR_MCO_HSE           6
 322 # define STM_RCC_CFGR_MCO_PLLCLK        7
 323 # define STM_RCC_CFGR_MCO_HSI48         8
 324 # define STM_RCC_CFGR_MCO_MASK          (0xf)
 325
 326 #define STM_RCC_CFGR_PLLMUL     (18)
 327 #define  STM_RCC_CFGR_PLLMUL_2          0
 328 #define  STM_RCC_CFGR_PLLMUL_3          1
 329 #define  STM_RCC_CFGR_PLLMUL_4          2
 330 #define  STM_RCC_CFGR_PLLMUL_5          3
 331 #define  STM_RCC_CFGR_PLLMUL_6          4
 332 #define  STM_RCC_CFGR_PLLMUL_7          5
 333 #define  STM_RCC_CFGR_PLLMUL_8          6
 334 #define  STM_RCC_CFGR_PLLMUL_9          7
 335 #define  STM_RCC_CFGR_PLLMUL_10         8
 336 #define  STM_RCC_CFGR_PLLMUL_11         9
 337 #define  STM_RCC_CFGR_PLLMUL_12         10
 338 #define  STM_RCC_CFGR_PLLMUL_13         11
 339 #define  STM_RCC_CFGR_PLLMUL_14         12
 340 #define  STM_RCC_CFGR_PLLMUL_15         13
 341 #define  STM_RCC_CFGR_PLLMUL_16         14
 342 #define  STM_RCC_CFGR_PLLMUL_MASK       0xf
 343
 344 #define STM_RCC_CFGR_PLLXTPRE   (17)
 345
 346 #define STM_RCC_CFGR_PLLSRC     (15)
 347 # define STM_RCC_CFGR_PLLSRC_HSI_DIV_2  0
 348 # define STM_RCC_CFGR_PLLSRC_HSI        1
 349 # define STM_RCC_CFGR_PLLSRC_HSE        2
 350 # define STM_RCC_CFGR_PLLSRC_HSI48      3
 351
 352 #define STM_RCC_CFGR_ADCPRE     (14)
 353
 354 #define STM_RCC_CFGR_PPRE       (8)
 355 #define  STM_RCC_CFGR_PPRE_DIV_1        0
 356 #define  STM_RCC_CFGR_PPRE_DIV_2        4
 357 #define  STM_RCC_CFGR_PPRE_DIV_4        5
 358 #define  STM_RCC_CFGR_PPRE_DIV_8        6
 359 #define  STM_RCC_CFGR_PPRE_DIV_16       7
 360 #define  STM_RCC_CFGR_PPRE_MASK         7
 361
 362 #define STM_RCC_CFGR_HPRE       (4)
 363 #define  STM_RCC_CFGR_HPRE_DIV_1        0
 364 #define  STM_RCC_CFGR_HPRE_DIV_2        8
 365 #define  STM_RCC_CFGR_HPRE_DIV_4        9
 366 #define  STM_RCC_CFGR_HPRE_DIV_8        0xa
 367 #define  STM_RCC_CFGR_HPRE_DIV_16       0xb
 368 #define  STM_RCC_CFGR_HPRE_DIV_64       0xc
 369 #define  STM_RCC_CFGR_HPRE_DIV_128      0xd
 370 #define  STM_RCC_CFGR_HPRE_DIV_256      0xe
 371 #define  STM_RCC_CFGR_HPRE_DIV_512      0xf
 372 #define  STM_RCC_CFGR_HPRE_MASK         0xf
 373
 374 #define STM_RCC_CFGR_SWS        (2)
 375 #define  STM_RCC_CFGR_SWS_HSI           0
 376 #define  STM_RCC_CFGR_SWS_HSE           1
 377 #define  STM_RCC_CFGR_SWS_PLL           2
 378 #define  STM_RCC_CFGR_SWS_HSI48         3
 379 #define  STM_RCC_CFGR_SWS_MASK          3
 380
 381 #define STM_RCC_CFGR_SW         (0)
 382 #define  STM_RCC_CFGR_SW_HSI            0
 383 #define  STM_RCC_CFGR_SW_HSE            1
 384 #define  STM_RCC_CFGR_SW_PLL            2
 385 #define  STM_RCC_CFGR_SW_HSI48          3
 386 #define  STM_RCC_CFGR_SW_MASK           3
 387
 388 #define STM_RCC_APB2RSTR_DBGMCURST      22
 389 #define STM_RCC_APB2RSTR_TIM17RST       18
 390 #define STM_RCC_APB2RSTR_TIM16RST       17
 391 #define STM_RCC_APB2RSTR_TIM15RST       16
 392 #define STM_RCC_APB2RSTR_USART1RST      14
 393 #define STM_RCC_APB2RSTR_SPI1RST        12
 394 #define STM_RCC_APB2RSTR_TIM1RST        11
 395 #define STM_RCC_APB2RSTR_ADCRST         9
 396 #define STM_RCC_APB2RSTR_USART8RST      7
 397 #define STM_RCC_APB2RSTR_USART7RST      6
 398 #define STM_RCC_APB2RSTR_USART6RST      5
 399 #define STM_RCC_APB2RSTR_SYSCFGRST      1
 400
 401 #define STM_RCC_APB1RSTR_CECRST         30
 402 #define STM_RCC_APB1RSTR_DACRST         29
 403 #define STM_RCC_APB1RSTR_PWRRST         28
 404 #define STM_RCC_APB1RSTR_CRSRST         27
 405 #define STM_RCC_APB1RSTR_CANRST         25
 406 #define STM_RCC_APB1RSTR_USBRST         23
 407 #define STM_RCC_APB1RSTR_I2C2RST        22
 408 #define STM_RCC_APB1RSTR_I1C1RST        21
 409 #define STM_RCC_APB1RSTR_USART5RST      20
 410 #define STM_RCC_APB1RSTR_USART4RST      19
 411 #define STM_RCC_APB1RSTR_USART3RST      18
 412 #define STM_RCC_APB1RSTR_USART2RST      17
 413 #define STM_RCC_APB1RSTR_SPI2RST        14
 414 #define STM_RCC_APB1RSTR_WWDGRST        11
 415 #define STM_RCC_APB1RSTR_TIM14RST       8
 416 #define STM_RCC_APB1RSTR_TIM7RST        5
 417 #define STM_RCC_APB1RSTR_TIM6RST        4
 418 #define STM_RCC_APB1RSTR_TIM3RST        1
 419 #define STM_RCC_APB1RSTR_TIM2RST        0
 420
 421 #define STM_RCC_AHBENR_TSCEN    24
 422 #define STM_RCC_AHBENR_IOPFEN   22
 423 #define STM_RCC_AHBENR_IOPEEN   21
 424 #define STM_RCC_AHBENR_IOPDEN   20
 425 #define STM_RCC_AHBENR_IOPCEN   19
 426 #define STM_RCC_AHBENR_IOPBEN   18
 427 #define STM_RCC_AHBENR_IOPAEN   17
 428 #define STM_RCC_AHBENR_CRCEN    6
 429 #define STM_RCC_AHBENR_FLITFEN  4
 430 #define STM_RCC_AHBENR_SRAMEN   2
 431 #define STM_RCC_AHBENR_DMA2EN   1
 432 #define STM_RCC_AHBENR_DMAEN    0
 433
 434 #define STM_RCC_APB2ENR_DBGMCUEN        22
 435 #define STM_RCC_APB2ENR_TIM17EN         18
 436 #define STM_RCC_APB2ENR_TIM16EN         17
 437 #define STM_RCC_APB2ENR_TIM15EN         16
 438 #define STM_RCC_APB2ENR_USART1EN        14
 439 #define STM_RCC_APB2ENR_SPI1EN          12
 440 #define STM_RCC_APB2ENR_TIM1EN          11
 441 #define STM_RCC_APB2ENR_ADCEN           9
 442 #define STM_RCC_APB2ENR_USART8EN        7
 443 #define STM_RCC_APB2ENR_USART7EN        6
 444 #define STM_RCC_APB2ENR_USART6EN        5
 445 #define STM_RCC_APB2ENR_SYSCFGCOMPEN    0
 446
 447 #define STM_RCC_APB1ENR_CECEN           30
 448 #define STM_RCC_APB1ENR_DACEN           29
 449 #define STM_RCC_APB1ENR_PWREN           28
 450 #define STM_RCC_APB1ENR_CRSEN           27
 451 #define STM_RCC_APB1ENR_CANEN           25
 452 #define STM_RCC_APB1ENR_USBEN           23
 453 #define STM_RCC_APB1ENR_I2C2EN          22
 454 #define STM_RCC_APB1ENR_IC21EN          21
 455 #define STM_RCC_APB1ENR_USART5EN        20
 456 #define STM_RCC_APB1ENR_USART4EN        19
 457 #define STM_RCC_APB1ENR_USART3EN        18
 458 #define STM_RCC_APB1ENR_USART2EN        17
 459 #define STM_RCC_APB1ENR_SPI2EN          14
 460 #define STM_RCC_APB1ENR_WWDGEN          11
 461 #define STM_RCC_APB1ENR_TIM14EN         8
 462 #define STM_RCC_APB1ENR_TIM7EN          5
 463 #define STM_RCC_APB1ENR_TIM6EN          4
 464 #define STM_RCC_APB1ENR_TIM3EN          1
 465 #define STM_RCC_APB1ENR_TIM2EN          0
 466
 467 #define STM_RCC_CSR_LPWRRSTF            (31)
 468 #define STM_RCC_CSR_WWDGRSTF            (30)
 469 #define STM_RCC_CSR_IWDGRSTF            (29)
 470 #define STM_RCC_CSR_SFTRSTF             (28)
 471 #define STM_RCC_CSR_PORRSTF             (27)
 472 #define STM_RCC_CSR_PINRSTF             (26)
 473 #define STM_RCC_CSR_OBLRSTF             (25)
 474 #define STM_RCC_CSR_RMVF                (24)
 475 #define STM_RCC_CSR_V18PWRRSTF          (23)
 476 #define STM_RCC_CSR_LSIRDY              (1)
 477 #define STM_RCC_CSR_LSION               (0)
 478
 479 #define STM_RCC_CR2_HSI48CAL            24
 480 #define STM_RCC_CR2_HSI48RDY            17
 481 #define STM_RCC_CR2_HSI48ON             16
 482 #define STM_RCC_CR2_HSI14CAL            8
 483 #define STM_RCC_CR2_HSI14TRIM           3
 484 #define STM_RCC_CR2_HSI14DIS            2
 485 #define STM_RCC_CR2_HSI14RDY            1
 486 #define STM_RCC_CR2_HSI14ON             0
 487
 488 #define STM_RCC_CFGR2_PREDIV            0
 489 #define  STM_RCC_CFGR2_PREDIV_1                 0x0
 490 #define  STM_RCC_CFGR2_PREDIV_2                 0x1
 491 #define  STM_RCC_CFGR2_PREDIV_3                 0x2
 492 #define  STM_RCC_CFGR2_PREDIV_4                 0x3
 493 #define  STM_RCC_CFGR2_PREDIV_5                 0x4
 494 #define  STM_RCC_CFGR2_PREDIV_6                 0x5
 495 #define  STM_RCC_CFGR2_PREDIV_7                 0x6
 496 #define  STM_RCC_CFGR2_PREDIV_8                 0x7
 497 #define  STM_RCC_CFGR2_PREDIV_9                 0x8
 498 #define  STM_RCC_CFGR2_PREDIV_10                0x9
 499 #define  STM_RCC_CFGR2_PREDIV_11                0xa
 500 #define  STM_RCC_CFGR2_PREDIV_12                0xb
 501 #define  STM_RCC_CFGR2_PREDIV_13                0xc
 502 #define  STM_RCC_CFGR2_PREDIV_14                0xd
 503 #define  STM_RCC_CFGR2_PREDIV_15                0xe
 504 #define  STM_RCC_CFGR2_PREDIV_16                0xf
 505
 506 #define STM_RCC_CFGR3_USART3SW          18
 507 #define STM_RCC_CFGR3_USART2SW          16
 508 #define STM_RCC_CFGR3_ADCSW             8
 509 #define STM_RCC_CFGR3_USBSW             7
 510 #define STM_RCC_CFGR3_CECSW             6
 511 #define STM_RCC_CFGR3_I2C1SW            4
 512 #define STM_RCC_CFGR3_USART1SW          0
 513
 514 struct stm_crs {
 515         vuint32_t       cr;
 516         vuint32_t       cfgr;
 517         vuint32_t       isr;
 518         vuint32_t       icr;
 519 };
 520
 521 extern struct stm_crs stm_crs;
 522
 523 #define STM_CRS_CR_TRIM         8
 524 #define STM_CRS_CR_SWSYNC       7
 525 #define STM_CRS_CR_AUTOTRIMEN   6
 526 #define STM_CRS_CR_CEN          5
 527 #define STM_CRS_CR_ESYNCIE      3
 528 #define STM_CRS_CR_ERRIE        2
 529 #define STM_CRS_CR_SYNCWARNIE   1
 530 #define STM_CRS_CR_SYNCOKIE     0
 531
 532 #define STM_CRS_CFGR_SYNCPOL    31
 533 #define STM_CRS_CFGR_SYNCSRC    28
 534 #define  STM_CRS_CFGR_SYNCSRC_GPIO      0
 535 #define  STM_CRS_CFGR_SYNCSRC_LSE       1
 536 #define  STM_CRS_CFGR_SYNCSRC_USB       2
 537 #define STM_CRS_CFGR_SYNCDIV    24
 538 #define  STM_CRS_CFGR_SYNCDIV_1         0
 539 #define  STM_CRS_CFGR_SYNCDIV_2         1
 540 #define  STM_CRS_CFGR_SYNCDIV_4         2
 541 #define  STM_CRS_CFGR_SYNCDIV_8         3
 542 #define  STM_CRS_CFGR_SYNCDIV_16        4
 543 #define  STM_CRS_CFGR_SYNCDIV_32        5
 544 #define  STM_CRS_CFGR_SYNCDIV_64        6
 545 #define  STM_CRS_CFGR_SYNCDIV_128       7
 546 #define STM_CRS_CFGR_FELIM      16
 547 #define STM_CRS_CFGR_RELOAD     0
 548
 549 #define STM_CRS_ISR_FECAP       16
 550 #define STM_CRS_ISR_FEDIR       15
 551 #define STM_CRS_ISR_TRIMOVF     10
 552 #define STM_CRS_ISR_SYNCMISS    9
 553 #define STM_CRS_ISR_SYNCERR     8
 554 #define STM_CRS_ISR_ESYNCF      3
 555 #define STM_CRS_ISR_ERRF        2
 556 #define STM_CRS_ISR_SYNCWARNF   1
 557 #define STM_CRS_ISR_SYNCOKF     0
 558
 559 #define STM_CRS_ICR_ESYNCC      3
 560 #define STM_CRS_ICR_ERRC        2
 561 #define STM_CRS_ICR_SYNCWARNC   1
 562 #define STM_CRS_ICR_SYNCOKC     0
 563
 564 struct stm_pwr {
 565         vuint32_t       cr;
 566         vuint32_t       csr;
 567 };
 568
 569 extern struct stm_pwr stm_pwr;
 570
 571 #define STM_PWR_CR_DBP          (8)
 572
 573 #define STM_PWR_CR_PLS          (5)
 574 #define  STM_PWR_CR_PLS_2_0     0
 575 #define  STM_PWR_CR_PLS_2_1     1
 576 #define  STM_PWR_CR_PLS_2_2     2
 577 #define  STM_PWR_CR_PLS_2_3     3
 578 #define  STM_PWR_CR_PLS_2_4     4
 579 #define  STM_PWR_CR_PLS_2_5     5
 580 #define  STM_PWR_CR_PLS_2_6     6
 581 #define  STM_PWR_CR_PLS_EXT     7
 582 #define  STM_PWR_CR_PLS_MASK    7
 583
 584 #define STM_PWR_CR_PVDE         (4)
 585 #define STM_PWR_CR_CSBF         (3)
 586 #define STM_PWR_CR_CWUF         (2)
 587 #define STM_PWR_CR_PDDS         (1)
 588 #define STM_PWR_CR_LPSDSR       (0)
 589
 590 #define STM_PWR_CSR_EWUP3       (10)
 591 #define STM_PWR_CSR_EWUP2       (9)
 592 #define STM_PWR_CSR_EWUP1       (8)
 593 #define STM_PWR_CSR_REGLPF      (5)
 594 #define STM_PWR_CSR_VOSF        (4)
 595 #define STM_PWR_CSR_VREFINTRDYF (3)
 596 #define STM_PWR_CSR_PVDO        (2)
 597 #define STM_PWR_CSR_SBF         (1)
 598 #define STM_PWR_CSR_WUF         (0)
 599
 600 struct stm_crc {
 601         union {
 602                 vuint32_t       u32;
 603                 vuint16_t       u16;
 604                 vuint8_t        u8;
 605         }               dr;
 606         vuint32_t       idr;
 607         vuint32_t       cr;
 608         uint32_t        _0c;
 609
 610         vuint32_t       init;
 611         vuint32_t       pol;
 612 };
 613
 614 extern struct stm_crc   stm_crc;
 615
 616 #define stm_crc (*((struct stm_crc *) 0x40023000))
 617
 618 #define STM_CRC_CR_REV_OUT      7
 619 #define STM_CRC_CR_REV_IN       5
 620 #define  STM_CRC_CR_REV_IN_NONE         0
 621 #define  STM_CRC_CR_REV_IN_BY_BYTE      1
 622 #define  STM_CRC_CR_REV_IN_BY_HALF_WORD 2
 623 #define  STM_CRC_CR_REV_IN_BY_WORD      3
 624 #define STM_CRC_CR_POLYSIZE     3
 625 #define  STM_CRC_CR_POLYSIZE_32         0
 626 #define  STM_CRC_CR_POLYSIZE_16         1
 627 #define  STM_CRC_CR_POLYSIZE_8          2
 628 #define  STM_CRC_CR_POLYSIZE_7          3
 629 #define STM_CRC_CR_RESET        0
 630
 631 /* The SYSTICK starts at 0xe000e010 */
 632
 633 struct stm_systick {
 634         vuint32_t       csr;
 635         vuint32_t       rvr;
 636         vuint32_t       cvr;
 637         vuint32_t       calib;
 638 };
 639
 640 extern struct stm_systick stm_systick;
 641
 642 #define STM_SYSTICK_CSR_ENABLE          0
 643 #define STM_SYSTICK_CSR_TICKINT         1
 644 #define STM_SYSTICK_CSR_CLKSOURCE       2
 645 #define  STM_SYSTICK_CSR_CLKSOURCE_EXTERNAL             0
 646 #define  STM_SYSTICK_CSR_CLKSOURCE_HCLK_8               1
 647 #define STM_SYSTICK_CSR_COUNTFLAG       16
 648
 649 /* The NVIC starts at 0xe000e100, so add that to the offsets to find the absolute address */
 650
 651 struct stm_nvic {
 652         vuint32_t       iser;           /* 0x000 0xe000e100 Set Enable Register */
 653
 654         uint8_t         _unused020[0x080 - 0x004];
 655
 656         vuint32_t       icer;           /* 0x080 0xe000e180 Clear Enable Register */
 657
 658         uint8_t         _unused0a0[0x100 - 0x084];
 659
 660         vuint32_t       ispr;           /* 0x100 0xe000e200 Set Pending Register */
 661
 662         uint8_t         _unused120[0x180 - 0x104];
 663
 664         vuint32_t       icpr;           /* 0x180 0xe000e280 Clear Pending Register */
 665
 666         uint8_t         _unused1a0[0x300 - 0x184];
 667
 668         vuint32_t       ipr[8];         /* 0x300 0xe000e400 Priority Register */
 669 };
 670
 671 extern struct stm_nvic stm_nvic;
 672
 673 #define IRQ_MASK(irq)   (1 << (irq))
 674 #define IRQ_BOOL(v,irq) (((v) >> (irq)) & 1)
 675
 676 static inline void
 677 stm_nvic_set_enable(int irq) {
 678         stm_nvic.iser = IRQ_MASK(irq);
 679 }
 680
 681 static inline void
 682 stm_nvic_clear_enable(int irq) {
 683         stm_nvic.icer = IRQ_MASK(irq);
 684 }
 685
 686 static inline int
 687 stm_nvic_enabled(int irq) {
 688         return IRQ_BOOL(stm_nvic.iser, irq);
 689 }
 690
 691 static inline void
 692 stm_nvic_set_pending(int irq) {
 693         stm_nvic.ispr = IRQ_MASK(irq);
 694 }
 695
 696 static inline void
 697 stm_nvic_clear_pending(int irq) {
 698         stm_nvic.icpr = IRQ_MASK(irq);
 699 }
 700
 701 static inline int
 702 stm_nvic_pending(int irq) {
 703         return IRQ_BOOL(stm_nvic.ispr, irq);
 704 }
 705
 706 #define IRQ_PRIO_REG(irq)       ((irq) >> 2)
 707 #define IRQ_PRIO_BIT(irq)       (((irq) & 3) << 3)
 708 #define IRQ_PRIO_MASK(irq)      (0xff << IRQ_PRIO_BIT(irq))
 709
 710 static inline void
 711 stm_nvic_set_priority(int irq, uint8_t prio) {
 712         int             n = IRQ_PRIO_REG(irq);
 713         uint32_t        v;
 714
 715         v = stm_nvic.ipr[n];
 716         v &= ~IRQ_PRIO_MASK(irq);
 717         v |= (prio) << IRQ_PRIO_BIT(irq);
 718         stm_nvic.ipr[n] = v;
 719 }
 720
 721 static inline uint8_t
 722 stm_nvic_get_priority(int irq) {
 723         return (stm_nvic.ipr[IRQ_PRIO_REG(irq)] >> IRQ_PRIO_BIT(irq)) & IRQ_PRIO_MASK(0);
 724 }
 725
 726 struct stm_scb {
 727         vuint32_t       cpuid;
 728         vuint32_t       icsr;
 729         vuint32_t       vtor;
 730         vuint32_t       aircr;
 731
 732         vuint32_t       scr;
 733         vuint32_t       ccr;
 734         vuint32_t       shpr1;
 735         vuint32_t       shpr2;
 736
 737         vuint32_t       shpr3;
 738         vuint32_t       shcrs;
 739         vuint32_t       cfsr;
 740         vuint32_t       hfsr;
 741
 742         uint32_t        unused_30;
 743         vuint32_t       mmfar;
 744         vuint32_t       bfar;
 745 };
 746
 747 extern struct stm_scb stm_scb;
 748
 749 #define STM_SCB_AIRCR_VECTKEY           16
 750 #define  STM_SCB_AIRCR_VECTKEY_KEY              0x05fa
 751 #define STM_SCB_AIRCR_PRIGROUP          8
 752 #define STM_SCB_AIRCR_SYSRESETREQ       2
 753 #define STM_SCB_AIRCR_VECTCLRACTIVE     1
 754 #define STM_SCB_AIRCR_VECTRESET         0
 755
 756 #define isr(name) void stm_ ## name ## _isr(void);
 757
 758 isr(nmi)
 759 isr(hardfault)
 760 isr(memmanage)
 761 isr(busfault)
 762 isr(usagefault)
 763 isr(svc)
 764 isr(debugmon)
 765 isr(pendsv)
 766 isr(systick)
 767 isr(wwdg)
 768 isr(pvd)
 769 isr(tamper_stamp)
 770 isr(rtc_wkup)
 771 isr(flash)
 772 isr(rcc)
 773 isr(exti0)
 774 isr(exti1)
 775 isr(exti2)
 776 isr(exti3)
 777 isr(exti4)
 778 isr(dma1_channel1)
 779 isr(dma1_channel2)
 780 isr(dma1_channel3)
 781 isr(dma1_channel4)
 782 isr(dma1_channel5)
 783 isr(dma1_channel6)
 784 isr(dma1_channel7)
 785 isr(adc1)
 786 isr(usb_hp)
 787 isr(usb_lp)
 788 isr(dac)
 789 isr(comp)
 790 isr(exti9_5)
 791 isr(lcd)
 792 isr(tim9)
 793 isr(tim10)
 794 isr(tim11)
 795 isr(tim2)
 796 isr(tim3)
 797 isr(tim4)
 798 isr(i2c1_ev)
 799 isr(i2c1_er)
 800 isr(i2c2_ev)
 801 isr(i2c2_er)
 802 isr(spi1)
 803 isr(spi2)
 804 isr(usart1)
 805 isr(usart2)
 806 isr(usart3)
 807 isr(exti15_10)
 808 isr(rtc_alarm)
 809 isr(usb_fs_wkup)
 810 isr(tim6)
 811 isr(tim7)
 812
 813 #undef isr
 814
 815 #define STM_ISR_WWDG_POS                0
 816 #define STM_ISR_PVD_VDDIO2_POS          1
 817 #define STM_ISR_RTC_POS                 2
 818 #define STM_ISR_FLASH_POS               3
 819 #define STM_ISR_RCC_CRS_POS             4
 820 #define STM_ISR_EXTI0_1_POS             5
 821 #define STM_ISR_EXTI2_3_POS             6
 822 #define STM_ISR_EXTI4_15_POS            7
 823 #define STM_ISR_TSC_POS                 8
 824 #define STM_ISR_DMA_CH1_POS             9
 825 #define STM_ISR_DMA_CH2_3_DMA2_CH1_2_POS        10
 826 #define STM_ISR_DMA_CH4_5_6_7_DMA2_CH3_4_5_POS  11
 827 #define STM_ISR_ADC_COMP_POS            12
 828 #define STM_ISR_TIM1_BRK_UP_TRG_COM_POS 13
 829 #define STM_ISR_TIM1_CC_POS             14
 830 #define STM_ISR_TIM2_POS                15
 831 #define STM_ISR_TIM3_POS                16
 832 #define STM_ISR_TIM6_DAC_POS            17
 833 #define STM_ISR_TIM7_POS                18
 834 #define STM_ISR_TIM14_POS               19
 835 #define STM_ISR_TIM15_POS               20
 836 #define STM_ISR_TIM16_POS               21
 837 #define STM_ISR_TIM17_POS               22
 838 #define STM_ISR_I2C1_POS                23
 839 #define STM_ISR_I2C2_POS                24
 840 #define STM_ISR_SPI1_POS                25
 841 #define STM_ISR_SPI2_POS                26
 842 #define STM_ISR_USART1_POS              27
 843 #define STM_ISR_USART2_POS              28
 844 #define STM_ISR_UASART3_4_5_6_7_8_POS   29
 845 #define STM_ISR_CEC_CAN_POS             30
 846 #define STM_ISR_USB_POS                 31
 847
 848 struct stm_syscfg {
 849         vuint32_t       cfgr1;
 850         uint32_t        reserved_04;
 851         vuint32_t       exticr[4];
 852         vuint32_t       cfgr2;
 853         uint8_t         reserved_1c[0x80-0x1c];
 854         vuint32_t       itline[31];
 855 };
 856
 857 extern struct stm_syscfg stm_syscfg;
 858
 859 #define STM_SYSCFG_CFGR1_TIM3_DMA_RMP   30
 860 #define STM_SYSCFG_CFGR1_TIM2_DMA_RMP   29
 861 #define STM_SYSCFG_CFGR1_TIM1_DMA_RMP   28
 862 #define STM_SYSCFG_CFGR1_I2C1_DMA_RMP   27
 863 #define STM_SYSCFG_CFGR1_USART3_DMA_RMP 26
 864 #define STM_SYSCFG_CFGR1_USART2_DMA_RMP 25
 865 #define STM_SYSCFG_CFGR1_SPI2_DMA_RMP   24
 866 #define STM_SYSCFG_CFGR1_I2C_PA10_FMP   23
 867 #define STM_SYSCFG_CFGR1_I2C_PA9_FMP    22
 868 #define STM_SYSCFG_CFGR1_I2C2_FMP       21
 869 #define STM_SYSCFG_CFGR1_I2C1_FMP       20
 870 #define STM_SYSCFG_CFGR1_I2C_PB9_FMP    19
 871 #define STM_SYSCFG_CFGR1_I2C_PB8_FMP    18
 872 #define STM_SYSCFG_CFGR1_I2C_PB7_FMP    17
 873 #define STM_SYSCFG_CFGR1_I2C_PB6_FMP    16
 874 #define STM_SYSCFG_CFGR1_TIM17_DMA_RMP2 14
 875 #define STM_SYSCFG_CFGR1_TIM16_DMA_RMP2 13
 876 #define STM_SYSCFG_CFGR1_TIM17_DMA_RMP  12
 877 #define STM_SYSCFG_CFGR1_TIM16_DMA_RMP  11
 878 #define STM_SYSCFG_CFGR1_USART1_RX_DMA_RMP      10
 879 #define STM_SYSCFG_CFGR1_USART1_TX_DMA_RMP      9
 880 #define STM_SYSCFG_CFGR1_ADC_DMA_RMP            8
 881 #define STM_SYSCFG_CFGR1_IRDA_ENV_SEL   6
 882 #define  STM_SYSCFG_CFGR1_IRDA_ENV_SEL_TIMER16  0
 883 #define  STM_SYSCFG_CFGR1_IRDA_ENV_SEL_USART1   1
 884 #define  STM_SYSCFG_CFGR1_IRDA_ENV_SEL_USART4   2
 885 #define STM_SYSCFG_CFGR1_PA11_PA12_RMP  4
 886 #define STM_SYSCFG_CFGR1_MEM_MODE       0
 887 #define  STM_SYSCFG_CFGR1_MEM_MODE_MAIN_FLASH   0
 888 #define  STM_SYSCFG_CFGR1_MEM_MODE_SYSTEM_FLASH 1
 889 #define  STM_SYSCFG_CFGR1_MEM_MODE_SRAM         3
 890 #define  STM_SYSCFG_CFGR1_MEM_MODE_MASK         3
 891
 892 #define STM_SYSCFG_EXTICR_PA            0
 893 #define STM_SYSCFG_EXTICR_PB            1
 894 #define STM_SYSCFG_EXTICR_PC            2
 895 #define STM_SYSCFG_EXTICR_PD            3
 896 #define STM_SYSCFG_EXTICR_PE            4
 897 #define STM_SYSCFG_EXTICR_PF            5
 898
 899 static inline void
 900 stm_exticr_set(struct stm_gpio *gpio, int pin) {
 901         uint8_t reg = pin >> 2;
 902         uint8_t shift = (pin & 3) << 2;
 903         uint8_t val = 0;
 904
 905         /* Enable SYSCFG */
 906         stm_rcc.apb2enr |= (1 << STM_RCC_APB2ENR_SYSCFGCOMPEN);
 907
 908         if (gpio == &stm_gpioa)
 909                 val = STM_SYSCFG_EXTICR_PA;
 910         else if (gpio == &stm_gpiob)
 911                 val = STM_SYSCFG_EXTICR_PB;
 912         else if (gpio == &stm_gpioc)
 913                 val = STM_SYSCFG_EXTICR_PC;
 914         else if (gpio == &stm_gpiof)
 915                 val = STM_SYSCFG_EXTICR_PF;
 916
 917         stm_syscfg.exticr[reg] = (stm_syscfg.exticr[reg] & ~(0xf << shift)) | val << shift;
 918 }
 919
 920 struct stm_dma_channel {
 921         vuint32_t       ccr;
 922         vuint32_t       cndtr;
 923         vvoid_t         cpar;
 924         vvoid_t         cmar;
 925         vuint32_t       reserved;
 926 };
 927
 928 #define STM_NUM_DMA     5
 929
 930 struct stm_dma {
 931         vuint32_t               isr;
 932         vuint32_t               ifcr;
 933         struct stm_dma_channel  channel[STM_NUM_DMA];
 934 };
 935
 936 extern struct stm_dma stm_dma;
 937
 938 /* DMA channels go from 1 to 5, instead of 0 to 4 (sigh)
 939  */
 940
 941 #define STM_DMA_INDEX(channel)          ((channel) - 1)
 942
 943 #define STM_DMA_ISR(index)              ((index) << 2)
 944 #define STM_DMA_ISR_MASK                        0xf
 945 #define STM_DMA_ISR_TEIF                        3
 946 #define STM_DMA_ISR_HTIF                        2
 947 #define STM_DMA_ISR_TCIF                        1
 948 #define STM_DMA_ISR_GIF                         0
 949
 950 #define STM_DMA_IFCR(index)             ((index) << 2)
 951 #define STM_DMA_IFCR_MASK                       0xf
 952 #define STM_DMA_IFCR_CTEIF                      3
 953 #define STM_DMA_IFCR_CHTIF                      2
 954 #define STM_DMA_IFCR_CTCIF                      1
 955 #define STM_DMA_IFCR_CGIF                       0
 956
 957 #define STM_DMA_CCR_MEM2MEM             (14)
 958
 959 #define STM_DMA_CCR_PL                  (12)
 960 #define  STM_DMA_CCR_PL_LOW                     (0)
 961 #define  STM_DMA_CCR_PL_MEDIUM                  (1)
 962 #define  STM_DMA_CCR_PL_HIGH                    (2)
 963 #define  STM_DMA_CCR_PL_VERY_HIGH               (3)
 964 #define  STM_DMA_CCR_PL_MASK                    (3)
 965
 966 #define STM_DMA_CCR_MSIZE               (10)
 967 #define  STM_DMA_CCR_MSIZE_8                    (0)
 968 #define  STM_DMA_CCR_MSIZE_16                   (1)
 969 #define  STM_DMA_CCR_MSIZE_32                   (2)
 970 #define  STM_DMA_CCR_MSIZE_MASK                 (3)
 971
 972 #define STM_DMA_CCR_PSIZE               (8)
 973 #define  STM_DMA_CCR_PSIZE_8                    (0)
 974 #define  STM_DMA_CCR_PSIZE_16                   (1)
 975 #define  STM_DMA_CCR_PSIZE_32                   (2)
 976 #define  STM_DMA_CCR_PSIZE_MASK                 (3)
 977
 978 #define STM_DMA_CCR_MINC                (7)
 979 #define STM_DMA_CCR_PINC                (6)
 980 #define STM_DMA_CCR_CIRC                (5)
 981 #define STM_DMA_CCR_DIR                 (4)
 982 #define  STM_DMA_CCR_DIR_PER_TO_MEM             0
 983 #define  STM_DMA_CCR_DIR_MEM_TO_PER             1
 984 #define STM_DMA_CCR_TEIE                (3)
 985 #define STM_DMA_CCR_HTIE                (2)
 986 #define STM_DMA_CCR_TCIE                (1)
 987 #define STM_DMA_CCR_EN                  (0)
 988
 989 /* DMA channel assignments. When a peripheral has multiple channels
 990  * (indicated with _<number>), then it can be configured to either
 991  * channel using syscfg.cfgr1
 992  */
 993
 994 #define STM_DMA_CHANNEL_ADC_1           1
 995 #define STM_DMA_CHANNEL_ADC_2           2
 996
 997 #define STM_DMA_CHANNEL_SPI1_RX         2
 998 #define STM_DMA_CHANNEL_SPI1_TX         3
 999
1000 #define STM_DMA_CHANNEL_SPI2_RX         4
1001 #define STM_DMA_CHANNEL_SPI2_TX         5
1002
1003 #define STM_DMA_CHANNEL_USART1_TX_1     2
1004 #define STM_DMA_CHANNEL_USART1_RX_1     3
1005 #define STM_DMA_CHANNEL_USART1_TX_2     4
1006 #define STM_DMA_CHANNEL_USART1_RX_2     5
1007
1008 #define STM_DMA_CHANNEL_USART2_RX       4
1009 #define STM_DMA_CHANNEL_USART2_TX       5
1010
1011 #define STM_DMA_CHANNEL_I2C1_TX         2
1012 #define STM_DMA_CHANNEL_I2C1_RX         3
1013
1014 #define STM_DMA_CHANNEL_I2C2_TX         4
1015 #define STM_DMA_CHANNEL_I2C2_RX         5
1016
1017 #define STM_DMA_CHANNEL_TIM1_CH1        2
1018 #define STM_DMA_CHANNEL_TIM1_CH2        3
1019 #define STM_DMA_CHANNEL_TIM1_CH4        4
1020 #define STM_DMA_CHANNEL_TIM1_TRIG       4
1021 #define STM_DMA_CHANNEL_TIM1_COM        4
1022 #define STM_DMA_CHANNEL_TIM1_CH3        5
1023 #define STM_DMA_CHANNEL_TIM1_UP         5
1024
1025 #define STM_DMA_CHANNEL_TIM2_CH3        1
1026 #define STM_DMA_CHANNEL_TIM2_UP         2
1027 #define STM_DMA_CHANNEL_TIM2_CH2        3
1028 #define STM_DMA_CHANNEL_TIM2_CH4        4
1029 #define STM_DMA_CHANNEL_TIM2_CH1        5
1030
1031 #define STM_DMA_CHANNEL_TIM3_CH3        2
1032 #define STM_DMA_CHANNEL_TIM3_CH4        3
1033 #define STM_DMA_CHANNEL_TIM3_UP         3
1034 #define STM_DMA_CHANNEL_TIM3_CH1        4
1035 #define STM_DMA_CHANNEL_TIM3_TRIG       4
1036
1037 #define STM_DMA_CHANNEL_TIM6_UP_DAC     2
1038
1039 #define STM_DMA_CHANNEL_TIM15_CH1       5
1040 #define STM_DMA_CHANNEL_TIM15_UP        5
1041 #define STM_DMA_CHANNEL_TIM15_TRIG      5
1042 #define STM_DMA_CHANNEL_TIM15_COM       5
1043
1044 #define STM_DMA_CHANNEL_TIM16_CH1_1     3
1045 #define STM_DMA_CHANNEL_TIM16_UP_1      3
1046 #define STM_DMA_CHANNEL_TIM16_CH1_2     4
1047 #define STM_DMA_CHANNEL_TIM16_UP_2      4
1048
1049 #define STM_DMA_CHANNEL_TIM17_CH1_1     1
1050 #define STM_DMA_CHANNEL_TIM17_UP_1      1
1051 #define STM_DMA_CHANNEL_TIM17_CH1_2     2
1052 #define STM_DMA_CHANNEL_TIM17_UP_2      2
1053
1054 /*
1055  * Only spi channel 1 and 2 can use DMA
1056  */
1057 #define STM_NUM_SPI     2
1058
1059 struct stm_spi {
1060         vuint32_t       cr1;
1061         vuint32_t       cr2;
1062         vuint32_t       sr;
1063         vuint32_t       dr;
1064         vuint32_t       crcpr;
1065         vuint32_t       rxcrcr;
1066         vuint32_t       txcrcr;
1067 };
1068
1069 extern struct stm_spi stm_spi1, stm_spi2, stm_spi3;
1070
1071 /* SPI channels go from 1 to 3, instead of 0 to 2 (sigh)
1072  */
1073
1074 #define STM_SPI_INDEX(channel)          ((channel) - 1)
1075
1076 #define STM_SPI_CR1_BIDIMODE            15
1077 #define STM_SPI_CR1_BIDIOE              14
1078 #define STM_SPI_CR1_CRCEN               13
1079 #define STM_SPI_CR1_CRCNEXT             12
1080 #define STM_SPI_CR1_CRCL                11
1081 #define STM_SPI_CR1_RXONLY              10
1082 #define STM_SPI_CR1_SSM                 9
1083 #define STM_SPI_CR1_SSI                 8
1084 #define STM_SPI_CR1_LSBFIRST            7
1085 #define STM_SPI_CR1_SPE                 6
1086 #define STM_SPI_CR1_BR                  3
1087 #define  STM_SPI_CR1_BR_PCLK_2                  0
1088 #define  STM_SPI_CR1_BR_PCLK_4                  1
1089 #define  STM_SPI_CR1_BR_PCLK_8                  2
1090 #define  STM_SPI_CR1_BR_PCLK_16                 3
1091 #define  STM_SPI_CR1_BR_PCLK_32                 4
1092 #define  STM_SPI_CR1_BR_PCLK_64                 5
1093 #define  STM_SPI_CR1_BR_PCLK_128                6
1094 #define  STM_SPI_CR1_BR_PCLK_256                7
1095 #define  STM_SPI_CR1_BR_MASK                    7
1096
1097 #define STM_SPI_CR1_MSTR                2
1098 #define STM_SPI_CR1_CPOL                1
1099 #define STM_SPI_CR1_CPHA                0
1100
1101 #define STM_SPI_CR2_LDMA_TX     14
1102 #define STM_SPI_CR2_LDMA_RX     13
1103 #define STM_SPI_CR2_FRXTH       12
1104 #define STM_SPI_CR2_DS          8
1105 #define  STM_SPI_CR2_DS_4               0x3
1106 #define  STM_SPI_CR2_DS_5               0x4
1107 #define  STM_SPI_CR2_DS_6               0x5
1108 #define  STM_SPI_CR2_DS_7               0x6
1109 #define  STM_SPI_CR2_DS_8               0x7
1110 #define  STM_SPI_CR2_DS_9               0x8
1111 #define  STM_SPI_CR2_DS_10              0x9
1112 #define  STM_SPI_CR2_DS_11              0xa
1113 #define  STM_SPI_CR2_DS_12              0xb
1114 #define  STM_SPI_CR2_DS_13              0xc
1115 #define  STM_SPI_CR2_DS_14              0xd
1116 #define  STM_SPI_CR2_DS_15              0xe
1117 #define  STM_SPI_CR2_DS_16              0xf
1118 #define STM_SPI_CR2_TXEIE       7
1119 #define STM_SPI_CR2_RXNEIE      6
1120 #define STM_SPI_CR2_ERRIE       5
1121 #define STM_SPI_CR2_FRF         4
1122 # define STM_SPI_CR2_FRF_MOTOROLA       0
1123 # define STM_SPI_CR2_FRF_TI             1
1124 #define STM_SPI_CR2_NSSP        3
1125 #define STM_SPI_CR2_SSOE        2
1126 #define STM_SPI_CR2_TXDMAEN     1
1127 #define STM_SPI_CR2_RXDMAEN     0
1128
1129 #define STM_SPI_SR_FTLVL        11
1130 #define STM_SPI_SR_FRLVL        9
1131 #define STM_SPI_SR_FRE          8
1132 #define STM_SPI_SR_BSY          7
1133 #define STM_SPI_SR_OVR          6
1134 #define STM_SPI_SR_MODF         5
1135 #define STM_SPI_SR_CRCERR       4
1136 #define STM_SPI_SR_UDR          3
1137 #define STM_SPI_SR_CHSIDE       2
1138 #define STM_SPI_SR_TXE          1
1139 #define STM_SPI_SR_RXNE         0
1140
1141 struct stm_adc {
1142         vuint32_t       isr;
1143         vuint32_t       ier;
1144         vuint32_t       cr;
1145         vuint32_t       cfgr1;
1146
1147         vuint32_t       cfgr2;
1148         vuint32_t       smpr;
1149         vuint32_t       r_18;
1150         vuint32_t       r_1c;
1151
1152         vuint32_t       tr;
1153         vuint32_t       r_24;
1154         vuint32_t       chselr;
1155         vuint32_t       r_2c;
1156
1157         vuint32_t       r_30[4];
1158
1159         vuint32_t       dr;
1160
1161         uint8_t         r_44[0x308 - 0x44];
1162         vuint32_t       ccr;
1163 };
1164
1165 extern struct stm_adc stm_adc;
1166
1167 #define STM_ADC_ISR_AWD         7
1168 #define STM_ADC_ISR_OVR         4
1169 #define STM_ADC_ISR_EOSEQ       3
1170 #define STM_ADC_ISR_EOC         2
1171 #define STM_ADC_ISR_EOSMP       1
1172 #define STM_ADC_ISR_ADRDY       0
1173
1174 #define STM_ADC_IER_AWDIE       7
1175 #define STM_ADC_IER_OVRIE       4
1176 #define STM_ADC_IER_EOSEQIE     3
1177 #define STM_ADC_IER_EOCIE       2
1178 #define STM_ADC_IER_EOSMPIE     1
1179 #define STM_ADC_IER_ADRDYIE     0
1180
1181 #define STM_ADC_CR_ADCAL        31
1182 #define STM_ADC_CR_ADSTP        4
1183 #define STM_ADC_CR_ADSTART      2
1184 #define STM_ADC_CR_ADDIS        1
1185 #define STM_ADC_CR_ADEN         0
1186
1187 #define STM_ADC_CFGR1_AWDCH     26
1188 #define STM_ADC_CFGR1_AWDEN     23
1189 #define STM_ADC_CFGR1_AWDSGL    22
1190 #define STM_ADC_CFGR1_DISCEN    16
1191 #define STM_ADC_CFGR1_AUTOOFF   15
1192 #define STM_ADC_CFGR1_WAIT      14
1193 #define STM_ADC_CFGR1_CONT      13
1194 #define STM_ADC_CFGR1_OVRMOD    12
1195 #define STM_ADC_CFGR1_EXTEN     10
1196 #define  STM_ADC_CFGR1_EXTEN_DISABLE    0
1197 #define  STM_ADC_CFGR1_EXTEN_RISING     1
1198 #define  STM_ADC_CFGR1_EXTEN_FALLING    2
1199 #define  STM_ADC_CFGR1_EXTEN_BOTH       3
1200 #define  STM_ADC_CFGR1_EXTEN_MASK       3
1201
1202 #define STM_ADC_CFGR1_EXTSEL    6
1203 #define STM_ADC_CFGR1_ALIGN     5
1204 #define STM_ADC_CFGR1_RES       3
1205 #define  STM_ADC_CFGR1_RES_12           0
1206 #define  STM_ADC_CFGR1_RES_10           1
1207 #define  STM_ADC_CFGR1_RES_8            2
1208 #define  STM_ADC_CFGR1_RES_6            3
1209 #define  STM_ADC_CFGR1_RES_MASK         3
1210 #define STM_ADC_CFGR1_SCANDIR   2
1211 #define  STM_ADC_CFGR1_SCANDIR_UP       0
1212 #define  STM_ADC_CFGR1_SCANDIR_DOWN     1
1213 #define STM_ADC_CFGR1_DMACFG    1
1214 #define  STM_ADC_CFGR1_DMACFG_ONESHOT   0
1215 #define  STM_ADC_CFGR1_DMACFG_CIRCULAR  1
1216 #define STM_ADC_CFGR1_DMAEN     0
1217
1218 #define STM_ADC_CFGR2_CKMODE    30
1219 #define  STM_ADC_CFGR2_CKMODE_ADCCLK    0
1220 #define  STM_ADC_CFGR2_CKMODE_PCLK_2    1
1221 #define  STM_ADC_CFGR2_CKMODE_PCLK_4    2
1222
1223 #define STM_ADC_SMPR_SMP        0
1224 #define  STM_ADC_SMPR_SMP_1_5           0
1225 #define  STM_ADC_SMPR_SMP_7_5           1
1226 #define  STM_ADC_SMPR_SMP_13_5          2
1227 #define  STM_ADC_SMPR_SMP_28_5          3
1228 #define  STM_ADC_SMPR_SMP_41_5          4
1229 #define  STM_ADC_SMPR_SMP_55_5          5
1230 #define  STM_ADC_SMPR_SMP_71_5          6
1231 #define  STM_ADC_SMPR_SMP_239_5         7
1232
1233 #define STM_ADC_TR_HT           16
1234 #define STM_ADC_TR_LT           0
1235
1236 #define STM_ADC_CCR_VBATEN      24
1237 #define STM_ADC_CCR_TSEN        23
1238 #define STM_ADC_CCR_VREFEN      22
1239
1240 struct stm_cal {
1241         uint16_t        ts_cal_cold;    /* 30°C */
1242         uint16_t        vrefint_cal;
1243         uint16_t        unused_c0;
1244         uint16_t        ts_cal_hot;     /* 110°C */
1245 };
1246
1247 extern struct stm_cal   stm_cal;
1248
1249 #define stm_temp_cal_cold       30
1250 #define stm_temp_cal_hot        110
1251
1252 struct stm_dbgmcu {
1253         uint32_t        idcode;
1254 };
1255
1256 extern struct stm_dbgmcu        stm_dbgmcu;
1257
1258 static inline uint16_t
1259 stm_dev_id(void) {
1260         return stm_dbgmcu.idcode & 0xfff;
1261 }
1262
1263 struct stm_flash_size {
1264         uint16_t        f_size;
1265 };
1266
1267 extern struct stm_flash_size    stm_flash_size_04x;
1268
1269 /* Returns flash size in bytes */
1270 extern uint32_t
1271 stm_flash_size(void);
1272
1273 struct stm_device_id {
1274         uint32_t        u_id0;
1275         uint32_t        u_id1;
1276         uint32_t        u_id2;
1277 };
1278
1279 extern struct stm_device_id     stm_device_id;
1280
1281 #define STM_NUM_I2C     2
1282
1283 #define STM_I2C_INDEX(channel)  ((channel) - 1)
1284
1285 struct stm_i2c {
1286         vuint32_t       cr1;
1287         vuint32_t       cr2;
1288         vuint32_t       oar1;
1289         vuint32_t       oar2;
1290         vuint32_t       dr;
1291         vuint32_t       sr1;
1292         vuint32_t       sr2;
1293         vuint32_t       ccr;
1294         vuint32_t       trise;
1295 };
1296
1297 extern struct stm_i2c stm_i2c1, stm_i2c2;
1298
1299 #define STM_I2C_CR1_SWRST       15
1300 #define STM_I2C_CR1_ALERT       13
1301 #define STM_I2C_CR1_PEC         12
1302 #define STM_I2C_CR1_POS         11
1303 #define STM_I2C_CR1_ACK         10
1304 #define STM_I2C_CR1_STOP        9
1305 #define STM_I2C_CR1_START       8
1306 #define STM_I2C_CR1_NOSTRETCH   7
1307 #define STM_I2C_CR1_ENGC        6
1308 #define STM_I2C_CR1_ENPEC       5
1309 #define STM_I2C_CR1_ENARP       4
1310 #define STM_I2C_CR1_SMBTYPE     3
1311 #define STM_I2C_CR1_SMBUS       1
1312 #define STM_I2C_CR1_PE          0
1313
1314 #define STM_I2C_CR2_LAST        12
1315 #define STM_I2C_CR2_DMAEN       11
1316 #define STM_I2C_CR2_ITBUFEN     10
1317 #define STM_I2C_CR2_ITEVTEN     9
1318 #define STM_I2C_CR2_ITERREN     8
1319 #define STM_I2C_CR2_FREQ        0
1320 #define  STM_I2C_CR2_FREQ_2_MHZ         2
1321 #define  STM_I2C_CR2_FREQ_4_MHZ         4
1322 #define  STM_I2C_CR2_FREQ_8_MHZ         8
1323 #define  STM_I2C_CR2_FREQ_16_MHZ        16
1324 #define  STM_I2C_CR2_FREQ_32_MHZ        32
1325 #define  STM_I2C_CR2_FREQ_MASK          0x3f
1326
1327 #define STM_I2C_SR1_SMBALERT    15
1328 #define STM_I2C_SR1_TIMEOUT     14
1329 #define STM_I2C_SR1_PECERR      12
1330 #define STM_I2C_SR1_OVR         11
1331 #define STM_I2C_SR1_AF          10
1332 #define STM_I2C_SR1_ARLO        9
1333 #define STM_I2C_SR1_BERR        8
1334 #define STM_I2C_SR1_TXE         7
1335 #define STM_I2C_SR1_RXNE        6
1336 #define STM_I2C_SR1_STOPF       4
1337 #define STM_I2C_SR1_ADD10       3
1338 #define STM_I2C_SR1_BTF         2
1339 #define STM_I2C_SR1_ADDR        1
1340 #define STM_I2C_SR1_SB          0
1341
1342 #define STM_I2C_SR2_PEC         8
1343 #define  STM_I2C_SR2_PEC_MASK   0xff00
1344 #define STM_I2C_SR2_DUALF       7
1345 #define STM_I2C_SR2_SMBHOST     6
1346 #define STM_I2C_SR2_SMBDEFAULT  5
1347 #define STM_I2C_SR2_GENCALL     4
1348 #define STM_I2C_SR2_TRA         2
1349 #define STM_I2C_SR2_BUSY        1
1350 #define STM_I2C_SR2_MSL         0
1351
1352 #define STM_I2C_CCR_FS          15
1353 #define STM_I2C_CCR_DUTY        14
1354 #define STM_I2C_CCR_CCR         0
1355 #define  STM_I2C_CCR_MASK       0x7ff
1356
1357 struct stm_tim1 {
1358         vuint32_t       cr1;
1359         vuint32_t       cr2;
1360         vuint32_t       smcr;
1361         vuint32_t       dier;
1362
1363         vuint32_t       sr;
1364         vuint32_t       egr;
1365         vuint32_t       ccmr1;
1366         vuint32_t       ccmr2;
1367
1368         vuint32_t       ccer;
1369         vuint32_t       cnt;
1370         vuint32_t       psc;
1371         vuint32_t       arr;
1372
1373         vuint32_t       rcr;
1374         vuint32_t       ccr1;
1375         vuint32_t       ccr2;
1376         vuint32_t       ccr3;
1377
1378         vuint32_t       ccr4;
1379         vuint32_t       bdtr;
1380         vuint32_t       dcr;
1381         vuint32_t       dmar;
1382 };
1383
1384 #define STM_TIM1_CR1_CKD        8
1385 #define  STM_TIM1_CR1_CKD_1             0
1386 #define  STM_TIM1_CR1_CKD_2             1
1387 #define  STM_TIM1_CR1_CKD_4             2
1388
1389 #define STM_TIM1_CR1_ARPE       7
1390
1391 #define STM_TIM1_CR1_CMS        5
1392 #define  STM_TIM1_CR1_CMS_EDGE          0
1393 #define  STM_TIM1_CR1_CMS_CENTER_1      1
1394 #define  STM_TIM1_CR1_CMS_CENTER_2      2
1395 #define  STM_TIM1_CR1_CMS_CENTER_3      3
1396
1397 #define STM_TIM1_CR1_DIR        4
1398 #define  STM_TIM1_CR1_DIR_UP            0
1399 #define  STM_TIM1_CR1_DIR_DOWn          1
1400 #define STM_TIM1_CR1_OPM        3
1401 #define STM_TIM1_CR1_URS        2
1402 #define STM_TIM1_CR1_UDIS       1
1403 #define STM_TIM1_CR1_CEN        0
1404
1405 #define STM_TIM1_CR2_OIS4       14
1406 #define STM_TIM1_CR2_OIS3N      13
1407 #define STM_TIM1_CR2_OIS3       12
1408 #define STM_TIM1_CR2_OIS2N      11
1409 #define STM_TIM1_CR2_OIS2       10
1410 #define STM_TIM1_CR2_OIS1N      9
1411 #define STM_TIM1_CR2_OSI1       8
1412 #define STM_TIM1_CR2_TI1S       7
1413 #define STM_TIM1_CR2_MMS        4
1414 #define  STM_TIM1_CR2_MMS_RESET                 0
1415 #define  STM_TIM1_CR2_MMS_ENABLE                1
1416 #define  STM_TIM1_CR2_MMS_UPDATE                2
1417 #define  STM_TIM1_CR2_MMS_COMPARE_PULSE         3
1418 #define  STM_TIM1_CR2_MMS_COMPARE_OC1REF        4
1419 #define  STM_TIM1_CR2_MMS_COMPARE_OC2REF        5
1420 #define  STM_TIM1_CR2_MMS_COMPARE_OC3REF        6
1421 #define  STM_TIM1_CR2_MMS_COMPARE_OC4REF        7
1422 #define STM_TIM1_CR2_CCDS       3
1423 #define STM_TIM1_CR2_CCUS       2
1424 #define STM_TIM1_CR2_CCPC       0
1425
1426 #define STM_TIM1_SMCR_ETP       15
1427 #define STM_TIM1_SMCR_ECE       14
1428 #define STM_TIM1_SMCR_ETPS      12
1429 #define  STM_TIM1_SMCR_ETPS_OFF         0
1430 #define  STM_TIM1_SMCR_ETPS_DIV_2       1
1431 #define  STM_TIM1_SMCR_ETPS_DIV_4       2
1432 #define  STM_TIM1_SMCR_ETPS_DIV_8       3
1433
1434 #define STM_TIM1_SMCR_ETF       8
1435 #define  STM_TIM1_SMCR_ETF_NONE         0
1436 #define  STM_TIM1_SMCR_ETF_DIV_1_N_2    1
1437 #define  STM_TIM1_SMCR_ETF_DIV_1_N_4    2
1438 #define  STM_TIM1_SMCR_ETF_DIV_1_N_8    3
1439 #define  STM_TIM1_SMCR_ETF_DIV_2_N_6    4
1440 #define  STM_TIM1_SMCR_ETF_DIV_2_N_8    5
1441 #define  STM_TIM1_SMCR_ETF_DIV_4_N_6    6
1442 #define  STM_TIM1_SMCR_ETF_DIV_4_N_8    7
1443 #define  STM_TIM1_SMCR_ETF_DIV_8_N_6    8
1444 #define  STM_TIM1_SMCR_ETF_DIV_8_N_8    9
1445 #define  STM_TIM1_SMCR_ETF_DIV_16_N_5   10
1446 #define  STM_TIM1_SMCR_ETF_DIV_16_N_6   11
1447 #define  STM_TIM1_SMCR_ETF_DIV_16_N_8   12
1448 #define  STM_TIM1_SMCR_ETF_DIV_32_N_5   13
1449 #define  STM_TIM1_SMCR_ETF_DIV_32_N_6   14
1450 #define  STM_TIM1_SMCR_ETF_DIV_32_N_8   15
1451
1452 #define STM_TIM1_SMCR_MSM       7
1453 #define STM_TIM1_SMCR_TS        4
1454 #define  STM_TIM1_SMCR_TS_ITR0          0
1455 #define  STM_TIM1_SMCR_TS_ITR1          1
1456 #define  STM_TIM1_SMCR_TS_ITR2          2
1457 #define  STM_TIM1_SMCR_TS_ITR3          3
1458 #define  STM_TIM1_SMCR_TS_TI1F_ED       4
1459 #define  STM_TIM1_SMCR_TS_TI1FP1        5
1460 #define  STM_TIM1_SMCR_TS_TI2FP2        6
1461 #define  STM_TIM1_SMCR_TS_ETRF          7
1462
1463 #define STM_TIM1_SMCR_OCCS      3
1464 #define STM_TIM1_SMCR_SMS       0
1465 #define  STM_TIM1_SMCR_SMS_DISABLE      0
1466 #define  STM_TIM1_SMCR_SMS_ENCODER_1    1
1467 #define  STM_TIM1_SMCR_SMS_ENCODER_2    2
1468 #define  STM_TIM1_SMCR_SMS_ENCODER_3    3
1469 #define  STM_TIM1_SMCR_SMS_RESET        4
1470 #define  STM_TIM1_SMCR_SMS_GATED        5
1471 #define  STM_TIM1_SMCR_SMS_TRIGGER      6
1472 #define  STM_TIM1_SMCR_SMS_EXTERNAL     7
1473
1474 #define STM_TIM1_DIER_TDE       14
1475 #define STM_TIM1_DIER_COMDE     13
1476 #define STM_TIM1_DIER_CC4DE     12
1477 #define STM_TIM1_DIER_CC3DE     11
1478 #define STM_TIM1_DIER_CC2DE     10
1479 #define STM_TIM1_DIER_CC1DE     9
1480 #define STM_TIM1_DIER_UDE       8
1481 #define STM_TIM1_DIER_BIE       7
1482 #define STM_TIM1_DIER_TIE       6
1483 #define STM_TIM1_DIER_COMIE     5
1484 #define STM_TIM1_DIER_CC4IE     4
1485 #define STM_TIM1_DIER_CC3IE     3
1486 #define STM_TIM1_DIER_CC2IE     2
1487 #define STM_TIM1_DIER_CC1IE     1
1488 #define STM_TIM1_DIER_UIE       0
1489
1490 #define STM_TIM1_SR_CC4OF       12
1491 #define STM_TIM1_SR_CC3OF       11
1492 #define STM_TIM1_SR_CC2OF       10
1493 #define STM_TIM1_SR_CC1OF       9
1494 #define STM_TIM1_SR_BIF         7
1495 #define STM_TIM1_SR_TIF         6
1496 #define STM_TIM1_SR_COMIF       5
1497 #define STM_TIM1_SR_CC4IF       4
1498 #define STM_TIM1_SR_CC3IF       3
1499 #define STM_TIM1_SR_CC2IF       2
1500 #define STM_TIM1_SR_CC1IF       1
1501 #define STM_TIM1_SR_UIF         0
1502
1503 #define STM_TIM1_EGR_BG         7
1504 #define STM_TIM1_EGR_TG         6
1505 #define STM_TIM1_EGR_COMG       5
1506 #define STM_TIM1_EGR_CC4G       4
1507 #define STM_TIM1_EGR_CC3G       3
1508 #define STM_TIM1_EGR_CC2G       2
1509 #define STM_TIM1_EGR_CC1G       1
1510 #define STM_TIM1_EGR_UG         0
1511
1512 #define STM_TIM1_CCMR1_OC2CE    15
1513 #define STM_TIM1_CCMR1_OC2M     12
1514 #define STM_TIM1_CCMR1_OC2PE    11
1515 #define STM_TIM1_CCMR1_OC2FE    10
1516 #define STM_TIM1_CCMR1_CC2S     8
1517 #define STM_TIM1_CCMR1_OC1CE    7
1518 #define STM_TIM1_CCMR1_OC1M     4
1519 #define  STM_TIM1_CCMR_OCM_FROZEN               0
1520 #define  STM_TIM1_CCMR_OCM_1_HIGH_MATCH         1
1521 #define  STM_TIM1_CCMR_OCM_1_LOW_MATCH          2
1522 #define  STM_TIM1_CCMR_OCM_TOGGLE               3
1523 #define  STM_TIM1_CCMR_OCM_FORCE_LOW            4
1524 #define  STM_TIM1_CCMR_OCM_FORCE_HIGH           5
1525 #define  STM_TIM1_CCMR_OCM_PWM_MODE_1           6
1526 #define  STM_TIM1_CCMR_OCM_PWM_MODE_2           7
1527
1528 #define STM_TIM1_CCMR1_OC1PE    3
1529 #define STM_TIM1_CCMR1_OC1FE    2
1530 #define STM_TIM1_CCMR1_CC1S     0
1531 #define  STM_TIM1_CCMR_CCS_OUTPUT       0
1532 #define  STM_TIM1_CCMR_CCS_INPUT_TI1    1
1533 #define  STM_TIM1_CCMR_CCS_INPUT_TI2    2
1534 #define  STM_TIM1_CCMR_CCS_INPUT_TRC    3
1535
1536 #define STM_TIM1_CCMR1_IC2F     12
1537 #define STM_TIM1_CCMR1_IC2PSC   10
1538 #define STM_TIM1_CCMR1_CC2S     8
1539 #define STM_TIM1_CCMR1_IC1F     4
1540 #define  STM_TIM1_CCMR1_IC1F_NONE       0
1541 #define  STM_TIM1_CCMR1_IC1F_DIV_1_N_2  1
1542 #define  STM_TIM1_CCMR1_IC1F_DIV_1_N_4  2
1543 #define  STM_TIM1_CCMR1_IC1F_DIV_1_N_8  3
1544 #define  STM_TIM1_CCMR1_IC1F_DIV_2_N_6  4
1545 #define  STM_TIM1_CCMR1_IC1F_DIV_2_N_8  5
1546 #define  STM_TIM1_CCMR1_IC1F_DIV_4_N_6  6
1547 #define  STM_TIM1_CCMR1_IC1F_DIV_4_N_8  7
1548 #define  STM_TIM1_CCMR1_IC1F_DIV_8_N_6  8
1549 #define  STM_TIM1_CCMR1_IC1F_DIV_8_N_8  9
1550 #define  STM_TIM1_CCMR1_IC1F_DIV_16_N_5 10
1551 #define  STM_TIM1_CCMR1_IC1F_DIV_16_N_6 11
1552 #define  STM_TIM1_CCMR1_IC1F_DIV_16_N_8 12
1553 #define  STM_TIM1_CCMR1_IC1F_DIV_32_N_5 13
1554 #define  STM_TIM1_CCMR1_IC1F_DIV_32_N_6 14
1555 #define  STM_TIM1_CCMR1_IC1F_DIV_32_N_8 15
1556
1557 #define STM_TIM1_CCMR1_IC1PSC   2
1558 #define  STM_TIM1_CCMR1_IC1PSC_NONE     0
1559 #define  STM_TIM1_CCMR1_IC1PSC_2        1
1560 #define  STM_TIM1_CCMR1_IC1PSC_4        2
1561 #define  STM_TIM1_CCMR1_IC1PSC_8        3
1562
1563 #define STM_TIM1_CCMR1_CC1S     0
1564 #define  STM_TIM1_CCMR1_CC1S_OUTPUT     0
1565 #define  STM_TIM1_CCMR1_CC1S_TI1        1
1566 #define  STM_TIM1_CCMR1_CC1S_TI2        2
1567 #define  STM_TIM1_CCMR1_CC1S_TRC        3
1568
1569 #define STM_TIM1_CCMR2_OC4CE    15
1570 #define STM_TIM1_CCMR2_OC4M     12
1571 #define STM_TIM1_CCMR2_OC4PE    11
1572 #define STM_TIM1_CCMR2_OC4FE    10
1573 #define STM_TIM1_CCMR2_CC4S     8
1574 #define  STM_TIM1_CCMR2_CCS_OUTPUT      0
1575 #define  STM_TIM1_CCMR2_CCS_INPUT_TI3   1
1576 #define  STM_TIM1_CCMR2_CCS_INPUT_TI4   2
1577 #define  STM_TIM1_CCMR2_CCS_INPUT_TRC   3
1578 #define STM_TIM1_CCMR2_OC3CE    7
1579 #define STM_TIM1_CCMR2_OC3M     4
1580 #define STM_TIM1_CCMR2_OC3PE    3
1581 #define STM_TIM1_CCMR2_OC3FE    2
1582 #define STM_TIM1_CCMR2_CC3S     0
1583
1584 #define STM_TIM1_CCMR2_IC4F     12
1585 #define STM_TIM1_CCMR2_IC2PSC   10
1586 #define STM_TIM1_CCMR2_CC4S     8
1587 #define STM_TIM1_CCMR2_IC3F     4
1588 #define  STM_TIM1_CCMR2_IC1F_NONE       0
1589 #define  STM_TIM1_CCMR2_IC1F_DIV_1_N_2  1
1590 #define  STM_TIM1_CCMR2_IC1F_DIV_1_N_4  2
1591 #define  STM_TIM1_CCMR2_IC1F_DIV_1_N_8  3
1592 #define  STM_TIM1_CCMR2_IC1F_DIV_2_N_6  4
1593 #define  STM_TIM1_CCMR2_IC1F_DIV_2_N_8  5
1594 #define  STM_TIM1_CCMR2_IC1F_DIV_4_N_6  6
1595 #define  STM_TIM1_CCMR2_IC1F_DIV_4_N_8  7
1596 #define  STM_TIM1_CCMR2_IC1F_DIV_8_N_6  8
1597 #define  STM_TIM1_CCMR2_IC1F_DIV_8_N_8  9
1598 #define  STM_TIM1_CCMR2_IC1F_DIV_16_N_5 10
1599 #define  STM_TIM1_CCMR2_IC1F_DIV_16_N_6 11
1600 #define  STM_TIM1_CCMR2_IC1F_DIV_16_N_8 12
1601 #define  STM_TIM1_CCMR2_IC1F_DIV_32_N_5 13
1602 #define  STM_TIM1_CCMR2_IC1F_DIV_32_N_6 14
1603 #define  STM_TIM1_CCMR2_IC1F_DIV_32_N_8 15
1604
1605 #define STM_TIM1_CCER_CC4P      13
1606 #define STM_TIM1_CCER_CC4E      12
1607 #define STM_TIM1_CCER_CC3NP     11
1608 #define STM_TIM1_CCER_CC3NE     10
1609 #define STM_TIM1_CCER_CC3P      9
1610 #define STM_TIM1_CCER_CC3E      8
1611 #define STM_TIM1_CCER_CC2NP     7
1612 #define STM_TIM1_CCER_CC2NE     6
1613 #define STM_TIM1_CCER_CC2P      5
1614 #define STM_TIM1_CCER_CC2E      4
1615 #define STM_TIM1_CCER_CC1BP     3
1616 #define STM_TIM1_CCER_CC1NE     2
1617 #define STM_TIM1_CCER_CC1P      1
1618 #define STM_TIM1_CCER_CC1E      0
1619
1620 #define STM_TIM1_BDTR_MOE       15
1621 #define STM_TIM1_BDTR_AOE       14
1622 #define STM_TIM1_BDTR_BKP       13
1623 #define STM_TIM1_BDTR_BKE       12
1624 #define STM_TIM1_BDTR_OSSR      11
1625 #define STM_TIM1_BDTR_OSSI      10
1626 #define STM_TIM1_BDTR_LOCK      8
1627 #define  STM_TIM1_BDTR_LOCK_OFF         0
1628 #define  STM_TIM1_BDTR_LOCK_LEVEL_1     1
1629 #define  STM_TIM1_BDTR_LOCK_LEVEL_2     2
1630 #define  STM_TIM1_BDTR_LOCK_LEVEL_3     3
1631
1632 #define STM_TIM1_BDTR_DTG       0
1633
1634 #define STM_TIM1_DCR_DBL        8
1635 #define STM_TIM1_DCR_DBA        0
1636
1637 extern struct stm_tim1 stm_tim1;
1638
1639 #define stm_tim1        (*(struct stm_tim1 *)0x40012c00)
1640
1641 struct stm_tim23 {
1642         vuint32_t       cr1;
1643         vuint32_t       cr2;
1644         vuint32_t       smcr;
1645         vuint32_t       dier;
1646
1647         vuint32_t       sr;
1648         vuint32_t       egr;
1649         vuint32_t       ccmr1;
1650         vuint32_t       ccmr2;
1651
1652         vuint32_t       ccer;
1653         vuint32_t       cnt;
1654         vuint32_t       psc;
1655         vuint32_t       arr;
1656
1657         uint32_t        reserved_30;
1658         vuint32_t       ccr1;
1659         vuint32_t       ccr2;
1660         vuint32_t       ccr3;
1661
1662         vuint32_t       ccr4;
1663         uint32_t        reserved_44;
1664         vuint32_t       dcr;
1665         vuint32_t       dmar;
1666 };
1667
1668 extern struct stm_tim23 stm_tim2, stm_tim3;
1669
1670 #define stm_tim3        (*(struct stm_tim23 *) 0x40000400)
1671 #define stm_tim2        (*(struct stm_tim23 *) 0x40000000)
1672
1673 #define STM_TIM23_CR1_CKD       8
1674 #define  STM_TIM23_CR1_CKD_1            0
1675 #define  STM_TIM23_CR1_CKD_2            1
1676 #define  STM_TIM23_CR1_CKD_4            2
1677 #define  STM_TIM23_CR1_CKD_MASK 3
1678 #define STM_TIM23_CR1_ARPE      7
1679 #define STM_TIM23_CR1_CMS       5
1680 #define  STM_TIM23_CR1_CMS_EDGE         0
1681 #define  STM_TIM23_CR1_CMS_CENTER_1     1
1682 #define  STM_TIM23_CR1_CMS_CENTER_2     2
1683 #define  STM_TIM23_CR1_CMS_CENTER_3     3
1684 #define  STM_TIM23_CR1_CMS_MASK         3
1685 #define STM_TIM23_CR1_DIR       4
1686 #define  STM_TIM23_CR1_DIR_UP           0
1687 #define  STM_TIM23_CR1_DIR_DOWN         1
1688 #define STM_TIM23_CR1_OPM       3
1689 #define STM_TIM23_CR1_URS       2
1690 #define STM_TIM23_CR1_UDIS      1
1691 #define STM_TIM23_CR1_CEN       0
1692
1693 #define STM_TIM23_CR2_TI1S      7
1694 #define STM_TIM23_CR2_MMS       4
1695 #define  STM_TIM23_CR2_MMS_RESET                0
1696 #define  STM_TIM23_CR2_MMS_ENABLE               1
1697 #define  STM_TIM23_CR2_MMS_UPDATE               2
1698 #define  STM_TIM23_CR2_MMS_COMPARE_PULSE        3
1699 #define  STM_TIM23_CR2_MMS_COMPARE_OC1REF       4
1700 #define  STM_TIM23_CR2_MMS_COMPARE_OC2REF       5
1701 #define  STM_TIM23_CR2_MMS_COMPARE_OC3REF       6
1702 #define  STM_TIM23_CR2_MMS_COMPARE_OC4REF       7
1703 #define  STM_TIM23_CR2_MMS_MASK                 7
1704 #define STM_TIM23_CR2_CCDS      3
1705
1706 #define STM_TIM23_SMCR_ETP      15
1707 #define STM_TIM23_SMCR_ECE      14
1708 #define STM_TIM23_SMCR_ETPS     12
1709 #define  STM_TIM23_SMCR_ETPS_OFF                0
1710 #define  STM_TIM23_SMCR_ETPS_DIV_2              1
1711 #define  STM_TIM23_SMCR_ETPS_DIV_4              2
1712 #define  STM_TIM23_SMCR_ETPS_DIV_8              3
1713 #define  STM_TIM23_SMCR_ETPS_MASK               3
1714 #define STM_TIM23_SMCR_ETF      8
1715 #define  STM_TIM23_SMCR_ETF_NONE                0
1716 #define  STM_TIM23_SMCR_ETF_INT_N_2             1
1717 #define  STM_TIM23_SMCR_ETF_INT_N_4             2
1718 #define  STM_TIM23_SMCR_ETF_INT_N_8             3
1719 #define  STM_TIM23_SMCR_ETF_DTS_2_N_6           4
1720 #define  STM_TIM23_SMCR_ETF_DTS_2_N_8           5
1721 #define  STM_TIM23_SMCR_ETF_DTS_4_N_6           6
1722 #define  STM_TIM23_SMCR_ETF_DTS_4_N_8           7
1723 #define  STM_TIM23_SMCR_ETF_DTS_8_N_6           8
1724 #define  STM_TIM23_SMCR_ETF_DTS_8_N_8           9
1725 #define  STM_TIM23_SMCR_ETF_DTS_16_N_5          10
1726 #define  STM_TIM23_SMCR_ETF_DTS_16_N_6          11
1727 #define  STM_TIM23_SMCR_ETF_DTS_16_N_8          12
1728 #define  STM_TIM23_SMCR_ETF_DTS_32_N_5          13
1729 #define  STM_TIM23_SMCR_ETF_DTS_32_N_6          14
1730 #define  STM_TIM23_SMCR_ETF_DTS_32_N_8          15
1731 #define  STM_TIM23_SMCR_ETF_MASK                15
1732 #define STM_TIM23_SMCR_MSM      7
1733 #define STM_TIM23_SMCR_TS       4
1734 #define  STM_TIM23_SMCR_TS_ITR0                 0
1735 #define  STM_TIM23_SMCR_TS_ITR1                 1
1736 #define  STM_TIM23_SMCR_TS_ITR2                 2
1737 #define  STM_TIM23_SMCR_TS_ITR3                 3
1738 #define  STM_TIM23_SMCR_TS_TI1F_ED              4
1739 #define  STM_TIM23_SMCR_TS_TI1FP1               5
1740 #define  STM_TIM23_SMCR_TS_TI2FP2               6
1741 #define  STM_TIM23_SMCR_TS_ETRF                 7
1742 #define  STM_TIM23_SMCR_TS_MASK                 7
1743 #define STM_TIM23_SMCR_OCCS     3
1744 #define STM_TIM23_SMCR_SMS      0
1745 #define  STM_TIM23_SMCR_SMS_DISABLE             0
1746 #define  STM_TIM23_SMCR_SMS_ENCODER_MODE_1      1
1747 #define  STM_TIM23_SMCR_SMS_ENCODER_MODE_2      2
1748 #define  STM_TIM23_SMCR_SMS_ENCODER_MODE_3      3
1749 #define  STM_TIM23_SMCR_SMS_RESET_MODE          4
1750 #define  STM_TIM23_SMCR_SMS_GATED_MODE          5
1751 #define  STM_TIM23_SMCR_SMS_TRIGGER_MODE        6
1752 #define  STM_TIM23_SMCR_SMS_EXTERNAL_CLOCK      7
1753 #define  STM_TIM23_SMCR_SMS_MASK                7
1754
1755 #define STM_TIM23_SR_CC4OF      12
1756 #define STM_TIM23_SR_CC3OF      11
1757 #define STM_TIM23_SR_CC2OF      10
1758 #define STM_TIM23_SR_CC1OF      9
1759 #define STM_TIM23_SR_TIF        6
1760 #define STM_TIM23_SR_CC4IF      4
1761 #define STM_TIM23_SR_CC3IF      3
1762 #define STM_TIM23_SR_CC2IF      2
1763 #define STM_TIM23_SR_CC1IF      1
1764 #define STM_TIM23_SR_UIF        0
1765
1766 #define STM_TIM23_EGR_TG        6
1767 #define STM_TIM23_EGR_CC4G      4
1768 #define STM_TIM23_EGR_CC3G      3
1769 #define STM_TIM23_EGR_CC2G      2
1770 #define STM_TIM23_EGR_CC1G      1
1771 #define STM_TIM23_EGR_UG        0
1772
1773 #define STM_TIM23_CCMR1_OC2CE   15
1774 #define STM_TIM23_CCMR1_OC2M    12
1775 #define  STM_TIM23_CCMR1_OC2M_FROZEN                    0
1776 #define  STM_TIM23_CCMR1_OC2M_SET_HIGH_ON_MATCH         1
1777 #define  STM_TIM23_CCMR1_OC2M_SET_LOW_ON_MATCH          2
1778 #define  STM_TIM23_CCMR1_OC2M_TOGGLE                    3
1779 #define  STM_TIM23_CCMR1_OC2M_FORCE_LOW                 4
1780 #define  STM_TIM23_CCMR1_OC2M_FORCE_HIGH                5
1781 #define  STM_TIM23_CCMR1_OC2M_PWM_MODE_1                6
1782 #define  STM_TIM23_CCMR1_OC2M_PWM_MODE_2                7
1783 #define  STM_TIM23_CCMR1_OC2M_MASK                      7
1784 #define STM_TIM23_CCMR1_OC2PE   11
1785 #define STM_TIM23_CCMR1_OC2FE   10
1786 #define STM_TIM23_CCMR1_CC2S    8
1787 #define  STM_TIM23_CCMR1_CC2S_OUTPUT                    0
1788 #define  STM_TIM23_CCMR1_CC2S_INPUT_TI2                 1
1789 #define  STM_TIM23_CCMR1_CC2S_INPUT_TI1                 2
1790 #define  STM_TIM23_CCMR1_CC2S_INPUT_TRC                 3
1791 #define  STM_TIM23_CCMR1_CC2S_MASK                      3
1792
1793 #define STM_TIM23_CCMR1_OC1CE   7
1794 #define STM_TIM23_CCMR1_OC1M    4
1795 #define  STM_TIM23_CCMR1_OC1M_FROZEN                    0
1796 #define  STM_TIM23_CCMR1_OC1M_SET_HIGH_ON_MATCH         1
1797 #define  STM_TIM23_CCMR1_OC1M_SET_LOW_ON_MATCH          2
1798 #define  STM_TIM23_CCMR1_OC1M_TOGGLE                    3
1799 #define  STM_TIM23_CCMR1_OC1M_FORCE_LOW                 4
1800 #define  STM_TIM23_CCMR1_OC1M_FORCE_HIGH                5
1801 #define  STM_TIM23_CCMR1_OC1M_PWM_MODE_1                6
1802 #define  STM_TIM23_CCMR1_OC1M_PWM_MODE_2                7
1803 #define  STM_TIM23_CCMR1_OC1M_MASK                      7
1804 #define STM_TIM23_CCMR1_OC1PE   11
1805 #define STM_TIM23_CCMR1_OC1FE   2
1806 #define STM_TIM23_CCMR1_CC1S    0
1807 #define  STM_TIM23_CCMR1_CC1S_OUTPUT                    0
1808 #define  STM_TIM23_CCMR1_CC1S_INPUT_TI1                 1
1809 #define  STM_TIM23_CCMR1_CC1S_INPUT_TI2                 2
1810 #define  STM_TIM23_CCMR1_CC1S_INPUT_TRC                 3
1811 #define  STM_TIM23_CCMR1_CC1S_MASK                      3
1812
1813 #define STM_TIM23_CCMR2_OC4CE   15
1814 #define STM_TIM23_CCMR2_OC4M    12
1815 #define  STM_TIM23_CCMR2_OC4M_FROZEN                    0
1816 #define  STM_TIM23_CCMR2_OC4M_SET_HIGH_ON_MATCH 1
1817 #define  STM_TIM23_CCMR2_OC4M_SET_LOW_ON_MATCH          2
1818 #define  STM_TIM23_CCMR2_OC4M_TOGGLE                    3
1819 #define  STM_TIM23_CCMR2_OC4M_FORCE_LOW                 4
1820 #define  STM_TIM23_CCMR2_OC4M_FORCE_HIGH                5
1821 #define  STM_TIM23_CCMR2_OC4M_PWM_MODE_1                6
1822 #define  STM_TIM23_CCMR2_OC4M_PWM_MODE_2                7
1823 #define  STM_TIM23_CCMR2_OC4M_MASK                      7
1824 #define STM_TIM23_CCMR2_OC4PE   11
1825 #define STM_TIM23_CCMR2_OC4FE   10
1826 #define STM_TIM23_CCMR2_CC4S    8
1827 #define  STM_TIM23_CCMR2_CC4S_OUTPUT                    0
1828 #define  STM_TIM23_CCMR2_CC4S_INPUT_TI4                 1
1829 #define  STM_TIM23_CCMR2_CC4S_INPUT_TI3                 2
1830 #define  STM_TIM23_CCMR2_CC4S_INPUT_TRC                 3
1831 #define  STM_TIM23_CCMR2_CC4S_MASK                      3
1832
1833 #define STM_TIM23_CCMR2_OC3CE   7
1834 #define STM_TIM23_CCMR2_OC3M    4
1835 #define  STM_TIM23_CCMR2_OC3M_FROZEN                    0
1836 #define  STM_TIM23_CCMR2_OC3M_SET_HIGH_ON_MATCH         1
1837 #define  STM_TIM23_CCMR2_OC3M_SET_LOW_ON_MATCH          2
1838 #define  STM_TIM23_CCMR2_OC3M_TOGGLE                    3
1839 #define  STM_TIM23_CCMR2_OC3M_FORCE_LOW                 4
1840 #define  STM_TIM23_CCMR2_OC3M_FORCE_HIGH                5
1841 #define  STM_TIM23_CCMR2_OC3M_PWM_MODE_1                6
1842 #define  STM_TIM23_CCMR2_OC3M_PWM_MODE_2                7
1843 #define  STM_TIM23_CCMR2_OC3M_MASK                      7
1844 #define STM_TIM23_CCMR2_OC3PE   11
1845 #define STM_TIM23_CCMR2_OC3FE   2
1846 #define STM_TIM23_CCMR2_CC3S    0
1847 #define  STM_TIM23_CCMR2_CC3S_OUTPUT                    0
1848 #define  STM_TIM23_CCMR2_CC3S_INPUT_TI3                 1
1849 #define  STM_TIM23_CCMR2_CC3S_INPUT_TI4                 2
1850 #define  STM_TIM23_CCMR2_CC3S_INPUT_TRC                 3
1851 #define  STM_TIM23_CCMR2_CC3S_MASK                      3
1852
1853 #define STM_TIM23_CCER_CC4NP    15
1854 #define STM_TIM23_CCER_CC4P     13
1855 #define STM_TIM23_CCER_CC4E     12
1856 #define STM_TIM23_CCER_CC3NP    11
1857 #define STM_TIM23_CCER_CC3P     9
1858 #define STM_TIM23_CCER_CC3E     8
1859 #define STM_TIM23_CCER_CC2NP    7
1860 #define STM_TIM23_CCER_CC2P     5
1861 #define STM_TIM23_CCER_CC2E     4
1862 #define STM_TIM23_CCER_CC1NP    3
1863 #define STM_TIM23_CCER_CC1P     1
1864 #define STM_TIM23_CCER_CC1E     0
1865
1866 struct stm_usb {
1867         struct {
1868                 vuint16_t       r;
1869                 uint16_t        _;
1870         } epr[8];
1871         uint8_t         reserved_20[0x40 - 0x20];
1872         vuint16_t       cntr;
1873         uint16_t        reserved_42;
1874         vuint16_t       istr;
1875         uint16_t        reserved_46;
1876         vuint16_t       fnr;
1877         uint16_t        reserved_4a;
1878         vuint16_t       daddr;
1879         uint16_t        reserved_4e;
1880         vuint16_t       btable;
1881         uint16_t        reserved_52;
1882         vuint16_t       lpmcsr;
1883         uint16_t        reserved_56;
1884         vuint16_t       bcdr;
1885         uint16_t        reserved_5a;
1886 };
1887
1888 extern struct stm_usb stm_usb;
1889
1890 #define STM_USB_EPR_CTR_RX      15
1891 #define  STM_USB_EPR_CTR_RX_WRITE_INVARIANT             1
1892 #define STM_USB_EPR_DTOG_RX     14
1893 #define STM_USB_EPR_SW_BUF_TX   14
1894 #define STM_USB_EPR_DTOG_RX_WRITE_INVARIANT             0
1895 #define STM_USB_EPR_STAT_RX     12
1896 #define  STM_USB_EPR_STAT_RX_DISABLED                   0
1897 #define  STM_USB_EPR_STAT_RX_STALL                      1
1898 #define  STM_USB_EPR_STAT_RX_NAK                        2
1899 #define  STM_USB_EPR_STAT_RX_VALID                      3
1900 #define  STM_USB_EPR_STAT_RX_MASK                       3
1901 #define  STM_USB_EPR_STAT_RX_WRITE_INVARIANT            0
1902 #define STM_USB_EPR_SETUP       11
1903 #define STM_USB_EPR_EP_TYPE     9
1904 #define  STM_USB_EPR_EP_TYPE_BULK                       0
1905 #define  STM_USB_EPR_EP_TYPE_CONTROL                    1
1906 #define  STM_USB_EPR_EP_TYPE_ISO                        2
1907 #define  STM_USB_EPR_EP_TYPE_INTERRUPT                  3
1908 #define  STM_USB_EPR_EP_TYPE_MASK                       3
1909 #define STM_USB_EPR_EP_KIND     8
1910 #define  STM_USB_EPR_EP_KIND_SNGL_BUF                   0       /* Bulk */
1911 #define  STM_USB_EPR_EP_KIND_DBL_BUF                    1       /* Bulk */
1912 #define  STM_USB_EPR_EP_KIND_NO_STATUS_OUT              0       /* Control */
1913 #define  STM_USB_EPR_EP_KIND_STATUS_OUT                 1       /* Control */
1914 #define STM_USB_EPR_CTR_TX      7
1915 #define  STM_USB_CTR_TX_WRITE_INVARIANT                 1
1916 #define STM_USB_EPR_DTOG_TX     6
1917 #define STM_USB_EPR_SW_BUF_RX   6
1918 #define  STM_USB_EPR_DTOG_TX_WRITE_INVARIANT            0
1919 #define STM_USB_EPR_STAT_TX     4
1920 #define  STM_USB_EPR_STAT_TX_DISABLED                   0
1921 #define  STM_USB_EPR_STAT_TX_STALL                      1
1922 #define  STM_USB_EPR_STAT_TX_NAK                        2
1923 #define  STM_USB_EPR_STAT_TX_VALID                      3
1924 #define  STM_USB_EPR_STAT_TX_WRITE_INVARIANT            0
1925 #define  STM_USB_EPR_STAT_TX_MASK                       3
1926 #define STM_USB_EPR_EA          0
1927 #define  STM_USB_EPR_EA_MASK                            0xf
1928
1929 #define STM_USB_CNTR_CTRM       15
1930 #define STM_USB_CNTR_PMAOVRM    14
1931 #define STM_USB_CNTR_ERRM       13
1932 #define STM_USB_CNTR_WKUPM      12
1933 #define STM_USB_CNTR_SUSPM      11
1934 #define STM_USB_CNTR_RESETM     10
1935 #define STM_USB_CNTR_SOFM       9
1936 #define STM_USB_CNTR_ESOFM      8
1937 #define STM_USB_CNTR_RESUME     4
1938 #define STM_USB_CNTR_FSUSP      3
1939 #define STM_USB_CNTR_LP_MODE    2
1940 #define STM_USB_CNTR_PDWN       1
1941 #define STM_USB_CNTR_FRES       0
1942
1943 #define STM_USB_ISTR_CTR        15
1944 #define STM_USB_ISTR_PMAOVR     14
1945 #define STM_USB_ISTR_ERR        13
1946 #define STM_USB_ISTR_WKUP       12
1947 #define STM_USB_ISTR_SUSP       11
1948 #define STM_USB_ISTR_RESET      10
1949 #define STM_USB_ISTR_SOF        9
1950 #define STM_USB_ISTR_ESOF       8
1951 #define STM_USB_L1REQ           7
1952 #define STM_USB_ISTR_DIR        4
1953 #define STM_USB_ISTR_EP_ID      0
1954 #define  STM_USB_ISTR_EP_ID_MASK                0xf
1955
1956 #define STM_USB_FNR_RXDP        15
1957 #define STM_USB_FNR_RXDM        14
1958 #define STM_USB_FNR_LCK         13
1959 #define STM_USB_FNR_LSOF        11
1960 #define  STM_USB_FNR_LSOF_MASK                  0x3
1961 #define STM_USB_FNR_FN          0
1962 #define  STM_USB_FNR_FN_MASK                    0x7ff
1963
1964 #define STM_USB_DADDR_EF        7
1965 #define STM_USB_DADDR_ADD       0
1966 #define  STM_USB_DADDR_ADD_MASK                 0x7f
1967
1968 #define STM_USB_BCDR_DPPU       15
1969 #define STM_USB_BCDR_PS2DET     7
1970 #define STM_USB_BCDR_SDET       6
1971 #define STM_USB_BCDR_PDET       5
1972 #define STM_USB_BCDR_DCDET      4
1973 #define STM_USB_BCDR_SDEN       3
1974 #define STM_USB_BCDR_PDEN       2
1975 #define STM_USB_BCDR_DCDEN      1
1976 #define STM_USB_BCDR_BCDEN      0
1977
1978 union stm_usb_bdt {
1979         struct {
1980                 vuint16_t       addr_tx;
1981                 vuint16_t       count_tx;
1982                 vuint16_t       addr_rx;
1983                 vuint16_t       count_rx;
1984         } single;
1985         struct {
1986                 vuint16_t       addr;
1987                 vuint16_t       count;
1988         } double_tx[2];
1989         struct {
1990                 vuint16_t       addr;
1991                 vuint16_t       count;
1992         } double_rx[2];
1993 };
1994
1995 #define STM_USB_BDT_COUNT_RX_BL_SIZE    15
1996 #define STM_USB_BDT_COUNT_RX_NUM_BLOCK  10
1997 #define  STM_USB_BDT_COUNT_RX_NUM_BLOCK_MASK    0x1f
1998 #define STM_USB_BDT_COUNT_RX_COUNT_RX   0
1999 #define  STM_USB_BDT_COUNT_RX_COUNT_RX_MASK     0x1ff
2000
2001 #define STM_USB_BDT_SIZE        8
2002
2003 /* We'll use the first block of usb SRAM for the BDT */
2004 extern uint8_t stm_usb_sram[] __attribute__((aligned(4)));
2005 extern union stm_usb_bdt stm_usb_bdt[STM_USB_BDT_SIZE] __attribute__((aligned(4)));
2006
2007 #define stm_usb_sram    ((uint8_t *) 0x40006000)
2008 #define stm_usb_bdt     ((union stm_usb_bdt *) 0x40006000)
2009
2010 struct stm_exti {
2011         vuint32_t       imr;
2012         vuint32_t       emr;
2013         vuint32_t       rtsr;
2014         vuint32_t       ftsr;
2015
2016         vuint32_t       swier;
2017         vuint32_t       pr;
2018 };
2019
2020 extern struct stm_exti stm_exti;
2021
2022 struct stm_usart {
2023         vuint32_t       cr1;    /* control register 1 */
2024         vuint32_t       cr2;    /* control register 2 */
2025         vuint32_t       cr3;    /* control register 3 */
2026         vuint32_t       brr;    /* baud rate register */
2027
2028         vuint32_t       gtpr;   /* guard time and prescaler */
2029         vuint32_t       rtor;   /* receiver timeout register */
2030         vuint32_t       rqr;    /* request register */
2031         vuint32_t       isr;    /* interrupt and status register */
2032
2033         vuint32_t       icr;    /* interrupt flag clear register */
2034         vuint32_t       rdr;    /* receive data register */
2035         vuint32_t       tdr;    /* transmit data register */
2036 };
2037
2038 #define STM_USART_CR1_M1        28
2039 #define STM_USART_CR1_EOBIE     27
2040 #define STM_USART_CR1_RTOIE     26
2041 #define STM_USART_CR1_DEAT      21
2042 #define STM_USART_CR1_DEDT      16
2043 #define STM_USART_CR1_OVER8     15
2044 #define STM_USART_CR1_CMIE      14
2045 #define STM_USART_CR1_MME       13
2046 #define STM_USART_CR1_M0        12
2047 #define STM_USART_CR1_WAKE      11
2048 #define STM_USART_CR1_PCE       10
2049 #define STM_USART_CR1_PS        9
2050 #define STM_USART_CR1_PEIE      8
2051 #define STM_USART_CR1_TXEIE     7
2052 #define STM_USART_CR1_TCIE      6
2053 #define STM_USART_CR1_RXNEIE    5
2054 #define STM_USART_CR1_IDLEIE    4
2055 #define STM_USART_CR1_TE        3
2056 #define STM_USART_CR1_RE        2
2057 #define STM_USART_CR1_UESM      1
2058 #define STM_USART_CR1_UE        0
2059
2060 #define STM_USART_CR2_ADD       24
2061 #define STM_USART_CR2_RTOEN     23
2062 #define STM_USART_CR2_ABRMOD    21
2063 #define STM_USART_CR2_ABREN     20
2064 #define STM_USART_CR2_MSBFIRST  19
2065 #define STM_USART_CR2_DATAINV   18
2066 #define STM_USART_CR2_TXINV     17
2067 #define STM_USART_CR2_RXINV     16
2068 #define STM_USART_CR2_SWAP      15
2069 #define STM_USART_CR2_LINEN     14
2070 #define STM_USART_CR2_STOP      12
2071 #define STM_USART_CR2_CLKEN     11
2072 #define STM_USART_CR2_CPOL      10
2073 #define STM_USART_CR2_CHPA      9
2074 #define STM_USART_CR2_LBCL      8
2075 #define STM_USART_CR2_LBDIE     6
2076 #define STM_USART_CR2_LBDL      5
2077 #define STM_USART_CR2_ADDM7     4
2078
2079 #define STM_USART_CR3_WUFIE     22
2080 #define STM_USART_CR3_WUS       20
2081 #define STM_USART_CR3_SCARCNT   17
2082 #define STM_USART_CR3_DEP       15
2083 #define STM_USART_CR3_DEM       14
2084 #define STM_USART_CR3_DDRE      13
2085 #define STM_USART_CR3_OVRDIS    12
2086 #define STM_USART_CR3_ONEBIT    11
2087 #define STM_USART_CR3_CTIIE     10
2088 #define STM_USART_CR3_CTSE      9
2089 #define STM_USART_CR3_RTSE      8
2090 #define STM_USART_CR3_DMAT      7
2091 #define STM_USART_CR3_DMAR      6
2092 #define STM_USART_CR3_SCEN      5
2093 #define STM_USART_CR3_NACK      4
2094 #define STM_USART_CR3_HDSEL     3
2095 #define STM_USART_CR3_IRLP      2
2096 #define STM_USART_CR3_IREN      1
2097 #define STM_USART_CR3_EIE       0
2098
2099 #define STM_USART_GTPR_GT       8
2100 #define STM_USART_GTPR_PSC      0
2101
2102 #define STM_USART_RQR_TXFRQ     4
2103 #define STM_USART_RQR_RXFRQ     3
2104 #define STM_USART_RQR_MMRQ      2
2105 #define STM_USART_RQR_SBKRQ     1
2106 #define STM_USART_RQR_ABRRQ     0
2107
2108 #define STM_USART_ISR_REACK     22
2109 #define STM_USART_ISR_TEACK     21
2110 #define STM_USART_ISR_WUF       20
2111 #define STM_USART_ISR_RWU       19
2112 #define STM_USART_ISR_SBKF      18
2113 #define STM_USART_ISR_CMF       17
2114 #define STM_USART_ISR_BUSY      16
2115 #define STM_USART_ISR_ABRF      15
2116 #define STM_USART_ISR_ABRE      14
2117 #define STM_USART_ISR_EOBF      12
2118 #define STM_USART_ISR_RTOF      11
2119 #define STM_USART_ISR_CTS       10
2120 #define STM_USART_ISR_CTSIF     9
2121 #define STM_USART_ISR_LBDF      8
2122 #define STM_USART_ISR_TXE       7
2123 #define STM_USART_ISR_TC        6
2124 #define STM_USART_ISR_RXNE      5
2125 #define STM_USART_ISR_IDLE      4
2126 #define STM_USART_ISR_ORE       3
2127 #define STM_USART_ISR_NF        2
2128 #define STM_USART_ISR_FE        1
2129 #define STM_USART_ISR_PE        0
2130
2131 #define STM_USART_ICR_WUCF      20
2132 #define STM_USART_ICR_CMCF      17
2133 #define STM_USART_ICR_EOBCF     12
2134 #define STM_USART_ICR_RTOCF     11
2135 #define STM_USART_ICR_CTSCF     9
2136 #define STM_USART_ICR_LBDCF     8
2137 #define STM_USART_ICR_TCCF      6
2138 #define STM_USART_ICR_IDLECF    4
2139 #define STM_USART_ICR_ORECF     3
2140 #define STM_USART_ICR_NCF       2
2141 #define STM_USART_ICR_FECF      1
2142 #define STM_USART_ICR_PECF      0
2143
2144 extern struct stm_usart stm_usart1;
2145 extern struct stm_usart stm_usart2;
2146
2147 #endif /* _STM32F0_H_ */