2 * Copyright © 2015 Keith Packard <keithp@keithp.com>
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; version 2 of the License.
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
11 * General Public License for more details.
13 * You should have received a copy of the GNU General Public License along
14 * with this program; if not, write to the Free Software Foundation, Inc.,
15 * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
23 typedef volatile uint32_t vuint32_t;
24 typedef volatile void * vvoid_t;
25 typedef volatile uint16_t vuint16_t;
43 #define STM_MODER_SHIFT(pin) ((pin) << 1)
44 #define STM_MODER_MASK 3
45 #define STM_MODER_INPUT 0
46 #define STM_MODER_OUTPUT 1
47 #define STM_MODER_ALTERNATE 2
48 #define STM_MODER_ANALOG 3
51 stm_moder_set(struct stm_gpio *gpio, int pin, vuint32_t value) {
52 gpio->moder = ((gpio->moder &
53 ~(STM_MODER_MASK << STM_MODER_SHIFT(pin))) |
54 value << STM_MODER_SHIFT(pin));
57 static inline uint32_t
58 stm_moder_get(struct stm_gpio *gpio, int pin) {
59 return (gpio->moder >> STM_MODER_SHIFT(pin)) & STM_MODER_MASK;
62 #define STM_OTYPER_SHIFT(pin) (pin)
63 #define STM_OTYPER_MASK 1
64 #define STM_OTYPER_PUSH_PULL 0
65 #define STM_OTYPER_OPEN_DRAIN 1
68 stm_otyper_set(struct stm_gpio *gpio, int pin, vuint32_t value) {
69 gpio->otyper = ((gpio->otyper &
70 ~(STM_OTYPER_MASK << STM_OTYPER_SHIFT(pin))) |
71 value << STM_OTYPER_SHIFT(pin));
74 static inline uint32_t
75 stm_otyper_get(struct stm_gpio *gpio, int pin) {
76 return (gpio->otyper >> STM_OTYPER_SHIFT(pin)) & STM_OTYPER_MASK;
79 #define STM_OSPEEDR_SHIFT(pin) ((pin) << 1)
80 #define STM_OSPEEDR_MASK 3
81 #define STM_OSPEEDR_LOW 0 /* 2MHz */
82 #define STM_OSPEEDR_MEDIUM 1 /* 10MHz */
83 #define STM_OSPEEDR_HIGH 3 /* 10-50MHz */
86 stm_ospeedr_set(struct stm_gpio *gpio, int pin, vuint32_t value) {
87 gpio->ospeedr = ((gpio->ospeedr &
88 ~(STM_OSPEEDR_MASK << STM_OSPEEDR_SHIFT(pin))) |
89 value << STM_OSPEEDR_SHIFT(pin));
92 static inline uint32_t
93 stm_ospeedr_get(struct stm_gpio *gpio, int pin) {
94 return (gpio->ospeedr >> STM_OSPEEDR_SHIFT(pin)) & STM_OSPEEDR_MASK;
97 #define STM_PUPDR_SHIFT(pin) ((pin) << 1)
98 #define STM_PUPDR_MASK 3
99 #define STM_PUPDR_NONE 0
100 #define STM_PUPDR_PULL_UP 1
101 #define STM_PUPDR_PULL_DOWN 2
102 #define STM_PUPDR_RESERVED 3
105 stm_pupdr_set(struct stm_gpio *gpio, int pin, uint32_t value) {
106 gpio->pupdr = ((gpio->pupdr &
107 ~(STM_PUPDR_MASK << STM_PUPDR_SHIFT(pin))) |
108 value << STM_PUPDR_SHIFT(pin));
111 static inline uint32_t
112 stm_pupdr_get(struct stm_gpio *gpio, int pin) {
113 return (gpio->pupdr >> STM_PUPDR_SHIFT(pin)) & STM_PUPDR_MASK;
116 #define STM_AFR_SHIFT(pin) ((pin) << 2)
117 #define STM_AFR_MASK 0xf
118 #define STM_AFR_NONE 0
119 #define STM_AFR_AF0 0x0
120 #define STM_AFR_AF1 0x1
121 #define STM_AFR_AF2 0x2
122 #define STM_AFR_AF3 0x3
123 #define STM_AFR_AF4 0x4
124 #define STM_AFR_AF5 0x5
125 #define STM_AFR_AF6 0x6
126 #define STM_AFR_AF7 0x7
129 stm_afr_set(struct stm_gpio *gpio, int pin, uint32_t value) {
131 * Set alternate pin mode too
133 stm_moder_set(gpio, pin, STM_MODER_ALTERNATE);
135 gpio->afrl = ((gpio->afrl &
136 ~(STM_AFR_MASK << STM_AFR_SHIFT(pin))) |
137 value << STM_AFR_SHIFT(pin));
140 gpio->afrh = ((gpio->afrh &
141 ~(STM_AFR_MASK << STM_AFR_SHIFT(pin))) |
142 value << STM_AFR_SHIFT(pin));
146 static inline uint32_t
147 stm_afr_get(struct stm_gpio *gpio, int pin) {
149 return (gpio->afrl >> STM_AFR_SHIFT(pin)) & STM_AFR_MASK;
152 return (gpio->afrh >> STM_AFR_SHIFT(pin)) & STM_AFR_MASK;
157 stm_gpio_set(struct stm_gpio *gpio, int pin, uint8_t value) {
158 /* Use the bit set/reset register to do this atomically */
159 gpio->bsrr = ((uint32_t) (value ^ 1) << (pin + 16)) | ((uint32_t) value << pin);
162 static inline uint8_t
163 stm_gpio_get(struct stm_gpio *gpio, int pin) {
164 return (gpio->idr >> pin) & 1;
167 static inline uint16_t
168 stm_gpio_get_all(struct stm_gpio *gpio) {
173 * We can't define these in registers.ld or our fancy
174 * ao_enable_gpio macro will expand into a huge pile of code
175 * as the compiler won't do correct constant folding and
176 * dead-code elimination
179 extern struct stm_gpio stm_gpioa;
180 extern struct stm_gpio stm_gpiob;
181 extern struct stm_gpio stm_gpioc;
182 extern struct stm_gpio stm_gpiof;
184 #define stm_gpiof (*((struct stm_gpio *) 0x48001400))
185 #define stm_gpioc (*((struct stm_gpio *) 0x48000800))
186 #define stm_gpiob (*((struct stm_gpio *) 0x48000400))
187 #define stm_gpioa (*((struct stm_gpio *) 0x48000000))
190 vuint32_t cr1; /* control register 1 */
191 vuint32_t cr2; /* control register 2 */
192 vuint32_t cr3; /* control register 3 */
193 vuint32_t brr; /* baud rate register */
195 vuint32_t gtpr; /* guard time and prescaler */
196 vuint32_t rtor; /* */
205 extern struct stm_usart stm_usart1;
206 extern struct stm_usart stm_usart2;
208 #define STM_USART_SR_CTS (9) /* CTS flag */
209 #define STM_USART_SR_LBD (8) /* LIN break detection flag */
210 #define STM_USART_SR_TXE (7) /* Transmit data register empty */
211 #define STM_USART_SR_TC (6) /* Transmission complete */
212 #define STM_USART_SR_RXNE (5) /* Read data register not empty */
213 #define STM_USART_SR_IDLE (4) /* IDLE line detected */
214 #define STM_USART_SR_ORE (3) /* Overrun error */
215 #define STM_USART_SR_NF (2) /* Noise detected flag */
216 #define STM_USART_SR_FE (1) /* Framing error */
217 #define STM_USART_SR_PE (0) /* Parity error */
219 #define STM_USART_CR1_OVER8 (15) /* Oversampling mode */
220 #define STM_USART_CR1_UE (13) /* USART enable */
221 #define STM_USART_CR1_M (12) /* Word length */
222 #define STM_USART_CR1_WAKE (11) /* Wakeup method */
223 #define STM_USART_CR1_PCE (10) /* Parity control enable */
224 #define STM_USART_CR1_PS (9) /* Parity selection */
225 #define STM_USART_CR1_PEIE (8) /* PE interrupt enable */
226 #define STM_USART_CR1_TXEIE (7) /* TXE interrupt enable */
227 #define STM_USART_CR1_TCIE (6) /* Transmission complete interrupt enable */
228 #define STM_USART_CR1_RXNEIE (5) /* RXNE interrupt enable */
229 #define STM_USART_CR1_IDLEIE (4) /* IDLE interrupt enable */
230 #define STM_USART_CR1_TE (3) /* Transmitter enable */
231 #define STM_USART_CR1_RE (2) /* Receiver enable */
232 #define STM_USART_CR1_RWU (1) /* Receiver wakeup */
233 #define STM_USART_CR1_SBK (0) /* Send break */
235 #define STM_USART_CR2_LINEN (14) /* LIN mode enable */
236 #define STM_USART_CR2_STOP (12) /* STOP bits */
237 #define STM_USART_CR2_STOP_MASK 3
238 #define STM_USART_CR2_STOP_1 0
239 #define STM_USART_CR2_STOP_0_5 1
240 #define STM_USART_CR2_STOP_2 2
241 #define STM_USART_CR2_STOP_1_5 3
243 #define STM_USART_CR2_CLKEN (11) /* Clock enable */
244 #define STM_USART_CR2_CPOL (10) /* Clock polarity */
245 #define STM_USART_CR2_CPHA (9) /* Clock phase */
246 #define STM_USART_CR2_LBCL (8) /* Last bit clock pulse */
247 #define STM_USART_CR2_LBDIE (6) /* LIN break detection interrupt enable */
248 #define STM_USART_CR2_LBDL (5) /* lin break detection length */
249 #define STM_USART_CR2_ADD (0)
250 #define STM_USART_CR2_ADD_MASK 0xf
252 #define STM_USART_CR3_ONEBITE (11) /* One sample bit method enable */
253 #define STM_USART_CR3_CTSIE (10) /* CTS interrupt enable */
254 #define STM_USART_CR3_CTSE (9) /* CTS enable */
255 #define STM_USART_CR3_RTSE (8) /* RTS enable */
256 #define STM_USART_CR3_DMAT (7) /* DMA enable transmitter */
257 #define STM_USART_CR3_DMAR (6) /* DMA enable receiver */
258 #define STM_USART_CR3_SCEN (5) /* Smartcard mode enable */
259 #define STM_USART_CR3_NACK (4) /* Smartcard NACK enable */
260 #define STM_USART_CR3_HDSEL (3) /* Half-duplex selection */
261 #define STM_USART_CR3_IRLP (2) /* IrDA low-power */
262 #define STM_USART_CR3_IREN (1) /* IrDA mode enable */
263 #define STM_USART_CR3_EIE (0) /* Error interrupt enable */
268 extern struct stm_tim stm_tim9;
294 extern struct stm_tim1011 stm_tim10;
295 extern struct stm_tim1011 stm_tim11;
297 #define STM_TIM1011_CR1_CKD 8
298 #define STM_TIM1011_CR1_CKD_1 0
299 #define STM_TIM1011_CR1_CKD_2 1
300 #define STM_TIM1011_CR1_CKD_4 2
301 #define STM_TIM1011_CR1_CKD_MASK 3
302 #define STM_TIM1011_CR1_ARPE 7
303 #define STM_TIM1011_CR1_URS 2
304 #define STM_TIM1011_CR1_UDIS 1
305 #define STM_TIM1011_CR1_CEN 0
307 #define STM_TIM1011_SMCR_ETP 15
308 #define STM_TIM1011_SMCR_ECE 14
309 #define STM_TIM1011_SMCR_ETPS 12
310 #define STM_TIM1011_SMCR_ETPS_OFF 0
311 #define STM_TIM1011_SMCR_ETPS_2 1
312 #define STM_TIM1011_SMCR_ETPS_4 2
313 #define STM_TIM1011_SMCR_ETPS_8 3
314 #define STM_TIM1011_SMCR_ETPS_MASK 3
315 #define STM_TIM1011_SMCR_ETF 8
316 #define STM_TIM1011_SMCR_ETF_NONE 0
317 #define STM_TIM1011_SMCR_ETF_CK_INT_2 1
318 #define STM_TIM1011_SMCR_ETF_CK_INT_4 2
319 #define STM_TIM1011_SMCR_ETF_CK_INT_8 3
320 #define STM_TIM1011_SMCR_ETF_DTS_2_6 4
321 #define STM_TIM1011_SMCR_ETF_DTS_2_8 5
322 #define STM_TIM1011_SMCR_ETF_DTS_4_6 6
323 #define STM_TIM1011_SMCR_ETF_DTS_4_8 7
324 #define STM_TIM1011_SMCR_ETF_DTS_8_6 8
325 #define STM_TIM1011_SMCR_ETF_DTS_8_8 9
326 #define STM_TIM1011_SMCR_ETF_DTS_16_5 10
327 #define STM_TIM1011_SMCR_ETF_DTS_16_6 11
328 #define STM_TIM1011_SMCR_ETF_DTS_16_8 12
329 #define STM_TIM1011_SMCR_ETF_DTS_32_5 13
330 #define STM_TIM1011_SMCR_ETF_DTS_32_6 14
331 #define STM_TIM1011_SMCR_ETF_DTS_32_8 15
332 #define STM_TIM1011_SMCR_ETF_MASK 15
334 #define STM_TIM1011_DIER_CC1E 1
335 #define STM_TIM1011_DIER_UIE 0
337 #define STM_TIM1011_SR_CC1OF 9
338 #define STM_TIM1011_SR_CC1IF 1
339 #define STM_TIM1011_SR_UIF 0
341 #define STM_TIM1011_EGR_CC1G 1
342 #define STM_TIM1011_EGR_UG 0
344 #define STM_TIM1011_CCMR1_OC1CE 7
345 #define STM_TIM1011_CCMR1_OC1M 4
346 #define STM_TIM1011_CCMR1_OC1M_FROZEN 0
347 #define STM_TIM1011_CCMR1_OC1M_SET_1_ACTIVE_ON_MATCH 1
348 #define STM_TIM1011_CCMR1_OC1M_SET_1_INACTIVE_ON_MATCH 2
349 #define STM_TIM1011_CCMR1_OC1M_TOGGLE 3
350 #define STM_TIM1011_CCMR1_OC1M_FORCE_INACTIVE 4
351 #define STM_TIM1011_CCMR1_OC1M_FORCE_ACTIVE 5
352 #define STM_TIM1011_CCMR1_OC1M_PWM_MODE_1 6
353 #define STM_TIM1011_CCMR1_OC1M_PWM_MODE_2 7
354 #define STM_TIM1011_CCMR1_OC1M_MASK 7
355 #define STM_TIM1011_CCMR1_OC1PE 3
356 #define STM_TIM1011_CCMR1_OC1FE 2
357 #define STM_TIM1011_CCMR1_CC1S 0
358 #define STM_TIM1011_CCMR1_CC1S_OUTPUT 0
359 #define STM_TIM1011_CCMR1_CC1S_INPUT_TI1 1
360 #define STM_TIM1011_CCMR1_CC1S_INPUT_TI2 2
361 #define STM_TIM1011_CCMR1_CC1S_INPUT_TRC 3
362 #define STM_TIM1011_CCMR1_CC1S_MASK 3
364 #define STM_TIM1011_CCMR1_IC1F_NONE 0
365 #define STM_TIM1011_CCMR1_IC1F_CK_INT_2 1
366 #define STM_TIM1011_CCMR1_IC1F_CK_INT_4 2
367 #define STM_TIM1011_CCMR1_IC1F_CK_INT_8 3
368 #define STM_TIM1011_CCMR1_IC1F_DTS_2_6 4
369 #define STM_TIM1011_CCMR1_IC1F_DTS_2_8 5
370 #define STM_TIM1011_CCMR1_IC1F_DTS_4_6 6
371 #define STM_TIM1011_CCMR1_IC1F_DTS_4_8 7
372 #define STM_TIM1011_CCMR1_IC1F_DTS_8_6 8
373 #define STM_TIM1011_CCMR1_IC1F_DTS_8_8 9
374 #define STM_TIM1011_CCMR1_IC1F_DTS_16_5 10
375 #define STM_TIM1011_CCMR1_IC1F_DTS_16_6 11
376 #define STM_TIM1011_CCMR1_IC1F_DTS_16_8 12
377 #define STM_TIM1011_CCMR1_IC1F_DTS_32_5 13
378 #define STM_TIM1011_CCMR1_IC1F_DTS_32_6 14
379 #define STM_TIM1011_CCMR1_IC1F_DTS_32_8 15
380 #define STM_TIM1011_CCMR1_IC1F_MASK 15
381 #define STM_TIM1011_CCMR1_IC1PSC 2
382 #define STM_TIM1011_CCMR1_IC1PSC_1 0
383 #define STM_TIM1011_CCMR1_IC1PSC_2 1
384 #define STM_TIM1011_CCMR1_IC1PSC_4 2
385 #define STM_TIM1011_CCMR1_IC1PSC_8 3
386 #define STM_TIM1011_CCMR1_IC1PSC_MASK 3
387 #define STM_TIM1011_CCMR1_CC1S 0
389 #define STM_TIM1011_CCER_CC1NP 3
390 #define STM_TIM1011_CCER_CC1P 1
391 #define STM_TIM1011_CCER_CC1E 0
393 #define STM_TIM1011_OR_TI1_RMP_RI 3
394 #define STM_TIM1011_ETR_RMP 2
395 #define STM_TIM1011_TI1_RMP 0
396 #define STM_TIM1011_TI1_RMP_GPIO 0
397 #define STM_TIM1011_TI1_RMP_LSI 1
398 #define STM_TIM1011_TI1_RMP_LSE 2
399 #define STM_TIM1011_TI1_RMP_RTC 3
400 #define STM_TIM1011_TI1_RMP_MASK 3
402 /* Flash interface */
412 vuint32_t unused_0x18;
418 extern struct stm_flash stm_flash;
420 #define STM_FLASH_ACR_PRFTBS (5)
421 #define STM_FLASH_ACR_PRFTBE (4)
422 #define STM_FLASH_ACR_LATENCY (0)
423 #define STM_FLASH_ACR_LATENCY_0 0
424 #define STM_FLASH_ACR_LATENCY_1 1
426 #define STM_FLASH_PECR_OBL_LAUNCH 18
427 #define STM_FLASH_PECR_ERRIE 17
428 #define STM_FLASH_PECR_EOPIE 16
429 #define STM_FLASH_PECR_FPRG 10
430 #define STM_FLASH_PECR_ERASE 9
431 #define STM_FLASH_PECR_FTDW 8
432 #define STM_FLASH_PECR_DATA 4
433 #define STM_FLASH_PECR_PROG 3
434 #define STM_FLASH_PECR_OPTLOCK 2
435 #define STM_FLASH_PECR_PRGLOCK 1
436 #define STM_FLASH_PECR_PELOCK 0
438 #define STM_FLASH_SR_EOP 5
439 #define STM_FLASH_SR_WRPRTERR 4
440 #define STM_FLASH_SR_PGERR 2
441 #define STM_FLASH_SR_BSY 0
443 #define STM_FLASH_CR_OBL_LAUNCH 13
444 #define STM_FLASH_CR_EOPIE 12
445 #define STM_FLASH_CR_ERRIE 10
446 #define STM_FLASH_CR_OPTWRE 9
447 #define STM_FLASH_CR_LOCK 7
448 #define STM_FLASH_CR_STRT 6
449 #define STM_FLASH_CR_OPTER 5
450 #define STM_FLASH_CR_OPTPG 4
451 #define STM_FLASH_CR_MER 2
452 #define STM_FLASH_CR_PER 1
453 #define STM_FLASH_CR_PG 0
455 #define STM_FLASH_OBR_DATA1 24
456 #define STM_FLASH_OBR_DATA0 16
457 #define STM_FLASH_OBR_BOOT_SEL 15
458 #define STM_FLASH_OBR_RAM_PARITY_CHECK 14
459 #define STM_FLASH_OBR_VDDA_MONITOR 13
460 #define STM_FLASH_OBR_NBOOT1 12
461 #define STM_FLASH_OBR_NBOOT0 11
462 #define STM_FLASH_OBR_NRST_STDBY 10
463 #define STM_FLASH_OBR_NRST_STOP 9
464 #define STM_FLASH_OBR_WDG_SW 8
465 #define STM_FLASH_OBR_RDPRT 1
466 #define STM_FLASH_OBR_RDPRT_LEVEL0 0
467 #define STM_FLASH_OBR_RDPRT_LEVEL1 1
468 #define STM_FLASH_OBR_RDPRT_LEVEL2 3
469 #define STM_FLASH_OBR_OPTERR 0
471 #define STM_FLASH_KEYR_KEY1 0x45670123
472 #define STM_FLASH_KEYR_KEY2 0xcdef89ab
494 extern struct stm_rcc stm_rcc;
496 /* Nominal high speed internal oscillator frequency is 16MHz */
497 #define STM_HSI_FREQ 16000000
499 #define STM_RCC_CR_PLLRDY (25)
500 #define STM_RCC_CR_PLLON (24)
501 #define STM_RCC_CR_CSSON (19)
502 #define STM_RCC_CR_HSEBYP (18)
503 #define STM_RCC_CR_HSERDY (17)
504 #define STM_RCC_CR_HSEON (16)
505 #define STM_RCC_CR_HSICAL (8)
506 #define STM_RCC_CR_HSITRIM (3)
507 #define STM_RCC_CR_HSIRDY (1)
508 #define STM_RCC_CR_HSION (0)
510 #define STM_RCC_CFGR_PLL_NODIV (31)
511 #define STM_RCC_CFGR_PLL_NODIV_DIV_1 1
512 #define STM_RCC_CFGR_PLL_NODIV_DIV_2 0
514 #define STM_RCC_CFGR_MCOPRE (28)
515 #define STM_RCC_CFGR_MCOPRE_DIV_1 0
516 #define STM_RCC_CFGR_MCOPRE_DIV_2 1
517 #define STM_RCC_CFGR_MCOPRE_DIV_4 2
518 #define STM_RCC_CFGR_MCOPRE_DIV_8 3
519 #define STM_RCC_CFGR_MCOPRE_DIV_16 4
520 #define STM_RCC_CFGR_MCOPRE_DIV_32 5
521 #define STM_RCC_CFGR_MCOPRE_DIV_64 6
522 #define STM_RCC_CFGR_MCOPRE_DIV_128 7
523 #define STM_RCC_CFGR_MCOPRE_DIV_MASK 7
525 #define STM_RCC_CFGR_MCO (24)
526 # define STM_RCC_CFGR_MCO_DISABLE 0
528 #define STM_RCC_CFGR_PLLMUL (18)
529 #define STM_RCC_CFGR_PLLMUL_2 0
530 #define STM_RCC_CFGR_PLLMUL_3 1
531 #define STM_RCC_CFGR_PLLMUL_4 2
532 #define STM_RCC_CFGR_PLLMUL_5 3
533 #define STM_RCC_CFGR_PLLMUL_6 4
534 #define STM_RCC_CFGR_PLLMUL_7 5
535 #define STM_RCC_CFGR_PLLMUL_8 6
536 #define STM_RCC_CFGR_PLLMUL_9 7
537 #define STM_RCC_CFGR_PLLMUL_10 8
538 #define STM_RCC_CFGR_PLLMUL_11 9
539 #define STM_RCC_CFGR_PLLMUL_12 10
540 #define STM_RCC_CFGR_PLLMUL_13 11
541 #define STM_RCC_CFGR_PLLMUL_14 12
542 #define STM_RCC_CFGR_PLLMUL_15 13
543 #define STM_RCC_CFGR_PLLMUL_16 14
544 #define STM_RCC_CFGR_PLLMUL_MASK 0xf
546 #define STM_RCC_CFGR_PLLXTPRE (17)
548 #define STM_RCC_CFGR_PLLSRC (15)
549 # define STM_RCC_CFGR_PLLSRC_HSI_DIV_2 0
550 # define STM_RCC_CFGR_PLLSRC_HSI 1
551 # define STM_RCC_CFGR_PLLSRC_HSE 2
552 # define STM_RCC_CFGR_PLLSRC_HSI48 3
554 #define STM_RCC_CFGR_ADCPRE (14)
556 #define STM_RCC_CFGR_PPRE (8)
557 #define STM_RCC_CFGR_PPRE_DIV_1 0
558 #define STM_RCC_CFGR_PPRE_DIV_2 4
559 #define STM_RCC_CFGR_PPRE_DIV_4 5
560 #define STM_RCC_CFGR_PPRE_DIV_8 6
561 #define STM_RCC_CFGR_PPRE_DIV_16 7
562 #define STM_RCC_CFGR_PPRE_MASK 7
564 #define STM_RCC_CFGR_HPRE (4)
565 #define STM_RCC_CFGR_HPRE_DIV_1 0
566 #define STM_RCC_CFGR_HPRE_DIV_2 8
567 #define STM_RCC_CFGR_HPRE_DIV_4 9
568 #define STM_RCC_CFGR_HPRE_DIV_8 0xa
569 #define STM_RCC_CFGR_HPRE_DIV_16 0xb
570 #define STM_RCC_CFGR_HPRE_DIV_64 0xc
571 #define STM_RCC_CFGR_HPRE_DIV_128 0xd
572 #define STM_RCC_CFGR_HPRE_DIV_256 0xe
573 #define STM_RCC_CFGR_HPRE_DIV_512 0xf
574 #define STM_RCC_CFGR_HPRE_MASK 0xf
576 #define STM_RCC_CFGR_SWS (2)
577 #define STM_RCC_CFGR_SWS_HSI 0
578 #define STM_RCC_CFGR_SWS_HSE 1
579 #define STM_RCC_CFGR_SWS_PLL 2
580 #define STM_RCC_CFGR_SWS_HSI48 3
581 #define STM_RCC_CFGR_SWS_MASK 3
583 #define STM_RCC_CFGR_SW (0)
584 #define STM_RCC_CFGR_SW_HSI 0
585 #define STM_RCC_CFGR_SW_HSE 1
586 #define STM_RCC_CFGR_SW_PLL 2
587 #define STM_RCC_CFGR_SW_HSI48 3
588 #define STM_RCC_CFGR_SW_MASK 3
590 #define STM_RCC_APB2RSTR_DBGMCURST 22
591 #define STM_RCC_APB2RSTR_TIM17RST 18
592 #define STM_RCC_APB2RSTR_TIM16RST 17
593 #define STM_RCC_APB2RSTR_TIM15RST 16
594 #define STM_RCC_APB2RSTR_USART1RST 14
595 #define STM_RCC_APB2RSTR_SPI1RST 12
596 #define STM_RCC_APB2RSTR_TIM1RST 11
597 #define STM_RCC_APB2RSTR_ADCRST 9
598 #define STM_RCC_APB2RSTR_USART8RST 7
599 #define STM_RCC_APB2RSTR_USART7RST 6
600 #define STM_RCC_APB2RSTR_USART6RST 5
601 #define STM_RCC_APB2RSTR_SYSCFGRST 1
603 #define STM_RCC_APB1RSTR_CECRST 30
604 #define STM_RCC_APB1RSTR_DACRST 29
605 #define STM_RCC_APB1RSTR_PWRRST 28
606 #define STM_RCC_APB1RSTR_CRSRST 27
607 #define STM_RCC_APB1RSTR_CANRST 25
608 #define STM_RCC_APB1RSTR_USBRST 23
609 #define STM_RCC_APB1RSTR_I2C2RST 22
610 #define STM_RCC_APB1RSTR_I1C1RST 21
611 #define STM_RCC_APB1RSTR_USART5RST 20
612 #define STM_RCC_APB1RSTR_USART4RST 19
613 #define STM_RCC_APB1RSTR_USART3RST 18
614 #define STM_RCC_APB1RSTR_USART2RST 17
615 #define STM_RCC_APB1RSTR_SPI2RST 14
616 #define STM_RCC_APB1RSTR_WWDGRST 11
617 #define STM_RCC_APB1RSTR_TIM14RST 8
618 #define STM_RCC_APB1RSTR_TIM7RST 5
619 #define STM_RCC_APB1RSTR_TIM6RST 4
620 #define STM_RCC_APB1RSTR_TIM3RST 1
621 #define STM_RCC_APB1RSTR_TIM2RST 0
623 #define STM_RCC_AHBENR_TSCEN 24
624 #define STM_RCC_AHBENR_IOPFEN 22
625 #define STM_RCC_AHBENR_IOPEEN 21
626 #define STM_RCC_AHBENR_IOPDEN 20
627 #define STM_RCC_AHBENR_IOPCEN 19
628 #define STM_RCC_AHBENR_IOPBEN 18
629 #define STM_RCC_AHBENR_IOPAEN 17
630 #define STM_RCC_AHBENR_CRCEN 6
631 #define STM_RCC_AHBENR_FLITFEN 4
632 #define STM_RCC_AHBENR_SRAMEN 2
633 #define STM_RCC_AHBENR_DMA2EN 1
634 #define STM_RCC_AHBENR_DMAEN 0
636 #define STM_RCC_APB2ENR_DBGMCUEN 22
637 #define STM_RCC_APB2ENR_TIM17EN 18
638 #define STM_RCC_APB2ENR_TIM16EN 17
639 #define STM_RCC_APB2ENR_TIM15EN 16
640 #define STM_RCC_APB2ENR_USART1EN 14
641 #define STM_RCC_APB2ENR_SPI1EN 12
642 #define STM_RCC_APB2ENR_TIM1EN 11
643 #define STM_RCC_APB2ENR_ADCEN 9
644 #define STM_RCC_APB2ENR_USART8EN 7
645 #define STM_RCC_APB2ENR_USART7EN 6
646 #define STM_RCC_APB2ENR_USART6EN 5
647 #define STM_RCC_APB2ENR_SYSCFGCOMPEN 0
649 #define STM_RCC_APB1ENR_CECEN 30
650 #define STM_RCC_APB1ENR_DACEN 29
651 #define STM_RCC_APB1ENR_PWREN 28
652 #define STM_RCC_APB1ENR_CRSEN 27
653 #define STM_RCC_APB1ENR_CANEN 25
654 #define STM_RCC_APB1ENR_USBEN 23
655 #define STM_RCC_APB1ENR_I2C2EN 22
656 #define STM_RCC_APB1ENR_IC21EN 21
657 #define STM_RCC_APB1ENR_USART5EN 20
658 #define STM_RCC_APB1ENR_USART4EN 19
659 #define STM_RCC_APB1ENR_USART3EN 18
660 #define STM_RCC_APB1ENR_USART2EN 17
661 #define STM_RCC_APB1ENR_SPI2EN 14
662 #define STM_RCC_APB1ENR_WWDGEN 11
663 #define STM_RCC_APB1ENR_TIM14EN 8
664 #define STM_RCC_APB1ENR_TIM7EN 5
665 #define STM_RCC_APB1ENR_TIM6EN 4
666 #define STM_RCC_APB1ENR_TIM3EN 1
667 #define STM_RCC_APB1ENR_TIM2EN 0
669 #define STM_RCC_CSR_LPWRRSTF (31)
670 #define STM_RCC_CSR_WWDGRSTF (30)
671 #define STM_RCC_CSR_IWDGRSTF (29)
672 #define STM_RCC_CSR_SFTRSTF (28)
673 #define STM_RCC_CSR_PORRSTF (27)
674 #define STM_RCC_CSR_PINRSTF (26)
675 #define STM_RCC_CSR_OBLRSTF (25)
676 #define STM_RCC_CSR_RMVF (24)
677 #define STM_RCC_CSR_V18PWRRSTF (23)
678 #define STM_RCC_CSR_LSIRDY (1)
679 #define STM_RCC_CSR_LSION (0)
681 #define STM_RCC_CR2_HSI48CAL 24
682 #define STM_RCC_CR2_HSI48RDY 17
683 #define STM_RCC_CR2_HSI48ON 16
684 #define STM_RCC_CR2_HSI14CAL 8
685 #define STM_RCC_CR2_HSI14TRIM 3
686 #define STM_RCC_CR2_HSI14DIS 2
687 #define STM_RCC_CR2_HSI14RDY 1
688 #define STM_RCC_CR2_HSI14ON 0
690 #define STM_RCC_CFGR3_USART3SW 18
691 #define STM_RCC_CFGR3_USART2SW 16
692 #define STM_RCC_CFGR3_ADCSW 8
693 #define STM_RCC_CFGR3_USBSW 7
694 #define STM_RCC_CFGR3_CECSW 6
695 #define STM_RCC_CFGR3_I2C1SW 4
696 #define STM_RCC_CFGR3_USART1SW 0
705 extern struct stm_crs stm_crs;
707 #define STM_CRS_CR_TRIM 8
708 #define STM_CRS_CR_SWSYNC 7
709 #define STM_CRS_CR_AUTOTRIMEN 6
710 #define STM_CRS_CR_CEN 5
711 #define STM_CRS_CR_ESYNCIE 3
712 #define STM_CRS_CR_ERRIE 2
713 #define STM_CRS_CR_SYNCWARNIE 1
714 #define STM_CRS_CR_SYNCOKIE 0
716 #define STM_CRS_CFGR_SYNCPOL 31
717 #define STM_CRS_CFGR_SYNCSRC 28
718 #define STM_CRS_CFGR_SYNCSRC_GPIO 0
719 #define STM_CRS_CFGR_SYNCSRC_LSE 1
720 #define STM_CRS_CFGR_SYNCSRC_USB 2
721 #define STM_CRS_CFGR_SYNCDIV 24
722 #define STM_CRS_CFGR_SYNCDIV_1 0
723 #define STM_CRS_CFGR_SYNCDIV_2 1
724 #define STM_CRS_CFGR_SYNCDIV_4 2
725 #define STM_CRS_CFGR_SYNCDIV_8 3
726 #define STM_CRS_CFGR_SYNCDIV_16 4
727 #define STM_CRS_CFGR_SYNCDIV_32 5
728 #define STM_CRS_CFGR_SYNCDIV_64 6
729 #define STM_CRS_CFGR_SYNCDIV_128 7
730 #define STM_CRS_CFGR_FELIM 16
731 #define STM_CRS_CFGR_RELOAD 0
733 #define STM_CRS_ISR_FECAP 16
734 #define STM_CRS_ISR_FEDIR 15
735 #define STM_CRS_ISR_TRIMOVF 10
736 #define STM_CRS_ISR_SYNCMISS 9
737 #define STM_CRS_ISR_SYNCERR 8
738 #define STM_CRS_ISR_ESYNCF 3
739 #define STM_CRS_ISR_ERRF 2
740 #define STM_CRS_ISR_SYNCWARNF 1
741 #define STM_CRS_ISR_SYNCOKF 0
743 #define STM_CRS_ICR_ESYNCC 3
744 #define STM_CRS_ICR_ERRC 2
745 #define STM_CRS_ICR_SYNCWARNC 1
746 #define STM_CRS_ICR_SYNCOKC 0
753 extern struct stm_pwr stm_pwr;
755 #define STM_PWR_CR_DBP (8)
757 #define STM_PWR_CR_PLS (5)
758 #define STM_PWR_CR_PLS_2_0 0
759 #define STM_PWR_CR_PLS_2_1 1
760 #define STM_PWR_CR_PLS_2_2 2
761 #define STM_PWR_CR_PLS_2_3 3
762 #define STM_PWR_CR_PLS_2_4 4
763 #define STM_PWR_CR_PLS_2_5 5
764 #define STM_PWR_CR_PLS_2_6 6
765 #define STM_PWR_CR_PLS_EXT 7
766 #define STM_PWR_CR_PLS_MASK 7
768 #define STM_PWR_CR_PVDE (4)
769 #define STM_PWR_CR_CSBF (3)
770 #define STM_PWR_CR_CWUF (2)
771 #define STM_PWR_CR_PDDS (1)
772 #define STM_PWR_CR_LPSDSR (0)
774 #define STM_PWR_CSR_EWUP3 (10)
775 #define STM_PWR_CSR_EWUP2 (9)
776 #define STM_PWR_CSR_EWUP1 (8)
777 #define STM_PWR_CSR_REGLPF (5)
778 #define STM_PWR_CSR_VOSF (4)
779 #define STM_PWR_CSR_VREFINTRDYF (3)
780 #define STM_PWR_CSR_PVDO (2)
781 #define STM_PWR_CSR_SBF (1)
782 #define STM_PWR_CSR_WUF (0)
801 extern struct stm_tim67 stm_tim6;
803 #define STM_TIM67_CR1_ARPE (7)
804 #define STM_TIM67_CR1_OPM (3)
805 #define STM_TIM67_CR1_URS (2)
806 #define STM_TIM67_CR1_UDIS (1)
807 #define STM_TIM67_CR1_CEN (0)
809 #define STM_TIM67_CR2_MMS (4)
810 #define STM_TIM67_CR2_MMS_RESET 0
811 #define STM_TIM67_CR2_MMS_ENABLE 1
812 #define STM_TIM67_CR2_MMS_UPDATE 2
813 #define STM_TIM67_CR2_MMS_MASK 7
815 #define STM_TIM67_DIER_UDE (8)
816 #define STM_TIM67_DIER_UIE (0)
818 #define STM_TIM67_SR_UIF (0)
820 #define STM_TIM67_EGR_UG (0)
827 uint32_t unused_0x10;
831 extern struct stm_lcd stm_lcd;
833 #define STM_LCD_CR_MUX_SEG (7)
835 #define STM_LCD_CR_BIAS (5)
836 #define STM_LCD_CR_BIAS_1_4 0
837 #define STM_LCD_CR_BIAS_1_2 1
838 #define STM_LCD_CR_BIAS_1_3 2
839 #define STM_LCD_CR_BIAS_MASK 3
841 #define STM_LCD_CR_DUTY (2)
842 #define STM_LCD_CR_DUTY_STATIC 0
843 #define STM_LCD_CR_DUTY_1_2 1
844 #define STM_LCD_CR_DUTY_1_3 2
845 #define STM_LCD_CR_DUTY_1_4 3
846 #define STM_LCD_CR_DUTY_1_8 4
847 #define STM_LCD_CR_DUTY_MASK 7
849 #define STM_LCD_CR_VSEL (1)
850 #define STM_LCD_CR_LCDEN (0)
852 #define STM_LCD_FCR_PS (22)
853 #define STM_LCD_FCR_PS_1 0x0
854 #define STM_LCD_FCR_PS_2 0x1
855 #define STM_LCD_FCR_PS_4 0x2
856 #define STM_LCD_FCR_PS_8 0x3
857 #define STM_LCD_FCR_PS_16 0x4
858 #define STM_LCD_FCR_PS_32 0x5
859 #define STM_LCD_FCR_PS_64 0x6
860 #define STM_LCD_FCR_PS_128 0x7
861 #define STM_LCD_FCR_PS_256 0x8
862 #define STM_LCD_FCR_PS_512 0x9
863 #define STM_LCD_FCR_PS_1024 0xa
864 #define STM_LCD_FCR_PS_2048 0xb
865 #define STM_LCD_FCR_PS_4096 0xc
866 #define STM_LCD_FCR_PS_8192 0xd
867 #define STM_LCD_FCR_PS_16384 0xe
868 #define STM_LCD_FCR_PS_32768 0xf
869 #define STM_LCD_FCR_PS_MASK 0xf
871 #define STM_LCD_FCR_DIV (18)
872 #define STM_LCD_FCR_DIV_16 0x0
873 #define STM_LCD_FCR_DIV_17 0x1
874 #define STM_LCD_FCR_DIV_18 0x2
875 #define STM_LCD_FCR_DIV_19 0x3
876 #define STM_LCD_FCR_DIV_20 0x4
877 #define STM_LCD_FCR_DIV_21 0x5
878 #define STM_LCD_FCR_DIV_22 0x6
879 #define STM_LCD_FCR_DIV_23 0x7
880 #define STM_LCD_FCR_DIV_24 0x8
881 #define STM_LCD_FCR_DIV_25 0x9
882 #define STM_LCD_FCR_DIV_26 0xa
883 #define STM_LCD_FCR_DIV_27 0xb
884 #define STM_LCD_FCR_DIV_28 0xc
885 #define STM_LCD_FCR_DIV_29 0xd
886 #define STM_LCD_FCR_DIV_30 0xe
887 #define STM_LCD_FCR_DIV_31 0xf
888 #define STM_LCD_FCR_DIV_MASK 0xf
890 #define STM_LCD_FCR_BLINK (16)
891 #define STM_LCD_FCR_BLINK_DISABLE 0
892 #define STM_LCD_FCR_BLINK_SEG0_COM0 1
893 #define STM_LCD_FCR_BLINK_SEG0_COMALL 2
894 #define STM_LCD_FCR_BLINK_SEGALL_COMALL 3
895 #define STM_LCD_FCR_BLINK_MASK 3
897 #define STM_LCD_FCR_BLINKF (13)
898 #define STM_LCD_FCR_BLINKF_8 0
899 #define STM_LCD_FCR_BLINKF_16 1
900 #define STM_LCD_FCR_BLINKF_32 2
901 #define STM_LCD_FCR_BLINKF_64 3
902 #define STM_LCD_FCR_BLINKF_128 4
903 #define STM_LCD_FCR_BLINKF_256 5
904 #define STM_LCD_FCR_BLINKF_512 6
905 #define STM_LCD_FCR_BLINKF_1024 7
906 #define STM_LCD_FCR_BLINKF_MASK 7
908 #define STM_LCD_FCR_CC (10)
909 #define STM_LCD_FCR_CC_MASK 7
911 #define STM_LCD_FCR_DEAD (7)
912 #define STM_LCD_FCR_DEAD_MASK 7
914 #define STM_LCD_FCR_PON (4)
915 #define STM_LCD_FCR_PON_MASK 7
917 #define STM_LCD_FCR_UDDIE (3)
918 #define STM_LCD_FCR_SOFIE (1)
919 #define STM_LCD_FCR_HD (0)
921 #define STM_LCD_SR_FCRSF (5)
922 #define STM_LCD_SR_RDY (4)
923 #define STM_LCD_SR_UDD (3)
924 #define STM_LCD_SR_UDR (2)
925 #define STM_LCD_SR_SOF (1)
926 #define STM_LCD_SR_ENS (0)
928 #define STM_LCD_CLR_UDDC (3)
929 #define STM_LCD_CLR_SOFC (1)
931 /* The SYSTICK starts at 0xe000e010 */
940 extern struct stm_systick stm_systick;
942 #define STM_SYSTICK_CSR_ENABLE 0
943 #define STM_SYSTICK_CSR_TICKINT 1
944 #define STM_SYSTICK_CSR_CLKSOURCE 2
945 #define STM_SYSTICK_CSR_CLKSOURCE_EXTERNAL 0
946 #define STM_SYSTICK_CSR_CLKSOURCE_HCLK_8 1
947 #define STM_SYSTICK_CSR_COUNTFLAG 16
949 /* The NVIC starts at 0xe000e100, so add that to the offsets to find the absolute address */
952 vuint32_t iser; /* 0x000 0xe000e100 Set Enable Register */
954 uint8_t _unused020[0x080 - 0x004];
956 vuint32_t icer; /* 0x080 0xe000e180 Clear Enable Register */
958 uint8_t _unused0a0[0x100 - 0x084];
960 vuint32_t ispr; /* 0x100 0xe000e200 Set Pending Register */
962 uint8_t _unused120[0x180 - 0x104];
964 vuint32_t icpr; /* 0x180 0xe000e280 Clear Pending Register */
966 uint8_t _unused1a0[0x300 - 0x184];
968 vuint32_t ipr[8]; /* 0x300 0xe000e400 Priority Register */
971 extern struct stm_nvic stm_nvic;
973 #define IRQ_MASK(irq) (1 << (irq))
974 #define IRQ_BOOL(v,irq) (((v) >> (irq)) & 1)
977 stm_nvic_set_enable(int irq) {
978 stm_nvic.iser = IRQ_MASK(irq);
982 stm_nvic_clear_enable(int irq) {
983 stm_nvic.icer = IRQ_MASK(irq);
987 stm_nvic_enabled(int irq) {
988 return IRQ_BOOL(stm_nvic.iser, irq);
992 stm_nvic_set_pending(int irq) {
993 stm_nvic.ispr = IRQ_MASK(irq);
997 stm_nvic_clear_pending(int irq) {
998 stm_nvic.icpr = IRQ_MASK(irq);
1002 stm_nvic_pending(int irq) {
1003 return IRQ_BOOL(stm_nvic.ispr, irq);
1006 #define IRQ_PRIO_REG(irq) ((irq) >> 2)
1007 #define IRQ_PRIO_BIT(irq) (((irq) & 3) << 3)
1008 #define IRQ_PRIO_MASK(irq) (0xff << IRQ_PRIO_BIT(irq))
1011 stm_nvic_set_priority(int irq, uint8_t prio) {
1012 int n = IRQ_PRIO_REG(irq);
1015 v = stm_nvic.ipr[n];
1016 v &= ~IRQ_PRIO_MASK(irq);
1017 v |= (prio) << IRQ_PRIO_BIT(irq);
1018 stm_nvic.ipr[n] = v;
1021 static inline uint8_t
1022 stm_nvic_get_priority(int irq) {
1023 return (stm_nvic.ipr[IRQ_PRIO_REG(irq)] >> IRQ_PRIO_BIT(irq)) & IRQ_PRIO_MASK(0);
1047 extern struct stm_scb stm_scb;
1049 #define STM_SCB_AIRCR_VECTKEY 16
1050 #define STM_SCB_AIRCR_VECTKEY_KEY 0x05fa
1051 #define STM_SCB_AIRCR_PRIGROUP 8
1052 #define STM_SCB_AIRCR_SYSRESETREQ 2
1053 #define STM_SCB_AIRCR_VECTCLRACTIVE 1
1054 #define STM_SCB_AIRCR_VECTRESET 0
1071 extern struct stm_mpu stm_mpu;
1073 #define STM_MPU_TYPER_IREGION 16
1074 #define STM_MPU_TYPER_IREGION_MASK 0xff
1075 #define STM_MPU_TYPER_DREGION 8
1076 #define STM_MPU_TYPER_DREGION_MASK 0xff
1077 #define STM_MPU_TYPER_SEPARATE 0
1079 #define STM_MPU_CR_PRIVDEFENA 2
1080 #define STM_MPU_CR_HFNMIENA 1
1081 #define STM_MPU_CR_ENABLE 0
1083 #define STM_MPU_RNR_REGION 0
1084 #define STM_MPU_RNR_REGION_MASK 0xff
1086 #define STM_MPU_RBAR_ADDR 5
1087 #define STM_MPU_RBAR_ADDR_MASK 0x7ffffff
1089 #define STM_MPU_RBAR_VALID 4
1090 #define STM_MPU_RBAR_REGION 0
1091 #define STM_MPU_RBAR_REGION_MASK 0xf
1093 #define STM_MPU_RASR_XN 28
1094 #define STM_MPU_RASR_AP 24
1095 #define STM_MPU_RASR_AP_NONE_NONE 0
1096 #define STM_MPU_RASR_AP_RW_NONE 1
1097 #define STM_MPU_RASR_AP_RW_RO 2
1098 #define STM_MPU_RASR_AP_RW_RW 3
1099 #define STM_MPU_RASR_AP_RO_NONE 5
1100 #define STM_MPU_RASR_AP_RO_RO 6
1101 #define STM_MPU_RASR_AP_MASK 7
1102 #define STM_MPU_RASR_TEX 19
1103 #define STM_MPU_RASR_TEX_MASK 7
1104 #define STM_MPU_RASR_S 18
1105 #define STM_MPU_RASR_C 17
1106 #define STM_MPU_RASR_B 16
1107 #define STM_MPU_RASR_SRD 8
1108 #define STM_MPU_RASR_SRD_MASK 0xff
1109 #define STM_MPU_RASR_SIZE 1
1110 #define STM_MPU_RASR_SIZE_MASK 0x1f
1111 #define STM_MPU_RASR_ENABLE 0
1113 #define isr(name) void stm_ ## name ## _isr(void);
1172 #define STM_ISR_WWDG_POS 0
1173 #define STM_ISR_PVD_VDDIO2_POS 1
1174 #define STM_ISR_RTC_POS 2
1175 #define STM_ISR_FLASH_POS 3
1176 #define STM_ISR_RCC_CRS_POS 4
1177 #define STM_ISR_EXTI0_1_POS 5
1178 #define STM_ISR_EXTI2_3_POS 6
1179 #define STM_ISR_EXTI4_15_POS 7
1180 #define STM_ISR_TSC_POS 8
1181 #define STM_ISR_DMA_CH1_POS 9
1182 #define STM_ISR_DMA_CH2_3_DMA2_CH1_2_POS 10
1183 #define STM_ISR_DMA_CH44_5_6_7_DMA2_CH3_4_5_POS 11
1184 #define STM_ISR_ADC_COMP_POS 12
1185 #define STM_ISR_TIM1_BRK_UP_TRG_COM_POS 13
1186 #define STM_ISR_TIM1_CC_POS 14
1187 #define STM_ISR_TIM2_POS 15
1188 #define STM_ISR_TIM3_POS 16
1189 #define STM_ISR_TIM6_DAC_POS 17
1190 #define STM_ISR_TIM7_POS 18
1191 #define STM_ISR_TIM14_POS 19
1192 #define STM_ISR_TIM15_POS 20
1193 #define STM_ISR_TIM16_POS 21
1194 #define STM_ISR_TIM17_POS 22
1195 #define STM_ISR_I2C1_POS 23
1196 #define STM_ISR_I2C2_POS 24
1197 #define STM_ISR_SPI1_POS 25
1198 #define STM_ISR_SPI2_POS 26
1199 #define STM_ISR_USART1_POS 27
1200 #define STM_ISR_USART2_POS 28
1201 #define STM_ISR_UASART3_4_5_6_7_8_POS 29
1202 #define STM_ISR_CEC_CAN_POS 30
1203 #define STM_ISR_USB_POS 31
1207 vuint32_t exticr[4];
1211 extern struct stm_syscfg stm_syscfg;
1213 #define STM_SYSCFG_CFGR1_TIM3_DMA_RMP 30
1214 #define STM_SYSCFG_CFGR1_TIM2_DMA_RMP 29
1215 #define STM_SYSCFG_CFGR1_TIM1_DMA_RMP 28
1216 #define STM_SYSCFG_CFGR1_I2C1_DMA_RMP 27
1217 #define STM_SYSCFG_CFGR1_USART3_DMA_RMP 26
1218 #define STM_SYSCFG_CFGR1_USART2_DMA_RMP 25
1219 #define STM_SYSCFG_CFGR1_SPI2_DMA_RMP 24
1220 #define STM_SYSCFG_CFGR1_I2C_PA10_FMP 23
1221 #define STM_SYSCFG_CFGR1_I2C_PA9_FMP 22
1222 #define STM_SYSCFG_CFGR1_I2C2_FMP 21
1223 #define STM_SYSCFG_CFGR1_I2C1_FMP 20
1224 #define STM_SYSCFG_CFGR1_I2C_PB9_FMP 19
1225 #define STM_SYSCFG_CFGR1_I2C_PB8_FMP 18
1226 #define STM_SYSCFG_CFGR1_I2C_PB7_FMP 17
1227 #define STM_SYSCFG_CFGR1_I2C_PB6_FMP 16
1228 #define STM_SYSCFG_CFGR1_TIM17_DMA_RMP2 14
1229 #define STM_SYSCFG_CFGR1_TIM16_DMA_RMP2 13
1230 #define STM_SYSCFG_CFGR1_TIM17_DMA_RMP 12
1231 #define STM_SYSCFG_CFGR1_TIM16_DMA_RMP 11
1232 #define STM_SYSCFG_CFGR1_USART1_RX_DMA_RMP 10
1233 #define STM_SYSCFG_CFGR1_USART1_TX_DMA_RMP 9
1234 #define STM_SYSCFG_CFGR1_ADC_DMA_RMP 8
1235 #define STM_SYSCFG_CFGR1_IRDA_ENV_SEL 6
1236 #define STM_SYSCFG_CFGR1_IRDA_ENV_SEL_TIMER16 0
1237 #define STM_SYSCFG_CFGR1_IRDA_ENV_SEL_USART1 1
1238 #define STM_SYSCFG_CFGR1_IRDA_ENV_SEL_USART4 2
1239 #define STM_SYSCFG_CFGR1_PA11_PA12_RMP 4
1240 #define STM_SYSCFG_CFGR1_MEM_MODE 0
1241 #define STM_SYSCFG_CFGR1_MEM_MODE_MAIN_FLASH 0
1242 #define STM_SYSCFG_CFGR1_MEM_MODE_SYSTEM_FLASH 1
1243 #define STM_SYSCFG_CFGR1_MEM_MODE_SRAM 3
1244 #define STM_SYSCFG_CFGR1_MEM_MODE_MASK 3
1248 stm_exticr_set(struct stm_gpio *gpio, int pin) {
1249 uint8_t reg = pin >> 2;
1250 uint8_t shift = (pin & 3) << 2;
1254 stm_rcc.apb2enr |= (1 << STM_RCC_APB2ENR_SYSCFGCOMPEN);
1256 if (gpio == &stm_gpioa)
1257 val = STM_SYSCFG_EXTICR_PA;
1258 else if (gpio == &stm_gpiob)
1259 val = STM_SYSCFG_EXTICR_PB;
1260 else if (gpio == &stm_gpioc)
1261 val = STM_SYSCFG_EXTICR_PC;
1262 else if (gpio == &stm_gpiof)
1263 val = STM_SYSCFG_EXTICR_PF;
1265 stm_syscfg.exticr[reg] = (stm_syscfg.exticr[reg] & ~(0xf << shift)) | val << shift;
1270 struct stm_dma_channel {
1278 #define STM_NUM_DMA 6
1283 struct stm_dma_channel channel[STM_NUM_DMA];
1286 extern struct stm_dma stm_dma;
1288 /* DMA channels go from 1 to 6, instead of 0 to 5 (sigh)
1291 #define STM_DMA_INDEX(channel) ((channel) - 1)
1293 #define STM_DMA_ISR(index) ((index) << 2)
1294 #define STM_DMA_ISR_MASK 0xf
1295 #define STM_DMA_ISR_TEIF 3
1296 #define STM_DMA_ISR_HTIF 2
1297 #define STM_DMA_ISR_TCIF 1
1298 #define STM_DMA_ISR_GIF 0
1300 #define STM_DMA_IFCR(index) ((index) << 2)
1301 #define STM_DMA_IFCR_MASK 0xf
1302 #define STM_DMA_IFCR_CTEIF 3
1303 #define STM_DMA_IFCR_CHTIF 2
1304 #define STM_DMA_IFCR_CTCIF 1
1305 #define STM_DMA_IFCR_CGIF 0
1307 #define STM_DMA_CCR_MEM2MEM (14)
1309 #define STM_DMA_CCR_PL (12)
1310 #define STM_DMA_CCR_PL_LOW (0)
1311 #define STM_DMA_CCR_PL_MEDIUM (1)
1312 #define STM_DMA_CCR_PL_HIGH (2)
1313 #define STM_DMA_CCR_PL_VERY_HIGH (3)
1314 #define STM_DMA_CCR_PL_MASK (3)
1316 #define STM_DMA_CCR_MSIZE (10)
1317 #define STM_DMA_CCR_MSIZE_8 (0)
1318 #define STM_DMA_CCR_MSIZE_16 (1)
1319 #define STM_DMA_CCR_MSIZE_32 (2)
1320 #define STM_DMA_CCR_MSIZE_MASK (3)
1322 #define STM_DMA_CCR_PSIZE (8)
1323 #define STM_DMA_CCR_PSIZE_8 (0)
1324 #define STM_DMA_CCR_PSIZE_16 (1)
1325 #define STM_DMA_CCR_PSIZE_32 (2)
1326 #define STM_DMA_CCR_PSIZE_MASK (3)
1328 #define STM_DMA_CCR_MINC (7)
1329 #define STM_DMA_CCR_PINC (6)
1330 #define STM_DMA_CCR_CIRC (5)
1331 #define STM_DMA_CCR_DIR (4)
1332 #define STM_DMA_CCR_DIR_PER_TO_MEM 0
1333 #define STM_DMA_CCR_DIR_MEM_TO_PER 1
1334 #define STM_DMA_CCR_TEIE (3)
1335 #define STM_DMA_CCR_HTIE (2)
1336 #define STM_DMA_CCR_TCIE (1)
1337 #define STM_DMA_CCR_EN (0)
1339 /* DMA channel assignments. When a peripheral has multiple channels
1340 * (indicated with _<number>), then it can be configured to either
1341 * channel using syscfg.cfgr1
1344 #define STM_DMA_CHANNEL_ADC_1 1
1345 #define STM_DMA_CHANNEL_ADC_2 2
1347 #define STM_DMA_CHANNEL_SPI1_RX 2
1348 #define STM_DMA_CHANNEL_SPI1_TX 3
1350 #define STM_DMA_CHANNEL_SPI2_RX 4
1351 #define STM_DMA_CHANNEL_SPI2_TX 5
1353 #define STM_DMA_CHANNEL_USART1_TX_1 2
1354 #define STM_DMA_CHANNEL_USART1_RX_1 3
1355 #define STM_DMA_CHANNEL_USART1_TX_2 4
1356 #define STM_DMA_CHANNEL_USART1_RX_2 5
1358 #define STM_DMA_CHANNEL_USART2_RX 4
1359 #define STM_DMA_CHANNEL_USART2_TX 5
1361 #define STM_DMA_CHANNEL_I2C1_TX 2
1362 #define STM_DMA_CHANNEL_I2C1_RX 3
1364 #define STM_DMA_CHANNEL_I2C2_TX 4
1365 #define STM_DMA_CHANNEL_I2C2_RX 5
1367 #define STM_DMA_CHANNEL_TIM1_CH1 2
1368 #define STM_DMA_CHANNEL_TIM1_CH2 3
1369 #define STM_DMA_CHANNEL_TIM1_CH4 4
1370 #define STM_DMA_CHANNEL_TIM1_TRIG 4
1371 #define STM_DMA_CHANNEL_TIM1_COM 4
1372 #define STM_DMA_CHANNEL_TIM1_CH3 5
1373 #define STM_DMA_CHANNEL_TIM1_UP 5
1375 #define STM_DMA_CHANNEL_TIM2_CH3 1
1376 #define STM_DMA_CHANNEL_TIM2_UP 2
1377 #define STM_DMA_CHANNEL_TIM2_CH2 3
1378 #define STM_DMA_CHANNEL_TIM2_CH4 4
1379 #define STM_DMA_CHANNEL_TIM2_CH1 5
1381 #define STM_DMA_CHANNEL_TIM3_CH3 2
1382 #define STM_DMA_CHANNEL_TIM3_CH4 3
1383 #define STM_DMA_CHANNEL_TIM3_UP 3
1384 #define STM_DMA_CHANNEL_TIM3_CH1 4
1385 #define STM_DMA_CHANNEL_TIM3_TRIG 4
1387 #define STM_DMA_CHANNEL_TIM6_UP_DAC 2
1389 #define STM_DMA_CHANNEL_TIM15_CH1 5
1390 #define STM_DMA_CHANNEL_TIM15_UP 5
1391 #define STM_DMA_CHANNEL_TIM15_TRIG 5
1392 #define STM_DMA_CHANNEL_TIM15_COM 5
1394 #define STM_DMA_CHANNEL_TIM16_CH1_1 3
1395 #define STM_DMA_CHANNEL_TIM16_UP_1 3
1396 #define STM_DMA_CHANNEL_TIM16_CH1_2 4
1397 #define STM_DMA_CHANNEL_TIM16_UP_2 4
1399 #define STM_DMA_CHANNEL_TIM17_CH1_1 1
1400 #define STM_DMA_CHANNEL_TIM17_UP_1 1
1401 #define STM_DMA_CHANNEL_TIM17_CH1_2 2
1402 #define STM_DMA_CHANNEL_TIM17_UP_2 2
1405 * Only spi channel 1 and 2 can use DMA
1407 #define STM_NUM_SPI 2
1419 extern struct stm_spi stm_spi1, stm_spi2, stm_spi3;
1421 /* SPI channels go from 1 to 3, instead of 0 to 2 (sigh)
1424 #define STM_SPI_INDEX(channel) ((channel) - 1)
1426 #define STM_SPI_CR1_BIDIMODE 15
1427 #define STM_SPI_CR1_BIDIOE 14
1428 #define STM_SPI_CR1_CRCEN 13
1429 #define STM_SPI_CR1_CRCNEXT 12
1430 #define STM_SPI_CR1_DFF 11
1431 #define STM_SPI_CR1_RXONLY 10
1432 #define STM_SPI_CR1_SSM 9
1433 #define STM_SPI_CR1_SSI 8
1434 #define STM_SPI_CR1_LSBFIRST 7
1435 #define STM_SPI_CR1_SPE 6
1436 #define STM_SPI_CR1_BR 3
1437 #define STM_SPI_CR1_BR_PCLK_2 0
1438 #define STM_SPI_CR1_BR_PCLK_4 1
1439 #define STM_SPI_CR1_BR_PCLK_8 2
1440 #define STM_SPI_CR1_BR_PCLK_16 3
1441 #define STM_SPI_CR1_BR_PCLK_32 4
1442 #define STM_SPI_CR1_BR_PCLK_64 5
1443 #define STM_SPI_CR1_BR_PCLK_128 6
1444 #define STM_SPI_CR1_BR_PCLK_256 7
1445 #define STM_SPI_CR1_BR_MASK 7
1447 #define STM_SPI_CR1_MSTR 2
1448 #define STM_SPI_CR1_CPOL 1
1449 #define STM_SPI_CR1_CPHA 0
1451 #define STM_SPI_CR2_TXEIE 7
1452 #define STM_SPI_CR2_RXNEIE 6
1453 #define STM_SPI_CR2_ERRIE 5
1454 #define STM_SPI_CR2_SSOE 2
1455 #define STM_SPI_CR2_TXDMAEN 1
1456 #define STM_SPI_CR2_RXDMAEN 0
1458 #define STM_SPI_SR_BSY 7
1459 #define STM_SPI_SR_OVR 6
1460 #define STM_SPI_SR_MODF 5
1461 #define STM_SPI_SR_CRCERR 4
1462 #define STM_SPI_SR_TXE 1
1463 #define STM_SPI_SR_RXNE 0
1485 uint8_t r_44[0x308 - 0x44];
1489 extern struct stm_adc stm_adc;
1491 #define STM_ADC_ISR_AWD 7
1492 #define STM_ADC_ISR_OVR 4
1493 #define STM_ADC_ISR_EOSEQ 3
1494 #define STM_ADC_ISR_EOC 2
1495 #define STM_ADC_ISR_EOSMP 1
1496 #define STM_ADC_ISR_ADRDY 0
1498 #define STM_ADC_IER_AWDIE 7
1499 #define STM_ADC_IER_OVRIE 4
1500 #define STM_ADC_IER_EOSEQIE 3
1501 #define STM_ADC_IER_EOCIE 2
1502 #define STM_ADC_IER_EOSMPIE 1
1503 #define STM_ADC_IER_ADRDYIE 0
1505 #define STM_ADC_CR_ADCAL 31
1506 #define STM_ADC_CR_ADSTP 4
1507 #define STM_ADC_CR_ADSTART 2
1508 #define STM_ADC_CR_ADDIS 1
1509 #define STM_ADC_CR_ADEN 0
1511 #define STM_ADC_CFGR1_AWDCH 26
1512 #define STM_ADC_CFGR1_AWDEN 23
1513 #define STM_ADC_CFGR1_AWDSGL 22
1514 #define STM_ADC_CFGR1_DISCEN 16
1515 #define STM_ADC_CFGR1_AUTOOFF 15
1516 #define STM_ADC_CFGR1_WAIT 14
1517 #define STM_ADC_CFGR1_CONT 13
1518 #define STM_ADC_CFGR1_OVRMOD 12
1519 #define STM_ADC_CFGR1_EXTEN 10
1520 #define STM_ADC_CFGR1_EXTEN_DISABLE 0
1521 #define STM_ADC_CFGR1_EXTEN_RISING 1
1522 #define STM_ADC_CFGR1_EXTEN_FALLING 2
1523 #define STM_ADC_CFGR1_EXTEN_BOTH 3
1524 #define STM_ADC_CFGR1_EXTEN_MASK 3
1526 #define STM_ADC_CFGR1_EXTSEL 6
1527 #define STM_ADC_CFGR1_ALIGN 5
1528 #define STM_ADC_CFGR1_RES 3
1529 #define STM_ADC_CFGR1_RES_12 0
1530 #define STM_ADC_CFGR1_RES_10 1
1531 #define STM_ADC_CFGR1_RES_8 2
1532 #define STM_ADC_CFGR1_RES_6 3
1533 #define STM_ADC_CFGR1_RES_MASK 3
1534 #define STM_ADC_CFGR1_SCANDIR 2
1535 #define STM_ADC_CFGR1_SCANDIR_UP 0
1536 #define STM_ADC_CFGR1_SCANDIR_DOWN 1
1537 #define STM_ADC_CFGR1_DMACFG 1
1538 #define STM_ADC_CFGR1_DMACFG_ONESHOT 0
1539 #define STM_ADC_CFGR1_DMACFG_CIRCULAR 1
1540 #define STM_ADC_CFGR1_DMAEN 0
1542 #define STM_ADC_CFGR2_CKMODE 30
1543 #define STM_ADC_CFGR2_CKMODE_ADCCLK 0
1544 #define STM_ADC_CFGR2_CKMODE_PCLK_2 1
1545 #define STM_ADC_CFGR2_CKMODE_PCLK_4 2
1547 #define STM_ADC_SMPR_SMP 0
1548 #define STM_ADC_SMPR_SMP_1_5 0
1549 #define STM_ADC_SMPR_SMP_7_5 1
1550 #define STM_ADC_SMPR_SMP_13_5 2
1551 #define STM_ADC_SMPR_SMP_28_5 3
1552 #define STM_ADC_SMPR_SMP_41_5 4
1553 #define STM_ADC_SMPR_SMP_55_5 5
1554 #define STM_ADC_SMPR_SMP_71_5 6
1555 #define STM_ADC_SMPR_SMP_239_5 7
1557 #define STM_ADC_TR_HT 16
1558 #define STM_ADC_TR_LT 0
1560 #define STM_ADC_CCR_VBATEN 24
1561 #define STM_ADC_CCR_TSEN 23
1562 #define STM_ADC_CCR_VREFEN 22
1565 uint16_t ts_cal_cold; /* 30°C */
1566 uint16_t vrefint_cal;
1568 uint16_t ts_cal_hot; /* 110°C */
1571 extern struct stm_cal stm_cal;
1573 #define stm_temp_cal_cold 30
1574 #define stm_temp_cal_hot 110
1580 extern struct stm_dbgmcu stm_dbgmcu;
1582 static inline uint16_t
1584 return stm_dbgmcu.idcode & 0xfff;
1587 struct stm_flash_size {
1591 extern struct stm_flash_size stm_flash_size_04x;
1593 /* Returns flash size in bytes */
1595 stm_flash_size(void);
1597 struct stm_device_id {
1603 extern struct stm_device_id stm_device_id;
1605 #define STM_NUM_I2C 2
1607 #define STM_I2C_INDEX(channel) ((channel) - 1)
1621 extern struct stm_i2c stm_i2c1, stm_i2c2;
1623 #define STM_I2C_CR1_SWRST 15
1624 #define STM_I2C_CR1_ALERT 13
1625 #define STM_I2C_CR1_PEC 12
1626 #define STM_I2C_CR1_POS 11
1627 #define STM_I2C_CR1_ACK 10
1628 #define STM_I2C_CR1_STOP 9
1629 #define STM_I2C_CR1_START 8
1630 #define STM_I2C_CR1_NOSTRETCH 7
1631 #define STM_I2C_CR1_ENGC 6
1632 #define STM_I2C_CR1_ENPEC 5
1633 #define STM_I2C_CR1_ENARP 4
1634 #define STM_I2C_CR1_SMBTYPE 3
1635 #define STM_I2C_CR1_SMBUS 1
1636 #define STM_I2C_CR1_PE 0
1638 #define STM_I2C_CR2_LAST 12
1639 #define STM_I2C_CR2_DMAEN 11
1640 #define STM_I2C_CR2_ITBUFEN 10
1641 #define STM_I2C_CR2_ITEVTEN 9
1642 #define STM_I2C_CR2_ITERREN 8
1643 #define STM_I2C_CR2_FREQ 0
1644 #define STM_I2C_CR2_FREQ_2_MHZ 2
1645 #define STM_I2C_CR2_FREQ_4_MHZ 4
1646 #define STM_I2C_CR2_FREQ_8_MHZ 8
1647 #define STM_I2C_CR2_FREQ_16_MHZ 16
1648 #define STM_I2C_CR2_FREQ_32_MHZ 32
1649 #define STM_I2C_CR2_FREQ_MASK 0x3f
1651 #define STM_I2C_SR1_SMBALERT 15
1652 #define STM_I2C_SR1_TIMEOUT 14
1653 #define STM_I2C_SR1_PECERR 12
1654 #define STM_I2C_SR1_OVR 11
1655 #define STM_I2C_SR1_AF 10
1656 #define STM_I2C_SR1_ARLO 9
1657 #define STM_I2C_SR1_BERR 8
1658 #define STM_I2C_SR1_TXE 7
1659 #define STM_I2C_SR1_RXNE 6
1660 #define STM_I2C_SR1_STOPF 4
1661 #define STM_I2C_SR1_ADD10 3
1662 #define STM_I2C_SR1_BTF 2
1663 #define STM_I2C_SR1_ADDR 1
1664 #define STM_I2C_SR1_SB 0
1666 #define STM_I2C_SR2_PEC 8
1667 #define STM_I2C_SR2_PEC_MASK 0xff00
1668 #define STM_I2C_SR2_DUALF 7
1669 #define STM_I2C_SR2_SMBHOST 6
1670 #define STM_I2C_SR2_SMBDEFAULT 5
1671 #define STM_I2C_SR2_GENCALL 4
1672 #define STM_I2C_SR2_TRA 2
1673 #define STM_I2C_SR2_BUSY 1
1674 #define STM_I2C_SR2_MSL 0
1676 #define STM_I2C_CCR_FS 15
1677 #define STM_I2C_CCR_DUTY 14
1678 #define STM_I2C_CCR_CCR 0
1679 #define STM_I2C_CCR_MASK 0x7ff
1697 uint32_t reserved_30;
1703 uint32_t reserved_44;
1707 uint32_t reserved_50;
1710 extern struct stm_tim234 stm_tim2, stm_tim3, stm_tim4;
1712 #define STM_TIM234_CR1_CKD 8
1713 #define STM_TIM234_CR1_CKD_1 0
1714 #define STM_TIM234_CR1_CKD_2 1
1715 #define STM_TIM234_CR1_CKD_4 2
1716 #define STM_TIM234_CR1_CKD_MASK 3
1717 #define STM_TIM234_CR1_ARPE 7
1718 #define STM_TIM234_CR1_CMS 5
1719 #define STM_TIM234_CR1_CMS_EDGE 0
1720 #define STM_TIM234_CR1_CMS_CENTER_1 1
1721 #define STM_TIM234_CR1_CMS_CENTER_2 2
1722 #define STM_TIM234_CR1_CMS_CENTER_3 3
1723 #define STM_TIM234_CR1_CMS_MASK 3
1724 #define STM_TIM234_CR1_DIR 4
1725 #define STM_TIM234_CR1_DIR_UP 0
1726 #define STM_TIM234_CR1_DIR_DOWN 1
1727 #define STM_TIM234_CR1_OPM 3
1728 #define STM_TIM234_CR1_URS 2
1729 #define STM_TIM234_CR1_UDIS 1
1730 #define STM_TIM234_CR1_CEN 0
1732 #define STM_TIM234_CR2_TI1S 7
1733 #define STM_TIM234_CR2_MMS 4
1734 #define STM_TIM234_CR2_MMS_RESET 0
1735 #define STM_TIM234_CR2_MMS_ENABLE 1
1736 #define STM_TIM234_CR2_MMS_UPDATE 2
1737 #define STM_TIM234_CR2_MMS_COMPARE_PULSE 3
1738 #define STM_TIM234_CR2_MMS_COMPARE_OC1REF 4
1739 #define STM_TIM234_CR2_MMS_COMPARE_OC2REF 5
1740 #define STM_TIM234_CR2_MMS_COMPARE_OC3REF 6
1741 #define STM_TIM234_CR2_MMS_COMPARE_OC4REF 7
1742 #define STM_TIM234_CR2_MMS_MASK 7
1743 #define STM_TIM234_CR2_CCDS 3
1745 #define STM_TIM234_SMCR_ETP 15
1746 #define STM_TIM234_SMCR_ECE 14
1747 #define STM_TIM234_SMCR_ETPS 12
1748 #define STM_TIM234_SMCR_ETPS_OFF 0
1749 #define STM_TIM234_SMCR_ETPS_DIV_2 1
1750 #define STM_TIM234_SMCR_ETPS_DIV_4 2
1751 #define STM_TIM234_SMCR_ETPS_DIV_8 3
1752 #define STM_TIM234_SMCR_ETPS_MASK 3
1753 #define STM_TIM234_SMCR_ETF 8
1754 #define STM_TIM234_SMCR_ETF_NONE 0
1755 #define STM_TIM234_SMCR_ETF_INT_N_2 1
1756 #define STM_TIM234_SMCR_ETF_INT_N_4 2
1757 #define STM_TIM234_SMCR_ETF_INT_N_8 3
1758 #define STM_TIM234_SMCR_ETF_DTS_2_N_6 4
1759 #define STM_TIM234_SMCR_ETF_DTS_2_N_8 5
1760 #define STM_TIM234_SMCR_ETF_DTS_4_N_6 6
1761 #define STM_TIM234_SMCR_ETF_DTS_4_N_8 7
1762 #define STM_TIM234_SMCR_ETF_DTS_8_N_6 8
1763 #define STM_TIM234_SMCR_ETF_DTS_8_N_8 9
1764 #define STM_TIM234_SMCR_ETF_DTS_16_N_5 10
1765 #define STM_TIM234_SMCR_ETF_DTS_16_N_6 11
1766 #define STM_TIM234_SMCR_ETF_DTS_16_N_8 12
1767 #define STM_TIM234_SMCR_ETF_DTS_32_N_5 13
1768 #define STM_TIM234_SMCR_ETF_DTS_32_N_6 14
1769 #define STM_TIM234_SMCR_ETF_DTS_32_N_8 15
1770 #define STM_TIM234_SMCR_ETF_MASK 15
1771 #define STM_TIM234_SMCR_MSM 7
1772 #define STM_TIM234_SMCR_TS 4
1773 #define STM_TIM234_SMCR_TS_ITR0 0
1774 #define STM_TIM234_SMCR_TS_ITR1 1
1775 #define STM_TIM234_SMCR_TS_ITR2 2
1776 #define STM_TIM234_SMCR_TS_ITR3 3
1777 #define STM_TIM234_SMCR_TS_TI1F_ED 4
1778 #define STM_TIM234_SMCR_TS_TI1FP1 5
1779 #define STM_TIM234_SMCR_TS_TI2FP2 6
1780 #define STM_TIM234_SMCR_TS_ETRF 7
1781 #define STM_TIM234_SMCR_TS_MASK 7
1782 #define STM_TIM234_SMCR_OCCS 3
1783 #define STM_TIM234_SMCR_SMS 0
1784 #define STM_TIM234_SMCR_SMS_DISABLE 0
1785 #define STM_TIM234_SMCR_SMS_ENCODER_MODE_1 1
1786 #define STM_TIM234_SMCR_SMS_ENCODER_MODE_2 2
1787 #define STM_TIM234_SMCR_SMS_ENCODER_MODE_3 3
1788 #define STM_TIM234_SMCR_SMS_RESET_MODE 4
1789 #define STM_TIM234_SMCR_SMS_GATED_MODE 5
1790 #define STM_TIM234_SMCR_SMS_TRIGGER_MODE 6
1791 #define STM_TIM234_SMCR_SMS_EXTERNAL_CLOCK 7
1792 #define STM_TIM234_SMCR_SMS_MASK 7
1794 #define STM_TIM234_SR_CC4OF 12
1795 #define STM_TIM234_SR_CC3OF 11
1796 #define STM_TIM234_SR_CC2OF 10
1797 #define STM_TIM234_SR_CC1OF 9
1798 #define STM_TIM234_SR_TIF 6
1799 #define STM_TIM234_SR_CC4IF 4
1800 #define STM_TIM234_SR_CC3IF 3
1801 #define STM_TIM234_SR_CC2IF 2
1802 #define STM_TIM234_SR_CC1IF 1
1803 #define STM_TIM234_SR_UIF 0
1805 #define STM_TIM234_EGR_TG 6
1806 #define STM_TIM234_EGR_CC4G 4
1807 #define STM_TIM234_EGR_CC3G 3
1808 #define STM_TIM234_EGR_CC2G 2
1809 #define STM_TIM234_EGR_CC1G 1
1810 #define STM_TIM234_EGR_UG 0
1812 #define STM_TIM234_CCMR1_OC2CE 15
1813 #define STM_TIM234_CCMR1_OC2M 12
1814 #define STM_TIM234_CCMR1_OC2M_FROZEN 0
1815 #define STM_TIM234_CCMR1_OC2M_SET_HIGH_ON_MATCH 1
1816 #define STM_TIM234_CCMR1_OC2M_SET_LOW_ON_MATCH 2
1817 #define STM_TIM234_CCMR1_OC2M_TOGGLE 3
1818 #define STM_TIM234_CCMR1_OC2M_FORCE_LOW 4
1819 #define STM_TIM234_CCMR1_OC2M_FORCE_HIGH 5
1820 #define STM_TIM234_CCMR1_OC2M_PWM_MODE_1 6
1821 #define STM_TIM234_CCMR1_OC2M_PWM_MODE_2 7
1822 #define STM_TIM234_CCMR1_OC2M_MASK 7
1823 #define STM_TIM234_CCMR1_OC2PE 11
1824 #define STM_TIM234_CCMR1_OC2FE 10
1825 #define STM_TIM234_CCMR1_CC2S 8
1826 #define STM_TIM234_CCMR1_CC2S_OUTPUT 0
1827 #define STM_TIM234_CCMR1_CC2S_INPUT_TI2 1
1828 #define STM_TIM234_CCMR1_CC2S_INPUT_TI1 2
1829 #define STM_TIM234_CCMR1_CC2S_INPUT_TRC 3
1830 #define STM_TIM234_CCMR1_CC2S_MASK 3
1832 #define STM_TIM234_CCMR1_OC1CE 7
1833 #define STM_TIM234_CCMR1_OC1M 4
1834 #define STM_TIM234_CCMR1_OC1M_FROZEN 0
1835 #define STM_TIM234_CCMR1_OC1M_SET_HIGH_ON_MATCH 1
1836 #define STM_TIM234_CCMR1_OC1M_SET_LOW_ON_MATCH 2
1837 #define STM_TIM234_CCMR1_OC1M_TOGGLE 3
1838 #define STM_TIM234_CCMR1_OC1M_FORCE_LOW 4
1839 #define STM_TIM234_CCMR1_OC1M_FORCE_HIGH 5
1840 #define STM_TIM234_CCMR1_OC1M_PWM_MODE_1 6
1841 #define STM_TIM234_CCMR1_OC1M_PWM_MODE_2 7
1842 #define STM_TIM234_CCMR1_OC1M_MASK 7
1843 #define STM_TIM234_CCMR1_OC1PE 11
1844 #define STM_TIM234_CCMR1_OC1FE 2
1845 #define STM_TIM234_CCMR1_CC1S 0
1846 #define STM_TIM234_CCMR1_CC1S_OUTPUT 0
1847 #define STM_TIM234_CCMR1_CC1S_INPUT_TI1 1
1848 #define STM_TIM234_CCMR1_CC1S_INPUT_TI2 2
1849 #define STM_TIM234_CCMR1_CC1S_INPUT_TRC 3
1850 #define STM_TIM234_CCMR1_CC1S_MASK 3
1852 #define STM_TIM234_CCMR2_OC4CE 15
1853 #define STM_TIM234_CCMR2_OC4M 12
1854 #define STM_TIM234_CCMR2_OC4M_FROZEN 0
1855 #define STM_TIM234_CCMR2_OC4M_SET_HIGH_ON_MATCH 1
1856 #define STM_TIM234_CCMR2_OC4M_SET_LOW_ON_MATCH 2
1857 #define STM_TIM234_CCMR2_OC4M_TOGGLE 3
1858 #define STM_TIM234_CCMR2_OC4M_FORCE_LOW 4
1859 #define STM_TIM234_CCMR2_OC4M_FORCE_HIGH 5
1860 #define STM_TIM234_CCMR2_OC4M_PWM_MODE_1 6
1861 #define STM_TIM234_CCMR2_OC4M_PWM_MODE_2 7
1862 #define STM_TIM234_CCMR2_OC4M_MASK 7
1863 #define STM_TIM234_CCMR2_OC4PE 11
1864 #define STM_TIM234_CCMR2_OC4FE 10
1865 #define STM_TIM234_CCMR2_CC4S 8
1866 #define STM_TIM234_CCMR2_CC4S_OUTPUT 0
1867 #define STM_TIM234_CCMR2_CC4S_INPUT_TI4 1
1868 #define STM_TIM234_CCMR2_CC4S_INPUT_TI3 2
1869 #define STM_TIM234_CCMR2_CC4S_INPUT_TRC 3
1870 #define STM_TIM234_CCMR2_CC4S_MASK 3
1872 #define STM_TIM234_CCMR2_OC3CE 7
1873 #define STM_TIM234_CCMR2_OC3M 4
1874 #define STM_TIM234_CCMR2_OC3M_FROZEN 0
1875 #define STM_TIM234_CCMR2_OC3M_SET_HIGH_ON_MATCH 1
1876 #define STM_TIM234_CCMR2_OC3M_SET_LOW_ON_MATCH 2
1877 #define STM_TIM234_CCMR2_OC3M_TOGGLE 3
1878 #define STM_TIM234_CCMR2_OC3M_FORCE_LOW 4
1879 #define STM_TIM234_CCMR2_OC3M_FORCE_HIGH 5
1880 #define STM_TIM234_CCMR2_OC3M_PWM_MODE_1 6
1881 #define STM_TIM234_CCMR2_OC3M_PWM_MODE_2 7
1882 #define STM_TIM234_CCMR2_OC3M_MASK 7
1883 #define STM_TIM234_CCMR2_OC3PE 11
1884 #define STM_TIM234_CCMR2_OC3FE 2
1885 #define STM_TIM234_CCMR2_CC3S 0
1886 #define STM_TIM234_CCMR2_CC3S_OUTPUT 0
1887 #define STM_TIM234_CCMR2_CC3S_INPUT_TI3 1
1888 #define STM_TIM234_CCMR2_CC3S_INPUT_TI4 2
1889 #define STM_TIM234_CCMR2_CC3S_INPUT_TRC 3
1890 #define STM_TIM234_CCMR2_CC3S_MASK 3
1892 #define STM_TIM234_CCER_CC4NP 15
1893 #define STM_TIM234_CCER_CC4P 13
1894 #define STM_TIM234_CCER_CC4E 12
1895 #define STM_TIM234_CCER_CC3NP 11
1896 #define STM_TIM234_CCER_CC3P 9
1897 #define STM_TIM234_CCER_CC3E 8
1898 #define STM_TIM234_CCER_CC2NP 7
1899 #define STM_TIM234_CCER_CC2P 5
1900 #define STM_TIM234_CCER_CC2E 4
1901 #define STM_TIM234_CCER_CC1NP 3
1902 #define STM_TIM234_CCER_CC1P 1
1903 #define STM_TIM234_CCER_CC1E 0
1910 uint8_t reserved_20[0x40 - 0x20];
1912 uint16_t reserved_42;
1914 uint16_t reserved_46;
1916 uint16_t reserved_4a;
1918 uint16_t reserved_4e;
1920 uint16_t reserved_52;
1922 uint16_t reserved_56;
1924 uint16_t reserved_5a;
1927 extern struct stm_usb stm_usb;
1929 #define STM_USB_EPR_CTR_RX 15
1930 #define STM_USB_EPR_CTR_RX_WRITE_INVARIANT 1
1931 #define STM_USB_EPR_DTOG_RX 14
1932 #define STM_USB_EPR_DTOG_RX_WRITE_INVARIANT 0
1933 #define STM_USB_EPR_STAT_RX 12
1934 #define STM_USB_EPR_STAT_RX_DISABLED 0
1935 #define STM_USB_EPR_STAT_RX_STALL 1
1936 #define STM_USB_EPR_STAT_RX_NAK 2
1937 #define STM_USB_EPR_STAT_RX_VALID 3
1938 #define STM_USB_EPR_STAT_RX_MASK 3
1939 #define STM_USB_EPR_STAT_RX_WRITE_INVARIANT 0
1940 #define STM_USB_EPR_SETUP 11
1941 #define STM_USB_EPR_EP_TYPE 9
1942 #define STM_USB_EPR_EP_TYPE_BULK 0
1943 #define STM_USB_EPR_EP_TYPE_CONTROL 1
1944 #define STM_USB_EPR_EP_TYPE_ISO 2
1945 #define STM_USB_EPR_EP_TYPE_INTERRUPT 3
1946 #define STM_USB_EPR_EP_TYPE_MASK 3
1947 #define STM_USB_EPR_EP_KIND 8
1948 #define STM_USB_EPR_EP_KIND_DBL_BUF 1 /* Bulk */
1949 #define STM_USB_EPR_EP_KIND_STATUS_OUT 1 /* Control */
1950 #define STM_USB_EPR_CTR_TX 7
1951 #define STM_USB_CTR_TX_WRITE_INVARIANT 1
1952 #define STM_USB_EPR_DTOG_TX 6
1953 #define STM_USB_EPR_DTOG_TX_WRITE_INVARIANT 0
1954 #define STM_USB_EPR_STAT_TX 4
1955 #define STM_USB_EPR_STAT_TX_DISABLED 0
1956 #define STM_USB_EPR_STAT_TX_STALL 1
1957 #define STM_USB_EPR_STAT_TX_NAK 2
1958 #define STM_USB_EPR_STAT_TX_VALID 3
1959 #define STM_USB_EPR_STAT_TX_WRITE_INVARIANT 0
1960 #define STM_USB_EPR_STAT_TX_MASK 3
1961 #define STM_USB_EPR_EA 0
1962 #define STM_USB_EPR_EA_MASK 0xf
1964 #define STM_USB_CNTR_CTRM 15
1965 #define STM_USB_CNTR_PMAOVRM 14
1966 #define STM_USB_CNTR_ERRM 13
1967 #define STM_USB_CNTR_WKUPM 12
1968 #define STM_USB_CNTR_SUSPM 11
1969 #define STM_USB_CNTR_RESETM 10
1970 #define STM_USB_CNTR_SOFM 9
1971 #define STM_USB_CNTR_ESOFM 8
1972 #define STM_USB_CNTR_RESUME 4
1973 #define STM_USB_CNTR_FSUSP 3
1974 #define STM_USB_CNTR_LP_MODE 2
1975 #define STM_USB_CNTR_PDWN 1
1976 #define STM_USB_CNTR_FRES 0
1978 #define STM_USB_ISTR_CTR 15
1979 #define STM_USB_ISTR_PMAOVR 14
1980 #define STM_USB_ISTR_ERR 13
1981 #define STM_USB_ISTR_WKUP 12
1982 #define STM_USB_ISTR_SUSP 11
1983 #define STM_USB_ISTR_RESET 10
1984 #define STM_USB_ISTR_SOF 9
1985 #define STM_USB_ISTR_ESOF 8
1986 #define STM_USB_L1REQ 7
1987 #define STM_USB_ISTR_DIR 4
1988 #define STM_USB_ISTR_EP_ID 0
1989 #define STM_USB_ISTR_EP_ID_MASK 0xf
1991 #define STM_USB_FNR_RXDP 15
1992 #define STM_USB_FNR_RXDM 14
1993 #define STM_USB_FNR_LCK 13
1994 #define STM_USB_FNR_LSOF 11
1995 #define STM_USB_FNR_LSOF_MASK 0x3
1996 #define STM_USB_FNR_FN 0
1997 #define STM_USB_FNR_FN_MASK 0x7ff
1999 #define STM_USB_DADDR_EF 7
2000 #define STM_USB_DADDR_ADD 0
2001 #define STM_USB_DADDR_ADD_MASK 0x7f
2003 #define STM_USB_BCDR_DPPU 15
2004 #define STM_USB_BCDR_PS2DET 7
2005 #define STM_USB_BCDR_SDET 6
2006 #define STM_USB_BCDR_PDET 5
2007 #define STM_USB_BCDR_DCDET 4
2008 #define STM_USB_BCDR_SDEN 3
2009 #define STM_USB_BCDR_PDEN 2
2010 #define STM_USB_BCDR_DCDEN 1
2011 #define STM_USB_BCDR_BCDEN 0
2030 #define STM_USB_BDT_COUNT_RX_BL_SIZE 15
2031 #define STM_USB_BDT_COUNT_RX_NUM_BLOCK 10
2032 #define STM_USB_BDT_COUNT_RX_NUM_BLOCK_MASK 0x1f
2033 #define STM_USB_BDT_COUNT_RX_COUNT_RX 0
2034 #define STM_USB_BDT_COUNT_RX_COUNT_RX_MASK 0x1ff
2036 #define STM_USB_BDT_SIZE 8
2038 extern uint8_t stm_usb_sram[];
2050 extern struct stm_exti stm_exti;
2052 #endif /* _STM32F0_H_ */