2 * Copyright © 2018 Keith Packard <keithp@keithp.com>
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
12 * General Public License for more details.
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
26 #if HAS_TICK || defined(AO_TIMER_HOOK)
29 volatile AO_TICK_TYPE ao_tick_count;
39 volatile uint8_t ao_data_interval = 1;
40 volatile uint8_t ao_data_count;
43 void stm_systick_isr(void)
45 ao_validate_cur_stack();
46 if (stm_systick.csr & (1 << STM_SYSTICK_CSR_COUNTFLAG)) {
51 if (ao_task_alarm_tick && (int16_t) (ao_tick_count - ao_task_alarm_tick) >= 0)
52 ao_task_check_alarm((uint16_t) ao_tick_count);
55 if (++ao_data_count == ao_data_interval) {
58 if (ao_fake_flight_active)
59 ao_fake_flight_poll();
63 #if (AO_DATA_ALL & ~(AO_DATA_ADC))
64 ao_wakeup((void *) &ao_data_count);
76 ao_timer_set_adc_interval(uint8_t interval)
79 ao_data_interval = interval;
85 #define SYSTICK_RELOAD ((AO_SYSTICK / 8) / 100 - 1)
90 stm_systick.rvr = SYSTICK_RELOAD;
92 stm_systick.csr = ((1 << STM_SYSTICK_CSR_ENABLE) |
93 (1 << STM_SYSTICK_CSR_TICKINT) |
94 (STM_SYSTICK_CSR_CLKSOURCE_AHB_8 << STM_SYSTICK_CSR_CLKSOURCE));
95 stm_scb.shpr3 |= AO_STM_NVIC_CLOCK_PRIORITY << 24;
106 /* Switch to HSI while messing about */
107 stm_rcc.cr |= (1 << STM_RCC_CR_HSION);
108 while (!(stm_rcc.cr & (1 << STM_RCC_CR_HSIRDY)))
111 stm_rcc.cfgr = (stm_rcc.cfgr & ~(STM_RCC_CFGR_SW_MASK << STM_RCC_CFGR_SW)) |
112 (STM_RCC_CFGR_SW_HSI << STM_RCC_CFGR_SW);
114 /* wait for system to switch to HSI */
115 while ((stm_rcc.cfgr & (STM_RCC_CFGR_SWS_MASK << STM_RCC_CFGR_SWS)) !=
116 (STM_RCC_CFGR_SWS_HSI << STM_RCC_CFGR_SWS))
119 /* reset everything but the HSI selection and status */
120 stm_rcc.cfgr &= (uint32_t)0x0000000f;
122 /* reset everything but HSI */
123 stm_rcc.cr &= 0x0000ffff;
125 /* Disable and clear all interrupts */
126 stm_rcc.cir = 0xffff0000;
130 stm_rcc.cr |= (1 << STM_RCC_CR_HSEBYP);
132 stm_rcc.cr &= ~(1 << STM_RCC_CR_HSEBYP);
134 /* Enable HSE clock */
135 stm_rcc.cr |= (1 << STM_RCC_CR_HSEON);
136 while (!(stm_rcc.cr & (1 << STM_RCC_CR_HSERDY)))
141 /* Set flash latency to tolerate SYSCLK */
143 #define FLASH_LATENCY ((AO_SYSCLK - 1) / 25000000)
145 /* Enable icache, dcache and prefetch. Set latency */
146 stm_flash.acr = ((1 << STM_FLASH_ACR_DCEN) |
147 (1 << STM_FLASH_ACR_ICEN) |
148 (1 << STM_FLASH_ACR_PRFTEN) |
149 (FLASH_LATENCY << STM_FLASH_ACR_LATENCY));
151 /* Enable power interface clock */
152 stm_rcc.apb1enr |= (1 << STM_RCC_APB1ENR_PWREN);
154 #if AO_SYSCLK <= 64000000
155 #define VOS_SCALE_MODE STM_PWR_CR_VOS_SCALE_MODE_1
156 #elif AO_SYSCLK <= 84000000
157 #define VOS_SCALE_MODE STM_PWR_CR_VOS_SCALE_MODE_2
159 #define VOS_SCALE_MODE STM_PWR_CR_VOS_SCALE_MODE_1
162 /* Set voltage scale mode */
163 stm_pwr.cr = ((stm_pwr.cr & ~(STM_PWR_CR_VOS_SCALE_MODE_MASK)) |
164 (VOS_SCALE_MODE << STM_PWR_CR_VOS));
168 cfgr &= ~(STM_RCC_CFGR_HPRE_MASK << STM_RCC_CFGR_HPRE);
169 cfgr |= (AO_RCC_CFGR_HPRE_DIV << STM_RCC_CFGR_HPRE);
172 /* APB1 Prescaler = AO_APB1_PRESCALER */
174 cfgr &= ~(STM_RCC_CFGR_PPRE1_MASK << STM_RCC_CFGR_PPRE1);
175 cfgr |= (AO_RCC_CFGR_PPRE1_DIV << STM_RCC_CFGR_PPRE1);
178 /* APB2 Prescaler = AO_APB2_PRESCALER */
180 cfgr &= ~(STM_RCC_CFGR_PPRE2_MASK << STM_RCC_CFGR_PPRE2);
181 cfgr |= (AO_RCC_CFGR_PPRE2_DIV << STM_RCC_CFGR_PPRE2);
184 /* Clock configuration register DCKCFGR2; mostly make sure USB
185 * gets clocked from PLL_Q
187 stm_rcc.dckcfgr2 = ((STM_RCC_DCKCFGR2_LPTIMER1SEL_APB << STM_RCC_DCKCFGR2_LPTIMER1SEL) |
188 (STM_RCC_DCKCFGR2_SDIOSEL_CK_48MHZ << STM_RCC_DCKCFGR2_SDIOSEL) |
189 (STM_RCC_DCKCFGR2_CK48MSEL_PLL_Q << STM_RCC_DCKCFGR2_CK48MSEL) |
190 (STM_RCC_DCKCFGR2_I2CFMP1SEL_APB << STM_RCC_DCKCFGR2_I2CFMP1SEL));
192 /* Disable the PLL */
193 stm_rcc.cr &= ~(1 << STM_RCC_CR_PLLON);
194 while (stm_rcc.cr & (1 << STM_RCC_CR_PLLRDY))
198 pllcfgr = stm_rcc.pllcfgr;
199 pllcfgr &= ~(STM_RCC_PLLCFGR_PLLM_MASK << STM_RCC_PLLCFGR_PLLM);
200 pllcfgr &= ~(STM_RCC_PLLCFGR_PLLN_MASK << STM_RCC_PLLCFGR_PLLN);
201 pllcfgr &= ~(STM_RCC_PLLCFGR_PLLP_MASK << STM_RCC_PLLCFGR_PLLP);
202 pllcfgr &= ~(STM_RCC_PLLCFGR_PLLQ_MASK << STM_RCC_PLLCFGR_PLLQ);
203 pllcfgr &= ~(STM_RCC_PLLCFGR_PLLR_MASK << STM_RCC_PLLCFGR_PLLR);
205 pllcfgr |= (AO_PLL_M << STM_RCC_PLLCFGR_PLLM);
206 pllcfgr |= (AO_PLL1_N << STM_RCC_PLLCFGR_PLLN);
208 #define AO_RCC_PLLCFGR_PLLP STM_RCC_PLLCFGR_PLLP_DIV_2
211 #define AO_RCC_PLLCFGR_PLLP STM_RCC_PLLCFGR_PLLP_DIV_4
214 #define AO_RCC_PLLCFGR_PLLP STM_RCC_PLLCFGR_PLLP_DIV_6
217 #define AO_RCC_PLLCFGR_PLLP STM_RCC_PLLCFGR_PLLP_DIV_8
219 pllcfgr |= (AO_RCC_PLLCFGR_PLLP << STM_RCC_PLLCFGR_PLLP);
220 pllcfgr |= (AO_PLL1_Q << STM_RCC_PLLCFGR_PLLQ);
221 pllcfgr |= (AO_PLL1_R << STM_RCC_PLLCFGR_PLLR);
223 pllcfgr &= ~(1 << STM_RCC_PLLCFGR_PLLSRC);
225 pllcfgr |= (STM_RCC_PLLCFGR_PLLSRC_HSI << STM_RCC_PLLCFGR_PLLSRC);
228 pllcfgr |= (STM_RCC_PLLCFGR_PLLSRC_HSE << STM_RCC_PLLCFGR_PLLSRC);
230 stm_rcc.pllcfgr = pllcfgr;
232 /* Enable the PLL and wait for it */
233 stm_rcc.cr |= (1 << STM_RCC_CR_PLLON);
234 while (!(stm_rcc.cr & (1 << STM_RCC_CR_PLLRDY)))
237 /* Switch to the PLL for the system clock */
240 cfgr &= ~(STM_RCC_CFGR_SW_MASK << STM_RCC_CFGR_SW);
241 cfgr |= (STM_RCC_CFGR_SW_PLL << STM_RCC_CFGR_SW);
244 uint32_t c, part, mask, val;
247 mask = (STM_RCC_CFGR_SWS_MASK << STM_RCC_CFGR_SWS);
248 val = (STM_RCC_CFGR_SWS_PLL << STM_RCC_CFGR_SWS);
255 /* Disable HSI clock */
256 stm_rcc.cr &= ~(1 << STM_RCC_CR_HSION);
259 /* Clear reset flags */
260 stm_rcc.csr |= (1 << STM_RCC_CSR_RMVF);
263 /* Output PLL clock on PA8 and SYCLK on PC9 for measurments */
265 ao_enable_port(&stm_gpioa);
266 stm_afr_set(&stm_gpioa, 8, STM_AFR_AF0);
267 stm_moder_set(&stm_gpioa, 8, STM_MODER_ALTERNATE);
268 stm_ospeedr_set(&stm_gpioa, 8, STM_OSPEEDR_HIGH);
270 ao_enable_port(&stm_gpioc);
271 stm_afr_set(&stm_gpioc, 9, STM_AFR_AF0);
272 stm_moder_set(&stm_gpioc, 9, STM_MODER_ALTERNATE);
273 stm_ospeedr_set(&stm_gpioc, 9, STM_OSPEEDR_HIGH);
277 cfgr |= ((0 << STM_RCC_CFGR_MCO2) |
278 (6 << STM_RCC_CFGR_MCO2PRE) |
279 (6 << STM_RCC_CFGR_MCO1PRE) |
280 (2 << STM_RCC_CFGR_MCO1));