2 * Copyright © 2012 Keith Packard <keithp@keithp.com>
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; version 2 of the License.
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
11 * General Public License for more details.
13 * You should have received a copy of the GNU General Public License along
14 * with this program; if not, write to the Free Software Foundation, Inc.,
15 * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
21 volatile __data AO_TICK_TYPE ao_tick_count;
23 uint16_t ao_time(void)
33 volatile __data uint8_t ao_data_interval = 1;
34 volatile __data uint8_t ao_data_count;
41 void stm_tim6_isr(void)
43 if (stm_tim6.sr & (1 << STM_TIM67_SR_UIF)) {
47 if (ao_task_alarm_tick && (int16_t) (ao_tick_count - ao_task_alarm_tick) >= 0)
48 ao_task_check_alarm((uint16_t) ao_tick_count);
51 if (++ao_data_count == ao_data_interval) {
54 #if (AO_DATA_ALL & ~(AO_DATA_ADC))
55 ao_wakeup((void *) &ao_data_count);
64 ao_timer_set_adc_interval(uint8_t interval)
67 ao_data_interval = interval;
74 * According to the STM clock-configuration, timers run
75 * twice as fast as the APB1 clock *if* the APB1 prescaler
79 #if AO_APB1_PRESCALER > 1
80 #define TIMER_23467_SCALER 2
82 #define TIMER_23467_SCALER 1
85 #define TIMER_10kHz ((AO_PCLK1 * TIMER_23467_SCALER) / 10000)
90 stm_nvic_set_enable(STM_ISR_TIM6_POS);
91 stm_nvic_set_priority(STM_ISR_TIM6_POS, AO_STM_NVIC_CLOCK_PRIORITY);
94 stm_rcc.apb1enr |= (1 << STM_RCC_APB1ENR_TIM6EN);
96 stm_tim6.psc = TIMER_10kHz;
100 /* Enable update interrupt */
101 stm_tim6.dier = (1 << STM_TIM67_DIER_UIE);
103 /* Poke timer to reload values */
104 stm_tim6.egr |= (1 << STM_TIM67_EGR_UG);
106 stm_tim6.cr2 = (STM_TIM67_CR2_MMS_RESET << STM_TIM67_CR2_MMS);
109 stm_tim6.cr1 = ((0 << STM_TIM67_CR1_ARPE) |
110 (0 << STM_TIM67_CR1_OPM) |
111 (1 << STM_TIM67_CR1_URS) |
112 (0 << STM_TIM67_CR1_UDIS) |
113 (1 << STM_TIM67_CR1_CEN));
122 /* Switch to MSI while messing about */
123 stm_rcc.cr |= (1 << STM_RCC_CR_MSION);
124 while (!(stm_rcc.cr & (1 << STM_RCC_CR_MSIRDY)))
127 /* reset SW, HPRE, PPRE1, PPRE2, MCOSEL and MCOPRE */
128 stm_rcc.cfgr &= (uint32_t)0x88FFC00C;
130 /* reset HSION, HSEON, CSSON and PLLON bits */
131 stm_rcc.cr &= 0xeefefffe;
133 /* reset PLLSRC, PLLMUL and PLLDIV bits */
134 stm_rcc.cfgr &= 0xff02ffff;
136 /* Disable all interrupts */
141 stm_rcc.cr |= (1 << STM_RCC_CR_HSEBYP);
143 stm_rcc.cr &= ~(1 << STM_RCC_CR_HSEBYP);
145 /* Enable HSE clock */
146 stm_rcc.cr |= (1 << STM_RCC_CR_HSEON);
147 while (!(stm_rcc.cr & (1 << STM_RCC_CR_HSERDY)))
150 #define STM_RCC_CFGR_SWS_TARGET_CLOCK (STM_RCC_CFGR_SWS_HSE << STM_RCC_CFGR_SWS)
151 #define STM_RCC_CFGR_SW_TARGET_CLOCK (STM_RCC_CFGR_SW_HSE)
152 #define STM_PLLSRC AO_HSE
153 #define STM_RCC_CFGR_PLLSRC_TARGET_CLOCK (1 << STM_RCC_CFGR_PLLSRC)
155 #define STM_HSI 16000000
156 #define STM_RCC_CFGR_SWS_TARGET_CLOCK (STM_RCC_CFGR_SWS_HSI << STM_RCC_CFGR_SWS)
157 #define STM_RCC_CFGR_SW_TARGET_CLOCK (STM_RCC_CFGR_SW_HSI)
158 #define STM_PLLSRC STM_HSI
159 #define STM_RCC_CFGR_PLLSRC_TARGET_CLOCK (0 << STM_RCC_CFGR_PLLSRC)
162 #if !AO_HSE || HAS_ADC
163 /* Enable HSI RC clock 16MHz */
164 stm_rcc.cr |= (1 << STM_RCC_CR_HSION);
165 while (!(stm_rcc.cr & (1 << STM_RCC_CR_HSIRDY)))
169 /* Set flash latency to tolerate 32MHz SYSCLK -> 1 wait state */
171 /* Enable 64-bit access and prefetch */
172 stm_flash.acr |= (1 << STM_FLASH_ACR_ACC64);
173 stm_flash.acr |= (1 << STM_FLASH_ACR_PRFEN);
175 /* Enable 1 wait state so the CPU can run at 32MHz */
176 /* (haven't managed to run the CPU at 32MHz yet, it's at 16MHz) */
177 stm_flash.acr |= (1 << STM_FLASH_ACR_LATENCY);
179 /* Enable power interface clock */
180 stm_rcc.apb1enr |= (1 << STM_RCC_APB1ENR_PWREN);
182 /* Set voltage range to 1.8V */
184 /* poll VOSF bit in PWR_CSR. Wait until it is reset to 0 */
185 while ((stm_pwr.csr & (1 << STM_PWR_CSR_VOSF)) != 0)
188 /* Configure voltage scaling range */
190 cr &= ~(STM_PWR_CR_VOS_MASK << STM_PWR_CR_VOS);
191 cr |= (STM_PWR_CR_VOS_1_8 << STM_PWR_CR_VOS);
194 /* poll VOSF bit in PWR_CSR. Wait until it is reset to 0 */
195 while ((stm_pwr.csr & (1 << STM_PWR_CSR_VOSF)) != 0)
198 /* HCLK to 16MHz -> AHB prescaler = /1 */
200 cfgr &= ~(STM_RCC_CFGR_HPRE_MASK << STM_RCC_CFGR_HPRE);
201 cfgr |= (AO_RCC_CFGR_HPRE_DIV << STM_RCC_CFGR_HPRE);
203 while ((stm_rcc.cfgr & (STM_RCC_CFGR_HPRE_MASK << STM_RCC_CFGR_HPRE)) !=
204 (AO_RCC_CFGR_HPRE_DIV << STM_RCC_CFGR_HPRE))
207 /* APB1 Prescaler = AO_APB1_PRESCALER */
209 cfgr &= ~(STM_RCC_CFGR_PPRE1_MASK << STM_RCC_CFGR_PPRE1);
210 cfgr |= (AO_RCC_CFGR_PPRE1_DIV << STM_RCC_CFGR_PPRE1);
213 /* APB2 Prescaler = AO_APB2_PRESCALER */
215 cfgr &= ~(STM_RCC_CFGR_PPRE2_MASK << STM_RCC_CFGR_PPRE2);
216 cfgr |= (AO_RCC_CFGR_PPRE2_DIV << STM_RCC_CFGR_PPRE2);
219 /* Disable the PLL */
220 stm_rcc.cr &= ~(1 << STM_RCC_CR_PLLON);
221 while (stm_rcc.cr & (1 << STM_RCC_CR_PLLRDY))
224 /* PLLVCO to 96MHz (for USB) -> PLLMUL = 6, PLLDIV = 4 */
226 cfgr &= ~(STM_RCC_CFGR_PLLMUL_MASK << STM_RCC_CFGR_PLLMUL);
227 cfgr &= ~(STM_RCC_CFGR_PLLDIV_MASK << STM_RCC_CFGR_PLLDIV);
229 cfgr |= (AO_RCC_CFGR_PLLMUL << STM_RCC_CFGR_PLLMUL);
230 cfgr |= (AO_RCC_CFGR_PLLDIV << STM_RCC_CFGR_PLLDIV);
233 cfgr &= ~(1 << STM_RCC_CFGR_PLLSRC);
234 cfgr |= STM_RCC_CFGR_PLLSRC_TARGET_CLOCK;
238 /* Enable the PLL and wait for it */
239 stm_rcc.cr |= (1 << STM_RCC_CR_PLLON);
240 while (!(stm_rcc.cr & (1 << STM_RCC_CR_PLLRDY)))
243 /* Switch to the PLL for the system clock */
246 cfgr &= ~(STM_RCC_CFGR_SW_MASK << STM_RCC_CFGR_SW);
247 cfgr |= (STM_RCC_CFGR_SW_PLL << STM_RCC_CFGR_SW);
250 uint32_t c, part, mask, val;
253 mask = (STM_RCC_CFGR_SWS_MASK << STM_RCC_CFGR_SWS);
254 val = (STM_RCC_CFGR_SWS_PLL << STM_RCC_CFGR_SWS);
261 stm_rcc.apb2rstr = 0xffff;
262 stm_rcc.apb1rstr = 0xffff;
263 stm_rcc.ahbrstr = 0x3f;
264 stm_rcc.ahbenr = (1 << STM_RCC_AHBENR_FLITFEN);
268 stm_rcc.apb1rstr = 0;
269 stm_rcc.apb2rstr = 0;
272 /* Clear reset flags */
273 stm_rcc.csr |= (1 << STM_RCC_CSR_RMVF);
277 /* Output SYSCLK on PA8 for measurments */
279 stm_rcc.ahbenr |= (1 << STM_RCC_AHBENR_GPIOAEN);
281 stm_afr_set(&stm_gpioa, 8, STM_AFR_AF0);
282 stm_moder_set(&stm_gpioa, 8, STM_MODER_ALTERNATE);
283 stm_ospeedr_set(&stm_gpioa, 8, STM_OSPEEDR_40MHz);
285 stm_rcc.cfgr |= (STM_RCC_CFGR_MCOPRE_DIV_1 << STM_RCC_CFGR_MCOPRE);
286 stm_rcc.cfgr |= (STM_RCC_CFGR_MCOSEL_HSE << STM_RCC_CFGR_MCOSEL);