2 * Copyright © 2012 Keith Packard <keithp@keithp.com>
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; version 2 of the License.
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
11 * General Public License for more details.
13 * You should have received a copy of the GNU General Public License along
14 * with this program; if not, write to the Free Software Foundation, Inc.,
15 * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
26 volatile AO_TICK_TYPE ao_tick_count;
35 volatile __data uint8_t ao_data_interval = 1;
36 volatile __data uint8_t ao_data_count;
39 void stm_systick_isr(void)
41 if (stm_systick.csr & (1 << STM_SYSTICK_CSR_COUNTFLAG)) {
44 if (ao_task_alarm_tick && (int16_t) (ao_tick_count - ao_task_alarm_tick) >= 0)
45 ao_task_check_alarm((uint16_t) ao_tick_count);
48 if (++ao_data_count == ao_data_interval) {
51 #if (AO_DATA_ALL & ~(AO_DATA_ADC))
52 ao_wakeup((void *) &ao_data_count);
64 ao_timer_set_adc_interval(uint8_t interval)
67 ao_data_interval = interval;
73 #define SYSTICK_RELOAD (AO_SYSTICK / 100 - 1)
78 stm_systick.rvr = SYSTICK_RELOAD;
80 stm_systick.csr = ((1 << STM_SYSTICK_CSR_ENABLE) |
81 (1 << STM_SYSTICK_CSR_TICKINT) |
82 (STM_SYSTICK_CSR_CLKSOURCE_HCLK_8 << STM_SYSTICK_CSR_CLKSOURCE));
93 /* Switch to MSI while messing about */
94 stm_rcc.cr |= (1 << STM_RCC_CR_MSION);
95 while (!(stm_rcc.cr & (1 << STM_RCC_CR_MSIRDY)))
98 stm_rcc.cfgr = (stm_rcc.cfgr & ~(STM_RCC_CFGR_SW_MASK << STM_RCC_CFGR_SW)) |
99 (STM_RCC_CFGR_SW_MSI << STM_RCC_CFGR_SW);
101 /* wait for system to switch to MSI */
102 while ((stm_rcc.cfgr & (STM_RCC_CFGR_SWS_MASK << STM_RCC_CFGR_SWS)) !=
103 (STM_RCC_CFGR_SWS_MSI << STM_RCC_CFGR_SWS))
106 /* reset SW, HPRE, PPRE1, PPRE2, MCOSEL and MCOPRE */
107 stm_rcc.cfgr &= (uint32_t)0x88FFC00C;
109 /* reset HSION, HSEON, CSSON and PLLON bits */
110 stm_rcc.cr &= 0xeefefffe;
112 /* reset PLLSRC, PLLMUL and PLLDIV bits */
113 stm_rcc.cfgr &= 0xff02ffff;
115 /* Disable all interrupts */
120 stm_rcc.cr |= (1 << STM_RCC_CR_HSEBYP);
122 stm_rcc.cr &= ~(1 << STM_RCC_CR_HSEBYP);
124 /* Enable HSE clock */
125 stm_rcc.cr |= (1 << STM_RCC_CR_HSEON);
126 while (!(stm_rcc.cr & (1 << STM_RCC_CR_HSERDY)))
129 #define STM_RCC_CFGR_SWS_TARGET_CLOCK (STM_RCC_CFGR_SWS_HSE << STM_RCC_CFGR_SWS)
130 #define STM_RCC_CFGR_SW_TARGET_CLOCK (STM_RCC_CFGR_SW_HSE)
131 #define STM_PLLSRC AO_HSE
132 #define STM_RCC_CFGR_PLLSRC_TARGET_CLOCK (1 << STM_RCC_CFGR_PLLSRC)
134 #define STM_HSI 16000000
135 #define STM_RCC_CFGR_SWS_TARGET_CLOCK (STM_RCC_CFGR_SWS_HSI << STM_RCC_CFGR_SWS)
136 #define STM_RCC_CFGR_SW_TARGET_CLOCK (STM_RCC_CFGR_SW_HSI)
137 #define STM_PLLSRC STM_HSI
138 #define STM_RCC_CFGR_PLLSRC_TARGET_CLOCK (0 << STM_RCC_CFGR_PLLSRC)
141 #if !AO_HSE || HAS_ADC
142 /* Enable HSI RC clock 16MHz */
143 stm_rcc.cr |= (1 << STM_RCC_CR_HSION);
144 while (!(stm_rcc.cr & (1 << STM_RCC_CR_HSIRDY)))
148 /* Set flash latency to tolerate 32MHz SYSCLK -> 1 wait state */
150 /* Enable 64-bit access and prefetch */
151 stm_flash.acr |= (1 << STM_FLASH_ACR_ACC64);
152 stm_flash.acr |= (1 << STM_FLASH_ACR_PRFEN);
154 /* Enable 1 wait state so the CPU can run at 32MHz */
155 stm_flash.acr |= (1 << STM_FLASH_ACR_LATENCY);
157 /* Enable power interface clock */
158 stm_rcc.apb1enr |= (1 << STM_RCC_APB1ENR_PWREN);
160 /* Set voltage range to 1.8V */
162 /* poll VOSF bit in PWR_CSR. Wait until it is reset to 0 */
163 while ((stm_pwr.csr & (1 << STM_PWR_CSR_VOSF)) != 0)
166 /* Configure voltage scaling range */
168 cr &= ~(STM_PWR_CR_VOS_MASK << STM_PWR_CR_VOS);
169 cr |= (STM_PWR_CR_VOS_1_8 << STM_PWR_CR_VOS);
172 /* poll VOSF bit in PWR_CSR. Wait until it is reset to 0 */
173 while ((stm_pwr.csr & (1 << STM_PWR_CSR_VOSF)) != 0)
176 /* HCLK to 16MHz -> AHB prescaler = /1 */
178 cfgr &= ~(STM_RCC_CFGR_HPRE_MASK << STM_RCC_CFGR_HPRE);
179 cfgr |= (AO_RCC_CFGR_HPRE_DIV << STM_RCC_CFGR_HPRE);
181 while ((stm_rcc.cfgr & (STM_RCC_CFGR_HPRE_MASK << STM_RCC_CFGR_HPRE)) !=
182 (AO_RCC_CFGR_HPRE_DIV << STM_RCC_CFGR_HPRE))
185 /* APB1 Prescaler = AO_APB1_PRESCALER */
187 cfgr &= ~(STM_RCC_CFGR_PPRE1_MASK << STM_RCC_CFGR_PPRE1);
188 cfgr |= (AO_RCC_CFGR_PPRE1_DIV << STM_RCC_CFGR_PPRE1);
191 /* APB2 Prescaler = AO_APB2_PRESCALER */
193 cfgr &= ~(STM_RCC_CFGR_PPRE2_MASK << STM_RCC_CFGR_PPRE2);
194 cfgr |= (AO_RCC_CFGR_PPRE2_DIV << STM_RCC_CFGR_PPRE2);
197 /* Disable the PLL */
198 stm_rcc.cr &= ~(1 << STM_RCC_CR_PLLON);
199 while (stm_rcc.cr & (1 << STM_RCC_CR_PLLRDY))
202 /* PLLVCO to 96MHz (for USB) -> PLLMUL = 6, PLLDIV = 4 */
204 cfgr &= ~(STM_RCC_CFGR_PLLMUL_MASK << STM_RCC_CFGR_PLLMUL);
205 cfgr &= ~(STM_RCC_CFGR_PLLDIV_MASK << STM_RCC_CFGR_PLLDIV);
207 cfgr |= (AO_RCC_CFGR_PLLMUL << STM_RCC_CFGR_PLLMUL);
208 cfgr |= (AO_RCC_CFGR_PLLDIV << STM_RCC_CFGR_PLLDIV);
211 cfgr &= ~(1 << STM_RCC_CFGR_PLLSRC);
212 cfgr |= STM_RCC_CFGR_PLLSRC_TARGET_CLOCK;
216 /* Enable the PLL and wait for it */
217 stm_rcc.cr |= (1 << STM_RCC_CR_PLLON);
218 while (!(stm_rcc.cr & (1 << STM_RCC_CR_PLLRDY)))
221 /* Switch to the PLL for the system clock */
224 cfgr &= ~(STM_RCC_CFGR_SW_MASK << STM_RCC_CFGR_SW);
225 cfgr |= (STM_RCC_CFGR_SW_PLL << STM_RCC_CFGR_SW);
228 uint32_t c, part, mask, val;
231 mask = (STM_RCC_CFGR_SWS_MASK << STM_RCC_CFGR_SWS);
232 val = (STM_RCC_CFGR_SWS_PLL << STM_RCC_CFGR_SWS);
239 stm_rcc.apb2rstr = 0xffff;
240 stm_rcc.apb1rstr = 0xffff;
241 stm_rcc.ahbrstr = 0x3f;
242 stm_rcc.ahbenr = (1 << STM_RCC_AHBENR_FLITFEN);
246 stm_rcc.apb1rstr = 0;
247 stm_rcc.apb2rstr = 0;
250 /* Clear reset flags */
251 stm_rcc.csr |= (1 << STM_RCC_CSR_RMVF);
255 /* Output SYSCLK on PA8 for measurments */
257 stm_rcc.ahbenr |= (1 << STM_RCC_AHBENR_GPIOAEN);
259 stm_afr_set(&stm_gpioa, 8, STM_AFR_AF0);
260 stm_moder_set(&stm_gpioa, 8, STM_MODER_ALTERNATE);
261 stm_ospeedr_set(&stm_gpioa, 8, STM_OSPEEDR_40MHz);
263 stm_rcc.cfgr |= (STM_RCC_CFGR_MCOPRE_DIV_1 << STM_RCC_CFGR_MCOPRE);
264 stm_rcc.cfgr |= (STM_RCC_CFGR_MCOSEL_HSE << STM_RCC_CFGR_MCOSEL);