2 * Copyright © 2012 Keith Packard <keithp@keithp.com>
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
12 * General Public License for more details.
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
22 #include <ao_fake_flight.h>
29 #if HAS_TICK || defined(AO_TIMER_HOOK)
32 volatile AO_TICK_TYPE ao_tick_count;
43 AO_TICK_TYPE before, after;
47 before = ao_tick_count;
48 cvr = stm_systick.cvr;
49 after = ao_tick_count;
50 } while (before != after);
52 return (uint64_t) after * (1000000000ULL / AO_HERTZ) +
53 (uint64_t) cvr * (1000000000ULL / AO_SYSTICK);
59 volatile uint8_t ao_data_interval = 1;
60 volatile uint8_t ao_data_count;
63 void stm_systick_isr(void)
65 ao_validate_cur_stack();
66 if (stm_systick.csr & (1 << STM_SYSTICK_CSR_COUNTFLAG)) {
70 ao_task_check_alarm();
72 if (++ao_data_count == ao_data_interval && ao_data_interval) {
75 if (ao_fake_flight_active)
76 ao_fake_flight_poll();
80 #if (AO_DATA_ALL & ~(AO_DATA_ADC))
81 ao_wakeup((void *) &ao_data_count);
93 ao_timer_set_adc_interval(uint8_t interval)
96 ao_data_interval = interval;
102 #define SYSTICK_RELOAD (AO_SYSTICK / 100 - 1)
107 stm_systick.rvr = SYSTICK_RELOAD;
109 stm_systick.csr = ((1 << STM_SYSTICK_CSR_ENABLE) |
110 (1 << STM_SYSTICK_CSR_TICKINT) |
111 (STM_SYSTICK_CSR_CLKSOURCE_HCLK_8 << STM_SYSTICK_CSR_CLKSOURCE));
112 stm_nvic.shpr15_12 |= (uint32_t) AO_STM_NVIC_CLOCK_PRIORITY << 24;
123 /* Switch to MSI while messing about */
124 stm_rcc.cr |= (1 << STM_RCC_CR_MSION);
125 while (!(stm_rcc.cr & (1 << STM_RCC_CR_MSIRDY)))
128 stm_rcc.cfgr = (stm_rcc.cfgr & ~(uint32_t) (STM_RCC_CFGR_SW_MASK << STM_RCC_CFGR_SW)) |
129 (STM_RCC_CFGR_SW_MSI << STM_RCC_CFGR_SW);
131 /* wait for system to switch to MSI */
132 while ((stm_rcc.cfgr & (STM_RCC_CFGR_SWS_MASK << STM_RCC_CFGR_SWS)) !=
133 (STM_RCC_CFGR_SWS_MSI << STM_RCC_CFGR_SWS))
136 /* reset SW, HPRE, PPRE1, PPRE2, MCOSEL and MCOPRE */
137 stm_rcc.cfgr &= (uint32_t)0x88FFC00C;
139 /* reset HSION, HSEON, CSSON and PLLON bits */
140 stm_rcc.cr &= 0xeefefffe;
142 /* reset PLLSRC, PLLMUL and PLLDIV bits */
143 stm_rcc.cfgr &= 0xff02ffff;
145 /* Disable all interrupts */
150 stm_rcc.cr |= (1 << STM_RCC_CR_HSEBYP);
152 stm_rcc.cr &= ~(uint32_t) (1 << STM_RCC_CR_HSEBYP);
154 /* Enable HSE clock */
155 stm_rcc.cr |= (1 << STM_RCC_CR_HSEON);
156 while (!(stm_rcc.cr & (1 << STM_RCC_CR_HSERDY)))
159 #define STM_RCC_CFGR_SWS_TARGET_CLOCK (STM_RCC_CFGR_SWS_HSE << STM_RCC_CFGR_SWS)
160 #define STM_RCC_CFGR_SW_TARGET_CLOCK (STM_RCC_CFGR_SW_HSE)
161 #define STM_PLLSRC AO_HSE
162 #define STM_RCC_CFGR_PLLSRC_TARGET_CLOCK (1 << STM_RCC_CFGR_PLLSRC)
164 #define STM_HSI 16000000
165 #define STM_RCC_CFGR_SWS_TARGET_CLOCK (STM_RCC_CFGR_SWS_HSI << STM_RCC_CFGR_SWS)
166 #define STM_RCC_CFGR_SW_TARGET_CLOCK (STM_RCC_CFGR_SW_HSI)
167 #define STM_PLLSRC STM_HSI
168 #define STM_RCC_CFGR_PLLSRC_TARGET_CLOCK (0 << STM_RCC_CFGR_PLLSRC)
171 #if !AO_HSE || HAS_ADC || HAS_ADC_SINGLE
172 /* Enable HSI RC clock 16MHz */
173 stm_rcc.cr |= (1 << STM_RCC_CR_HSION);
174 while (!(stm_rcc.cr & (1 << STM_RCC_CR_HSIRDY)))
178 /* Set flash latency to tolerate 32MHz SYSCLK -> 1 wait state */
180 /* Enable 64-bit access and prefetch */
181 stm_flash.acr |= (1 << STM_FLASH_ACR_ACC64);
182 stm_flash.acr |= (1 << STM_FLASH_ACR_PRFEN);
184 /* Enable 1 wait state so the CPU can run at 32MHz */
185 stm_flash.acr |= (1 << STM_FLASH_ACR_LATENCY);
187 /* Enable power interface clock */
188 stm_rcc.apb1enr |= (1 << STM_RCC_APB1ENR_PWREN);
190 /* Set voltage range to 1.8V */
192 /* poll VOSF bit in PWR_CSR. Wait until it is reset to 0 */
193 while ((stm_pwr.csr & (1 << STM_PWR_CSR_VOSF)) != 0)
196 /* Configure voltage scaling range */
198 cr &= ~(STM_PWR_CR_VOS_MASK << STM_PWR_CR_VOS);
199 cr |= (STM_PWR_CR_VOS_1_8 << STM_PWR_CR_VOS);
202 /* poll VOSF bit in PWR_CSR. Wait until it is reset to 0 */
203 while ((stm_pwr.csr & (1 << STM_PWR_CSR_VOSF)) != 0)
206 /* HCLK to 16MHz -> AHB prescaler = /1 */
208 cfgr &= ~(STM_RCC_CFGR_HPRE_MASK << STM_RCC_CFGR_HPRE);
209 cfgr |= (AO_RCC_CFGR_HPRE_DIV << STM_RCC_CFGR_HPRE);
211 while ((stm_rcc.cfgr & (STM_RCC_CFGR_HPRE_MASK << STM_RCC_CFGR_HPRE)) !=
212 (AO_RCC_CFGR_HPRE_DIV << STM_RCC_CFGR_HPRE))
215 /* APB1 Prescaler = AO_APB1_PRESCALER */
217 cfgr &= ~(STM_RCC_CFGR_PPRE1_MASK << STM_RCC_CFGR_PPRE1);
218 cfgr |= (AO_RCC_CFGR_PPRE1_DIV << STM_RCC_CFGR_PPRE1);
221 /* APB2 Prescaler = AO_APB2_PRESCALER */
223 cfgr &= ~(STM_RCC_CFGR_PPRE2_MASK << STM_RCC_CFGR_PPRE2);
224 cfgr |= (AO_RCC_CFGR_PPRE2_DIV << STM_RCC_CFGR_PPRE2);
227 /* Disable the PLL */
228 stm_rcc.cr &= ~(1UL << STM_RCC_CR_PLLON);
229 while (stm_rcc.cr & (1UL << STM_RCC_CR_PLLRDY))
232 /* PLLVCO to 96MHz (for USB) -> PLLMUL = 6, PLLDIV = 4 */
234 cfgr &= ~(STM_RCC_CFGR_PLLMUL_MASK << STM_RCC_CFGR_PLLMUL);
235 cfgr &= ~(STM_RCC_CFGR_PLLDIV_MASK << STM_RCC_CFGR_PLLDIV);
237 cfgr |= (AO_RCC_CFGR_PLLMUL << STM_RCC_CFGR_PLLMUL);
238 cfgr |= (AO_RCC_CFGR_PLLDIV << STM_RCC_CFGR_PLLDIV);
241 cfgr &= ~(1UL << STM_RCC_CFGR_PLLSRC);
242 cfgr |= STM_RCC_CFGR_PLLSRC_TARGET_CLOCK;
246 /* Enable the PLL and wait for it */
247 stm_rcc.cr |= (1 << STM_RCC_CR_PLLON);
248 while (!(stm_rcc.cr & (1 << STM_RCC_CR_PLLRDY)))
251 /* Switch to the PLL for the system clock */
254 cfgr &= ~(STM_RCC_CFGR_SW_MASK << STM_RCC_CFGR_SW);
255 cfgr |= (STM_RCC_CFGR_SW_PLL << STM_RCC_CFGR_SW);
258 uint32_t c, part, mask, val;
261 mask = (STM_RCC_CFGR_SWS_MASK << STM_RCC_CFGR_SWS);
262 val = (STM_RCC_CFGR_SWS_PLL << STM_RCC_CFGR_SWS);
269 stm_rcc.apb2rstr = 0xffff;
270 stm_rcc.apb1rstr = 0xffff;
271 stm_rcc.ahbrstr = 0x3f;
272 stm_rcc.ahbenr = (1 << STM_RCC_AHBENR_FLITFEN);
276 stm_rcc.apb1rstr = 0;
277 stm_rcc.apb2rstr = 0;
280 /* Clear reset flags */
281 stm_rcc.csr |= (1 << STM_RCC_CSR_RMVF);
285 /* Output SYSCLK on PA8 for measurments */
287 stm_rcc.ahbenr |= (1 << STM_RCC_AHBENR_GPIOAEN);
289 stm_afr_set(&stm_gpioa, 8, STM_AFR_AF0);
290 stm_moder_set(&stm_gpioa, 8, STM_MODER_ALTERNATE);
291 stm_ospeedr_set(&stm_gpioa, 8, STM_OSPEEDR_40MHz);
293 stm_rcc.cfgr |= (STM_RCC_CFGR_MCOPRE_DIV_1 << STM_RCC_CFGR_MCOPRE);
294 stm_rcc.cfgr |= (STM_RCC_CFGR_MCOSEL_HSE << STM_RCC_CFGR_MCOSEL);