2 * Copyright © 2012 Keith Packard <keithp@keithp.com>
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; version 2 of the License.
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
11 * General Public License for more details.
13 * You should have received a copy of the GNU General Public License along
14 * with this program; if not, write to the Free Software Foundation, Inc.,
15 * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
20 static volatile __data uint16_t ao_tick_count;
22 uint16_t ao_time(void)
31 static __xdata uint8_t ao_forever;
34 ao_delay(uint16_t ticks)
37 ao_sleep(&ao_forever);
41 volatile __data uint8_t ao_adc_interval = 1;
42 volatile __data uint8_t ao_adc_count;
49 void stm_tim6_isr(void)
51 if (stm_tim6.sr & (1 << STM_TIM67_SR_UIF)) {
55 if (++ao_adc_count == ao_adc_interval) {
65 ao_timer_set_adc_interval(uint8_t interval) __critical
67 ao_adc_interval = interval;
72 #define TIMER_10kHz (STM_APB1 / 10000)
77 stm_nvic_set_enable(STM_ISR_TIM6_POS);
78 stm_nvic_set_priority(STM_ISR_TIM6_POS, 1);
81 stm_rcc.apb1enr |= (1 << STM_RCC_APB1ENR_TIM6EN);
83 stm_tim6.psc = TIMER_10kHz;
87 /* Enable update interrupt */
88 stm_tim6.dier = (1 << STM_TIM67_DIER_UIE);
90 /* Poke timer to reload values */
91 stm_tim6.egr |= (1 << STM_TIM67_EGR_UG);
93 stm_tim6.cr2 = (STM_TIM67_CR2_MMS_RESET << STM_TIM67_CR2_MMS);
96 stm_tim6.cr1 = ((0 << STM_TIM67_CR1_ARPE) |
97 (0 << STM_TIM67_CR1_OPM) |
98 (1 << STM_TIM67_CR1_URS) |
99 (0 << STM_TIM67_CR1_UDIS) |
100 (1 << STM_TIM67_CR1_CEN));
109 /* Set flash latency to tolerate 32MHz SYSCLK -> 1 wait state */
110 uint32_t acr = stm_flash.acr;
112 /* Enable 64-bit access and prefetch */
113 acr |= (1 << STM_FLASH_ACR_ACC64) | (1 << STM_FLASH_ACR_PRFEN);
116 /* Enable 1 wait state so the CPU can run at 32MHz */
117 /* (haven't managed to run the CPU at 32MHz yet, it's at 16MHz) */
118 acr |= (1 << STM_FLASH_ACR_LATENCY);
121 /* HCLK to 16MHz -> AHB prescaler = /1 */
123 cfgr &= ~(STM_RCC_CFGR_HPRE_MASK << STM_RCC_CFGR_HPRE);
124 cfgr |= (STM_RCC_CFGR_HPRE_DIV_1 << STM_RCC_CFGR_HPRE);
126 while ((stm_rcc.cfgr & (STM_RCC_CFGR_HPRE_MASK << STM_RCC_CFGR_HPRE)) !=
127 (STM_RCC_CFGR_HPRE_DIV_1 << STM_RCC_CFGR_HPRE))
129 #define STM_AHB_PRESCALER 1
131 /* PCLK1 to 16MHz -> APB1 Prescaler = 1 */
133 cfgr &= ~(STM_RCC_CFGR_PPRE1_MASK << STM_RCC_CFGR_PPRE1);
134 cfgr |= (STM_RCC_CFGR_PPRE1_DIV_1 << STM_RCC_CFGR_PPRE1);
136 #define STM_APB1_PRESCALER 1
138 /* PCLK2 to 16MHz -> APB2 Prescaler = 1 */
140 cfgr &= ~(STM_RCC_CFGR_PPRE2_MASK << STM_RCC_CFGR_PPRE2);
141 cfgr |= (STM_RCC_CFGR_PPRE2_DIV_1 << STM_RCC_CFGR_PPRE2);
143 #define STM_APB2_PRESCALER 1
145 /* Enable power interface clock */
146 stm_rcc.apb1enr |= (1 << STM_RCC_APB1ENR_PWREN);
148 /* Set voltage range to 1.8V */
150 /* poll VOSF bit in PWR_CSR. Wait until it is reset to 0 */
151 while ((stm_pwr.csr & (1 << STM_PWR_CSR_VOSF)) != 0)
154 /* Configure voltage scaling range */
156 cr &= ~(STM_PWR_CR_VOS_MASK << STM_PWR_CR_VOS);
157 cr |= (STM_PWR_CR_VOS_1_8 << STM_PWR_CR_VOS);
160 /* poll VOSF bit in PWR_CSR. Wait until it is reset to 0 */
161 while ((stm_pwr.csr & (1 << STM_PWR_CSR_VOSF)) != 0)
164 /* Enable HSI RC clock 16MHz */
165 if (!(stm_rcc.cr & (1 << STM_RCC_CR_HSIRDY))) {
166 stm_rcc.cr |= (1 << STM_RCC_CR_HSION);
167 while (!(stm_rcc.cr & (1 << STM_RCC_CR_HSIRDY)))
170 #define STM_HSI 16000000
172 /* Switch to direct HSI for SYSCLK */
173 if ((stm_rcc.cfgr & (STM_RCC_CFGR_SWS_MASK << STM_RCC_CFGR_SWS)) !=
174 (STM_RCC_CFGR_SWS_HSI << STM_RCC_CFGR_SWS)) {
176 cfgr &= ~(STM_RCC_CFGR_SW_MASK << STM_RCC_CFGR_SW);
177 cfgr |= (STM_RCC_CFGR_SW_HSI << STM_RCC_CFGR_SW);
179 while ((stm_rcc.cfgr & (STM_RCC_CFGR_SWS_MASK << STM_RCC_CFGR_SWS)) !=
180 (STM_RCC_CFGR_SWS_HSI << STM_RCC_CFGR_SWS))
184 /* Disable the PLL */
185 stm_rcc.cr &= ~(1 << STM_RCC_CR_PLLON);
186 while (stm_rcc.cr & (1 << STM_RCC_CR_PLLRDY))
189 /* PLLVCO to 96MHz (for USB) -> PLLMUL = 6, PLLDIV = 4 */
191 cfgr &= ~(STM_RCC_CFGR_PLLMUL_MASK << STM_RCC_CFGR_PLLMUL);
192 cfgr &= ~(STM_RCC_CFGR_PLLDIV_MASK << STM_RCC_CFGR_PLLDIV);
194 // cfgr |= (STM_RCC_CFGR_PLLMUL_6 << STM_RCC_CFGR_PLLMUL);
195 // cfgr |= (STM_RCC_CFGR_PLLDIV_3 << STM_RCC_CFGR_PLLDIV);
197 cfgr |= (STM_RCC_CFGR_PLLMUL_6 << STM_RCC_CFGR_PLLMUL);
198 cfgr |= (STM_RCC_CFGR_PLLDIV_4 << STM_RCC_CFGR_PLLDIV);
203 /* PLL source to HSI */
204 cfgr &= ~(1 << STM_RCC_CFGR_PLLSRC);
206 #define STM_PLLSRC STM_HSI
210 /* Enable the PLL and wait for it */
211 stm_rcc.cr |= (1 << STM_RCC_CR_PLLON);
212 while (!(stm_rcc.cr & (1 << STM_RCC_CR_PLLRDY)))
215 /* Switch to the PLL for the system clock */
218 cfgr &= ~(STM_RCC_CFGR_SW_MASK << STM_RCC_CFGR_SW);
219 cfgr |= (STM_RCC_CFGR_SW_PLL << STM_RCC_CFGR_SW);
222 uint32_t c, part, mask, val;
225 mask = (STM_RCC_CFGR_SWS_MASK << STM_RCC_CFGR_SWS);
226 val = (STM_RCC_CFGR_SWS_PLL << STM_RCC_CFGR_SWS);