2 * Copyright © 2012 Keith Packard <keithp@keithp.com>
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; version 2 of the License.
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
11 * General Public License for more details.
13 * You should have received a copy of the GNU General Public License along
14 * with this program; if not, write to the Free Software Foundation, Inc.,
15 * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
20 static volatile __data uint16_t ao_tick_count;
22 uint16_t ao_time(void)
31 static __xdata uint8_t ao_forever;
34 ao_delay(uint16_t ticks)
37 ao_sleep(&ao_forever);
41 volatile __data uint8_t ao_adc_interval = 1;
42 volatile __data uint8_t ao_adc_count;
49 void stm_tim6_isr(void)
51 if (stm_tim6.sr & (1 << STM_TIM67_SR_UIF)) {
55 if (++ao_adc_count == ao_adc_interval) {
65 ao_timer_set_adc_interval(uint8_t interval) __critical
67 ao_adc_interval = interval;
72 #define TIMER_10kHz (AO_PCLK1 / 10000)
77 stm_nvic_set_enable(STM_ISR_TIM6_POS);
78 stm_nvic_set_priority(STM_ISR_TIM6_POS, 1);
81 stm_rcc.apb1enr |= (1 << STM_RCC_APB1ENR_TIM6EN);
83 stm_tim6.psc = TIMER_10kHz;
87 /* Enable update interrupt */
88 stm_tim6.dier = (1 << STM_TIM67_DIER_UIE);
90 /* Poke timer to reload values */
91 stm_tim6.egr |= (1 << STM_TIM67_EGR_UG);
93 stm_tim6.cr2 = (STM_TIM67_CR2_MMS_RESET << STM_TIM67_CR2_MMS);
96 stm_tim6.cr1 = ((0 << STM_TIM67_CR1_ARPE) |
97 (0 << STM_TIM67_CR1_OPM) |
98 (1 << STM_TIM67_CR1_URS) |
99 (0 << STM_TIM67_CR1_UDIS) |
100 (1 << STM_TIM67_CR1_CEN));
109 /* Switch to MSI while messing about */
110 stm_rcc.cr |= (1 << STM_RCC_CR_MSION);
111 while (!(stm_rcc.cr & (1 << STM_RCC_CR_MSIRDY)))
114 /* reset SW, HPRE, PPRE1, PPRE2, MCOSEL and MCOPRE */
115 stm_rcc.cfgr &= (uint32_t)0x88FFC00C;
117 /* reset HSION, HSEON, CSSON and PLLON bits */
118 stm_rcc.cr &= 0xeefefffe;
120 /* reset PLLSRC, PLLMUL and PLLDIV bits */
121 stm_rcc.cfgr &= 0xff02ffff;
123 /* Disable all interrupts */
128 stm_rcc.cr |= (1 << STM_RCC_CR_HSEBYP);
130 stm_rcc.cr &= ~(1 << STM_RCC_CR_HSEBYP);
132 /* Enable HSE clock */
133 stm_rcc.cr |= (1 << STM_RCC_CR_HSEON);
134 while (!(stm_rcc.cr & (1 << STM_RCC_CR_HSERDY)))
137 #define STM_RCC_CFGR_SWS_TARGET_CLOCK (STM_RCC_CFGR_SWS_HSE << STM_RCC_CFGR_SWS)
138 #define STM_RCC_CFGR_SW_TARGET_CLOCK (STM_RCC_CFGR_SW_HSE)
139 #define STM_PLLSRC AO_HSE
140 #define STM_RCC_CFGR_PLLSRC_TARGET_CLOCK (1 << STM_RCC_CFGR_PLLSRC)
142 #define STM_HSI 16000000
143 #define STM_RCC_CFGR_SWS_TARGET_CLOCK (STM_RCC_CFGR_SWS_HSI << STM_RCC_CFGR_SWS)
144 #define STM_RCC_CFGR_SW_TARGET_CLOCK (STM_RCC_CFGR_SW_HSI)
145 #define STM_PLLSRC STM_HSI
146 #define STM_RCC_CFGR_PLLSRC_TARGET_CLOCK (0 << STM_RCC_CFGR_PLLSRC)
149 #if !AO_HSE || HAS_ADC
150 /* Enable HSI RC clock 16MHz */
151 stm_rcc.cr |= (1 << STM_RCC_CR_HSION);
152 while (!(stm_rcc.cr & (1 << STM_RCC_CR_HSIRDY)))
156 /* Set flash latency to tolerate 32MHz SYSCLK -> 1 wait state */
158 /* Enable 64-bit access and prefetch */
159 stm_flash.acr |= (1 << STM_FLASH_ACR_ACC64);
160 stm_flash.acr |= (1 << STM_FLASH_ACR_PRFEN);
162 /* Enable 1 wait state so the CPU can run at 32MHz */
163 /* (haven't managed to run the CPU at 32MHz yet, it's at 16MHz) */
164 stm_flash.acr |= (1 << STM_FLASH_ACR_LATENCY);
166 /* Enable power interface clock */
167 stm_rcc.apb1enr |= (1 << STM_RCC_APB1ENR_PWREN);
169 /* Set voltage range to 1.8V */
171 /* poll VOSF bit in PWR_CSR. Wait until it is reset to 0 */
172 while ((stm_pwr.csr & (1 << STM_PWR_CSR_VOSF)) != 0)
175 /* Configure voltage scaling range */
177 cr &= ~(STM_PWR_CR_VOS_MASK << STM_PWR_CR_VOS);
178 cr |= (STM_PWR_CR_VOS_1_8 << STM_PWR_CR_VOS);
181 /* poll VOSF bit in PWR_CSR. Wait until it is reset to 0 */
182 while ((stm_pwr.csr & (1 << STM_PWR_CSR_VOSF)) != 0)
185 /* HCLK to 16MHz -> AHB prescaler = /1 */
187 cfgr &= ~(STM_RCC_CFGR_HPRE_MASK << STM_RCC_CFGR_HPRE);
188 cfgr |= (AO_RCC_CFGR_HPRE_DIV << STM_RCC_CFGR_HPRE);
190 while ((stm_rcc.cfgr & (STM_RCC_CFGR_HPRE_MASK << STM_RCC_CFGR_HPRE)) !=
191 (AO_RCC_CFGR_HPRE_DIV << STM_RCC_CFGR_HPRE))
194 /* APB1 Prescaler = AO_APB1_PRESCALER */
196 cfgr &= ~(STM_RCC_CFGR_PPRE1_MASK << STM_RCC_CFGR_PPRE1);
197 cfgr |= (AO_RCC_CFGR_PPRE1_DIV << STM_RCC_CFGR_PPRE1);
200 /* APB2 Prescaler = AO_APB2_PRESCALER */
202 cfgr &= ~(STM_RCC_CFGR_PPRE2_MASK << STM_RCC_CFGR_PPRE2);
203 cfgr |= (AO_RCC_CFGR_PPRE2_DIV << STM_RCC_CFGR_PPRE2);
206 /* Disable the PLL */
207 stm_rcc.cr &= ~(1 << STM_RCC_CR_PLLON);
208 while (stm_rcc.cr & (1 << STM_RCC_CR_PLLRDY))
211 /* PLLVCO to 96MHz (for USB) -> PLLMUL = 6, PLLDIV = 4 */
213 cfgr &= ~(STM_RCC_CFGR_PLLMUL_MASK << STM_RCC_CFGR_PLLMUL);
214 cfgr &= ~(STM_RCC_CFGR_PLLDIV_MASK << STM_RCC_CFGR_PLLDIV);
216 cfgr |= (AO_RCC_CFGR_PLLMUL << STM_RCC_CFGR_PLLMUL);
217 cfgr |= (AO_RCC_CFGR_PLLDIV << STM_RCC_CFGR_PLLDIV);
220 cfgr &= ~(1 << STM_RCC_CFGR_PLLSRC);
221 cfgr |= STM_RCC_CFGR_PLLSRC_TARGET_CLOCK;
225 /* Enable the PLL and wait for it */
226 stm_rcc.cr |= (1 << STM_RCC_CR_PLLON);
227 while (!(stm_rcc.cr & (1 << STM_RCC_CR_PLLRDY)))
230 /* Switch to the PLL for the system clock */
233 cfgr &= ~(STM_RCC_CFGR_SW_MASK << STM_RCC_CFGR_SW);
234 cfgr |= (STM_RCC_CFGR_SW_PLL << STM_RCC_CFGR_SW);
237 uint32_t c, part, mask, val;
240 mask = (STM_RCC_CFGR_SWS_MASK << STM_RCC_CFGR_SWS);
241 val = (STM_RCC_CFGR_SWS_PLL << STM_RCC_CFGR_SWS);
248 stm_rcc.apb2rstr = 0xffff;
249 stm_rcc.apb1rstr = 0xffff;
250 stm_rcc.ahbrstr = 0x3f;
251 stm_rcc.ahbenr = (1 << STM_RCC_AHBENR_FLITFEN);
255 stm_rcc.apb1rstr = 0;
256 stm_rcc.apb2rstr = 0;
259 /* Clear reset flags */
260 stm_rcc.csr |= (1 << STM_RCC_CSR_RMVF);
263 /* Output SYSCLK on PA8 for measurments */
265 stm_rcc.ahbenr |= (1 << STM_RCC_AHBENR_GPIOAEN);
267 stm_afr_set(&stm_gpioa, 8, STM_AFR_AF0);
268 stm_moder_set(&stm_gpioa, 8, STM_MODER_ALTERNATE);
269 stm_ospeedr_set(&stm_gpioa, 8, STM_OSPEEDR_40MHz);
271 stm_rcc.cfgr |= (STM_RCC_CFGR_MCOPRE_DIV_1 << STM_RCC_CFGR_MCOPRE);
272 stm_rcc.cfgr |= (STM_RCC_CFGR_MCOSEL_HSE << STM_RCC_CFGR_MCOSEL);