2 * Copyright © 2012 Keith Packard <keithp@keithp.com>
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; version 2 of the License.
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
11 * General Public License for more details.
13 * You should have received a copy of the GNU General Public License along
14 * with this program; if not, write to the Free Software Foundation, Inc.,
15 * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
19 #include <ao_cc1120.h>
22 uint8_t ao_radio_done;
23 uint8_t ao_radio_mutex;
24 uint8_t ao_radio_abort;
26 #define CC1120_DEBUG 1
28 uint32_t ao_radio_cal = 1186611;
30 #define ao_radio_select() ao_spi_get_mask(AO_CC1120_SPI_CS_PORT,(1 << AO_CC1120_SPI_CS_PIN),AO_CC1120_SPI_BUS)
31 #define ao_radio_deselect() ao_spi_put_mask(AO_CC1120_SPI_CS_PORT,(1 << AO_CC1120_SPI_CS_PIN),AO_CC1120_SPI_BUS)
32 #define ao_radio_spi_send(d,l) ao_spi_send((d), (l), AO_CC1120_SPI_BUS)
33 #define ao_radio_spi_send_fixed(d,l) ao_spi_send_fixed((d), (l), AO_CC1120_SPI_BUS)
34 #define ao_radio_spi_recv(d,l) ao_spi_recv((d), (l), AO_CC1120_SPI_BUS)
35 #define ao_radio_duplex(o,i,l) ao_spi_duplex((o), (i), (l), AO_CC1120_SPI_BUS)
38 ao_radio_reg_read(uint16_t addr)
44 printf("ao_radio_reg_read (%04x): ", addr); flush();
46 if (CC1120_IS_EXTENDED(addr)) {
47 data[0] = ((1 << CC1120_READ) |
53 data[0] = ((1 << CC1120_READ) |
59 ao_radio_spi_send(data, d);
60 ao_radio_spi_recv(data, 1);
63 printf (" %02x\n", data[0]);
69 ao_radio_reg_write(uint16_t addr, uint8_t value)
75 printf("ao_radio_reg_write (%04x): %02x\n", addr, value);
77 if (CC1120_IS_EXTENDED(addr)) {
78 data[0] = ((1 << CC1120_READ) |
84 data[0] = ((1 << CC1120_READ) |
91 ao_radio_spi_send(data, d+1);
96 ao_radio_strobe(uint8_t addr)
101 ao_radio_duplex(&addr, &in, 1);
107 ao_radio_fifo_read(uint8_t *data, uint8_t len)
109 uint8_t addr = ((1 << CC1120_READ) |
110 (1 << CC1120_BURST) |
115 ao_radio_duplex(&addr, &status, 1);
116 ao_radio_spi_recv(data, len);
122 ao_radio_fifo_write(uint8_t *data, uint8_t len)
124 uint8_t addr = ((0 << CC1120_READ) |
125 (1 << CC1120_BURST) |
130 ao_radio_duplex(&addr, &status, 1);
131 ao_radio_spi_send(data, len);
137 ao_radio_fifo_write_fixed(uint8_t data, uint8_t len)
139 uint8_t addr = ((0 << CC1120_READ) |
140 (1 << CC1120_BURST) |
145 ao_radio_duplex(&addr, &status, 1);
146 ao_radio_spi_send_fixed(data, len);
152 ao_radio_status(void)
154 return ao_radio_strobe (CC1120_SNOP);
158 ao_radio_recv_abort(void)
161 ao_wakeup(&ao_radio_done);
164 #define ao_radio_rdf_value 0x55
166 static const uint16_t rdf_setup[] = {
170 ao_radio_rdf(uint8_t len)
177 for (i = 0; i < sizeof (rdf_setup) / sizeof (rdf_setup[0]); i += 2)
178 ao_radio_reg_write(rdf_setup[i], rdf_setup[i+1]);
179 ao_radio_fifo_write_fixed(ao_radio_rdf_value, len);
180 ao_radio_reg_write(CC1120_IOCFG2, CC1120_IOCFG_GPIO_CFG_RX0TX1_CFG);
181 ao_exti_enable(&AO_CC1120_INT_PORT, AO_CC1120_INT_PIN);
182 ao_radio_strobe(CC1120_STX);
184 while (!ao_radio_done)
185 ao_sleep(&ao_radio_done);
187 ao_radio_set_packet();
192 ao_radio_rdf_abort(void)
202 if (ao_cmd_lex_c != '\n') {
204 mode = (uint8_t) ao_cmd_lex_u32;
207 if ((mode & 2) && !radio_on) {
209 ao_monitor_disable();
212 ao_packet_slave_stop();
215 ao_radio_strobe(CC1120_STX);
219 printf ("Hit a character to stop..."); flush();
223 if ((mode & 1) && radio_on) {
234 ao_radio_send(void *d, uint8_t size)
238 ao_radio_fifo_write(d, size);
239 ao_radio_reg_write(CC1120_IOCFG2, CC1120_IOCFG_GPIO_CFG_RX0TX1_CFG);
240 ao_exti_enable(&AO_CC1120_INT_PORT, AO_CC1120_INT_PIN);
241 ao_radio_strobe(CC1120_STX);
243 while (!ao_radio_done)
244 ao_sleep(&ao_radio_done);
250 ao_radio_recv(__xdata void *d, uint8_t size)
252 /* configure interrupt pin */
255 ao_radio_reg_write(CC1120_IOCFG2, CC1120_IOCFG_GPIO_CFG_RXFIFO_THR_PKT);
256 ao_exti_enable(&AO_CC1120_INT_PORT, AO_CC1120_INT_PIN);
257 ao_radio_strobe(CC1120_SRX);
259 while (!ao_radio_done && !ao_radio_abort)
260 ao_sleep(&ao_radio_done);
263 ao_radio_fifo_read(d, size);
268 static const uint16_t packet_setup[] = {
272 ao_radio_set_packet(void)
276 for (i = 0; i < sizeof (rdf_setup) / sizeof (rdf_setup[0]); i += 2)
277 ao_radio_reg_write(packet_setup[i], packet_setup[i+1]);
284 uint8_t state = ao_radio_strobe(CC1120_SIDLE);
285 if ((state >> CC1120_STATUS_STATE) == CC1120_STATUS_STATE_IDLE)
290 static const uint16_t radio_setup[] = {
291 #include "ao_cc1120_CC1120.h"
294 static uint8_t ao_radio_configured = 0;
299 ao_exti_disable(&AO_CC1120_INT_PORT, AO_CC1120_INT_PIN);
301 ao_wakeup(&ao_radio_done);
309 for (i = 0; i < sizeof (radio_setup) / sizeof (radio_setup[0]); i += 2)
310 ao_radio_reg_write(radio_setup[i], radio_setup[i+1]);
312 /* Disable GPIO2 pin (radio_int) */
313 ao_radio_reg_write(CC1120_IOCFG2, CC1120_IOCFG_GPIO_CFG_HIGHZ);
315 /* Enable the EXTI interrupt for the appropriate pin */
316 ao_enable_port(AO_CC1120_INT_PORT);
317 ao_exti_setup(&AO_CC1120_INT_PORT, AO_CC1120_INT_PIN, AO_EXTI_MODE_RISING, ao_radio_isr);
319 ao_radio_set_packet();
320 ao_radio_configured = 1;
324 ao_radio_get(uint8_t len)
326 ao_mutex_get(&ao_radio_mutex);
327 if (!ao_radio_configured)
329 ao_radio_reg_write(CC1120_PKT_LEN, len);
333 static char *cc1120_state_name[] = {
334 [CC1120_STATUS_STATE_IDLE] = "IDLE",
335 [CC1120_STATUS_STATE_RX] = "RX",
336 [CC1120_STATUS_STATE_TX] = "TX",
337 [CC1120_STATUS_STATE_FSTXON] = "FSTXON",
338 [CC1120_STATUS_STATE_CALIBRATE] = "CALIBRATE",
339 [CC1120_STATUS_STATE_SETTLING] = "SETTLING",
340 [CC1120_STATUS_STATE_RX_FIFO_ERROR] = "RX_FIFO_ERROR",
341 [CC1120_STATUS_STATE_TX_FIFO_ERROR] = "TX_FIFO_ERROR",
344 struct ao_cc1120_reg {
349 const static struct ao_cc1120_reg ao_cc1120_reg[] = {
350 { .addr = CC1120_IOCFG3, .name = "IOCFG3" },
351 { .addr = CC1120_IOCFG2, .name = "IOCFG2" },
352 { .addr = CC1120_IOCFG1, .name = "IOCFG1" },
353 { .addr = CC1120_IOCFG0, .name = "IOCFG0" },
354 { .addr = CC1120_SYNC3, .name = "SYNC3" },
355 { .addr = CC1120_SYNC2, .name = "SYNC2" },
356 { .addr = CC1120_SYNC1, .name = "SYNC1" },
357 { .addr = CC1120_SYNC0, .name = "SYNC0" },
358 { .addr = CC1120_SYNC_CFG1, .name = "SYNC_CFG1" },
359 { .addr = CC1120_SYNC_CFG0, .name = "SYNC_CFG0" },
360 { .addr = CC1120_DEVIATION_M, .name = "DEVIATION_M" },
361 { .addr = CC1120_MODCFG_DEV_E, .name = "MODCFG_DEV_E" },
362 { .addr = CC1120_DCFILT_CFG, .name = "DCFILT_CFG" },
363 { .addr = CC1120_PREAMBLE_CFG1, .name = "PREAMBLE_CFG1" },
364 { .addr = CC1120_PREAMBLE_CFG0, .name = "PREAMBLE_CFG0" },
365 { .addr = CC1120_FREQ_IF_CFG, .name = "FREQ_IF_CFG" },
366 { .addr = CC1120_IQIC, .name = "IQIC" },
367 { .addr = CC1120_CHAN_BW, .name = "CHAN_BW" },
368 { .addr = CC1120_MDMCFG1, .name = "MDMCFG1" },
369 { .addr = CC1120_MDMCFG0, .name = "MDMCFG0" },
370 { .addr = CC1120_DRATE2, .name = "DRATE2" },
371 { .addr = CC1120_DRATE1, .name = "DRATE1" },
372 { .addr = CC1120_DRATE0, .name = "DRATE0" },
373 { .addr = CC1120_AGC_REF, .name = "AGC_REF" },
374 { .addr = CC1120_AGC_CS_THR, .name = "AGC_CS_THR" },
375 { .addr = CC1120_AGC_GAIN_ADJUST, .name = "AGC_GAIN_ADJUST" },
376 { .addr = CC1120_AGC_CFG3, .name = "AGC_CFG3" },
377 { .addr = CC1120_AGC_CFG2, .name = "AGC_CFG2" },
378 { .addr = CC1120_AGC_CFG1, .name = "AGC_CFG1" },
379 { .addr = CC1120_AGC_CFG0, .name = "AGC_CFG0" },
380 { .addr = CC1120_FIFO_CFG, .name = "FIFO_CFG" },
381 { .addr = CC1120_DEV_ADDR, .name = "DEV_ADDR" },
382 { .addr = CC1120_SETTLING_CFG, .name = "SETTLING_CFG" },
383 { .addr = CC1120_FS_CFG, .name = "FS_CFG" },
384 { .addr = CC1120_WOR_CFG1, .name = "WOR_CFG1" },
385 { .addr = CC1120_WOR_CFG0, .name = "WOR_CFG0" },
386 { .addr = CC1120_WOR_EVENT0_MSB, .name = "WOR_EVENT0_MSB" },
387 { .addr = CC1120_WOR_EVENT0_LSB, .name = "WOR_EVENT0_LSB" },
388 { .addr = CC1120_PKT_CFG2, .name = "PKT_CFG2" },
389 { .addr = CC1120_PKT_CFG1, .name = "PKT_CFG1" },
390 { .addr = CC1120_PKT_CFG0, .name = "PKT_CFG0" },
391 { .addr = CC1120_RFEND_CFG1, .name = "RFEND_CFG1" },
392 { .addr = CC1120_RFEND_CFG0, .name = "RFEND_CFG0" },
393 { .addr = CC1120_PA_CFG2, .name = "PA_CFG2" },
394 { .addr = CC1120_PA_CFG1, .name = "PA_CFG1" },
395 { .addr = CC1120_PA_CFG0, .name = "PA_CFG0" },
396 { .addr = CC1120_PKT_LEN, .name = "PKT_LEN" },
397 { .addr = CC1120_IF_MIX_CFG, .name = "IF_MIX_CFG" },
398 { .addr = CC1120_FREQOFF_CFG, .name = "FREQOFF_CFG" },
399 { .addr = CC1120_TOC_CFG, .name = "TOC_CFG" },
400 { .addr = CC1120_MARC_SPARE, .name = "MARC_SPARE" },
401 { .addr = CC1120_ECG_CFG, .name = "ECG_CFG" },
402 { .addr = CC1120_SOFT_TX_DATA_CFG, .name = "SOFT_TX_DATA_CFG" },
403 { .addr = CC1120_EXT_CTRL, .name = "EXT_CTRL" },
404 { .addr = CC1120_RCCAL_FINE, .name = "RCCAL_FINE" },
405 { .addr = CC1120_RCCAL_COARSE, .name = "RCCAL_COARSE" },
406 { .addr = CC1120_RCCAL_OFFSET, .name = "RCCAL_OFFSET" },
407 { .addr = CC1120_FREQOFF1, .name = "FREQOFF1" },
408 { .addr = CC1120_FREQOFF0, .name = "FREQOFF0" },
409 { .addr = CC1120_FREQ2, .name = "FREQ2" },
410 { .addr = CC1120_FREQ1, .name = "FREQ1" },
411 { .addr = CC1120_FREQ0, .name = "FREQ0" },
412 { .addr = CC1120_IF_ADC2, .name = "IF_ADC2" },
413 { .addr = CC1120_IF_ADC1, .name = "IF_ADC1" },
414 { .addr = CC1120_IF_ADC0, .name = "IF_ADC0" },
415 { .addr = CC1120_FS_DIG1, .name = "FS_DIG1" },
416 { .addr = CC1120_FS_DIG0, .name = "FS_DIG0" },
417 { .addr = CC1120_FS_CAL3, .name = "FS_CAL3" },
418 { .addr = CC1120_FS_CAL2, .name = "FS_CAL2" },
419 { .addr = CC1120_FS_CAL1, .name = "FS_CAL1" },
420 { .addr = CC1120_FS_CAL0, .name = "FS_CAL0" },
421 { .addr = CC1120_FS_CHP, .name = "FS_CHP" },
422 { .addr = CC1120_FS_DIVTWO, .name = "FS_DIVTWO" },
423 { .addr = CC1120_FS_DSM1, .name = "FS_DSM1" },
424 { .addr = CC1120_FS_DSM0, .name = "FS_DSM0" },
425 { .addr = CC1120_FS_DVC1, .name = "FS_DVC1" },
426 { .addr = CC1120_FS_DVC0, .name = "FS_DVC0" },
427 { .addr = CC1120_FS_LBI, .name = "FS_LBI" },
428 { .addr = CC1120_FS_PFD, .name = "FS_PFD" },
429 { .addr = CC1120_FS_PRE, .name = "FS_PRE" },
430 { .addr = CC1120_FS_REG_DIV_CML, .name = "FS_REG_DIV_CML" },
431 { .addr = CC1120_FS_SPARE, .name = "FS_SPARE" },
432 { .addr = CC1120_FS_VCO4, .name = "FS_VCO4" },
433 { .addr = CC1120_FS_VCO3, .name = "FS_VCO3" },
434 { .addr = CC1120_FS_VCO2, .name = "FS_VCO2" },
435 { .addr = CC1120_FS_VCO1, .name = "FS_VCO1" },
436 { .addr = CC1120_FS_VCO0, .name = "FS_VCO0" },
437 { .addr = CC1120_GBIAS6, .name = "GBIAS6" },
438 { .addr = CC1120_GBIAS5, .name = "GBIAS5" },
439 { .addr = CC1120_GBIAS4, .name = "GBIAS4" },
440 { .addr = CC1120_GBIAS3, .name = "GBIAS3" },
441 { .addr = CC1120_GBIAS2, .name = "GBIAS2" },
442 { .addr = CC1120_GBIAS1, .name = "GBIAS1" },
443 { .addr = CC1120_GBIAS0, .name = "GBIAS0" },
444 { .addr = CC1120_IFAMP, .name = "IFAMP" },
445 { .addr = CC1120_LNA, .name = "LNA" },
446 { .addr = CC1120_RXMIX, .name = "RXMIX" },
447 { .addr = CC1120_XOSC5, .name = "XOSC5" },
448 { .addr = CC1120_XOSC4, .name = "XOSC4" },
449 { .addr = CC1120_XOSC3, .name = "XOSC3" },
450 { .addr = CC1120_XOSC2, .name = "XOSC2" },
451 { .addr = CC1120_XOSC1, .name = "XOSC1" },
452 { .addr = CC1120_XOSC0, .name = "XOSC0" },
453 { .addr = CC1120_ANALOG_SPARE, .name = "ANALOG_SPARE" },
454 { .addr = CC1120_PA_CFG3, .name = "PA_CFG3" },
455 { .addr = CC1120_WOR_TIME1, .name = "WOR_TIME1" },
456 { .addr = CC1120_WOR_TIME0, .name = "WOR_TIME0" },
457 { .addr = CC1120_WOR_CAPTURE1, .name = "WOR_CAPTURE1" },
458 { .addr = CC1120_WOR_CAPTURE0, .name = "WOR_CAPTURE0" },
459 { .addr = CC1120_BIST, .name = "BIST" },
460 { .addr = CC1120_DCFILTOFFSET_I1, .name = "DCFILTOFFSET_I1" },
461 { .addr = CC1120_DCFILTOFFSET_I0, .name = "DCFILTOFFSET_I0" },
462 { .addr = CC1120_DCFILTOFFSET_Q1, .name = "DCFILTOFFSET_Q1" },
463 { .addr = CC1120_DCFILTOFFSET_Q0, .name = "DCFILTOFFSET_Q0" },
464 { .addr = CC1120_IQIE_I1, .name = "IQIE_I1" },
465 { .addr = CC1120_IQIE_I0, .name = "IQIE_I0" },
466 { .addr = CC1120_IQIE_Q1, .name = "IQIE_Q1" },
467 { .addr = CC1120_IQIE_Q0, .name = "IQIE_Q0" },
468 { .addr = CC1120_RSSI1, .name = "RSSI1" },
469 { .addr = CC1120_RSSI0, .name = "RSSI0" },
470 { .addr = CC1120_MARCSTATE, .name = "MARCSTATE" },
471 { .addr = CC1120_LQI_VAL, .name = "LQI_VAL" },
472 { .addr = CC1120_PQT_SYNC_ERR, .name = "PQT_SYNC_ERR" },
473 { .addr = CC1120_DEM_STATUS, .name = "DEM_STATUS" },
474 { .addr = CC1120_FREQOFF_EST1, .name = "FREQOFF_EST1" },
475 { .addr = CC1120_FREQOFF_EST0, .name = "FREQOFF_EST0" },
476 { .addr = CC1120_AGC_GAIN3, .name = "AGC_GAIN3" },
477 { .addr = CC1120_AGC_GAIN2, .name = "AGC_GAIN2" },
478 { .addr = CC1120_AGC_GAIN1, .name = "AGC_GAIN1" },
479 { .addr = CC1120_AGC_GAIN0, .name = "AGC_GAIN0" },
480 { .addr = CC1120_SOFT_RX_DATA_OUT, .name = "SOFT_RX_DATA_OUT" },
481 { .addr = CC1120_SOFT_TX_DATA_IN, .name = "SOFT_TX_DATA_IN" },
482 { .addr = CC1120_ASK_SOFT_RX_DATA, .name = "ASK_SOFT_RX_DATA" },
483 { .addr = CC1120_RNDGEN, .name = "RNDGEN" },
484 { .addr = CC1120_MAGN2, .name = "MAGN2" },
485 { .addr = CC1120_MAGN1, .name = "MAGN1" },
486 { .addr = CC1120_MAGN0, .name = "MAGN0" },
487 { .addr = CC1120_ANG1, .name = "ANG1" },
488 { .addr = CC1120_ANG0, .name = "ANG0" },
489 { .addr = CC1120_CHFILT_I2, .name = "CHFILT_I2" },
490 { .addr = CC1120_CHFILT_I1, .name = "CHFILT_I1" },
491 { .addr = CC1120_CHFILT_I0, .name = "CHFILT_I0" },
492 { .addr = CC1120_CHFILT_Q2, .name = "CHFILT_Q2" },
493 { .addr = CC1120_CHFILT_Q1, .name = "CHFILT_Q1" },
494 { .addr = CC1120_CHFILT_Q0, .name = "CHFILT_Q0" },
495 { .addr = CC1120_GPIO_STATUS, .name = "GPIO_STATUS" },
496 { .addr = CC1120_FSCAL_CTRL, .name = "FSCAL_CTRL" },
497 { .addr = CC1120_PHASE_ADJUST, .name = "PHASE_ADJUST" },
498 { .addr = CC1120_PARTNUMBER, .name = "PARTNUMBER" },
499 { .addr = CC1120_PARTVERSION, .name = "PARTVERSION" },
500 { .addr = CC1120_SERIAL_STATUS, .name = "SERIAL_STATUS" },
501 { .addr = CC1120_RX_STATUS, .name = "RX_STATUS" },
502 { .addr = CC1120_TX_STATUS, .name = "TX_STATUS" },
503 { .addr = CC1120_MARC_STATUS1, .name = "MARC_STATUS1" },
504 { .addr = CC1120_MARC_STATUS0, .name = "MARC_STATUS0" },
505 { .addr = CC1120_PA_IFAMP_TEST, .name = "PA_IFAMP_TEST" },
506 { .addr = CC1120_FSRF_TEST, .name = "FSRF_TEST" },
507 { .addr = CC1120_PRE_TEST, .name = "PRE_TEST" },
508 { .addr = CC1120_PRE_OVR, .name = "PRE_OVR" },
509 { .addr = CC1120_ADC_TEST, .name = "ADC_TEST" },
510 { .addr = CC1120_DVC_TEST, .name = "DVC_TEST" },
511 { .addr = CC1120_ATEST, .name = "ATEST" },
512 { .addr = CC1120_ATEST_LVDS, .name = "ATEST_LVDS" },
513 { .addr = CC1120_ATEST_MODE, .name = "ATEST_MODE" },
514 { .addr = CC1120_XOSC_TEST1, .name = "XOSC_TEST1" },
515 { .addr = CC1120_XOSC_TEST0, .name = "XOSC_TEST0" },
516 { .addr = CC1120_RXFIRST, .name = "RXFIRST" },
517 { .addr = CC1120_TXFIRST, .name = "TXFIRST" },
518 { .addr = CC1120_RXLAST, .name = "RXLAST" },
519 { .addr = CC1120_TXLAST, .name = "TXLAST" },
520 { .addr = CC1120_NUM_TXBYTES, .name = "NUM_TXBYTES" },
521 { .addr = CC1120_NUM_RXBYTES, .name = "NUM_RXBYTES" },
522 { .addr = CC1120_FIFO_NUM_TXBYTES, .name = "FIFO_NUM_TXBYTES" },
523 { .addr = CC1120_FIFO_NUM_RXBYTES, .name = "FIFO_NUM_RXBYTES" },
526 #define AO_NUM_CC1120_REG (sizeof ao_cc1120_reg / sizeof ao_cc1120_reg[0])
528 static void ao_radio_show(void) {
529 uint8_t status = ao_radio_status();
533 status = ao_radio_status();
534 printf ("Status: %02x\n", status);
535 printf ("CHIP_RDY: %d\n", (status >> CC1120_STATUS_CHIP_RDY) & 1);
536 printf ("STATE: %s\n", cc1120_state_name[(status >> CC1120_STATUS_STATE) & CC1120_STATUS_STATE_MASK]);
538 for (i = 0; i < AO_NUM_CC1120_REG; i++)
539 printf ("\t%02x %-20.20s\n", ao_radio_reg_read(ao_cc1120_reg[i].addr), ao_cc1120_reg[i].name);
544 static const struct ao_cmds ao_radio_cmds[] = {
545 { ao_radio_test, "C <1 start, 0 stop, none both>\0Radio carrier test" },
547 { ao_radio_show, "R\0Show CC1120 status" },
555 ao_radio_configured = 0;
556 ao_spi_init_cs (AO_CC1120_SPI_CS_PORT, (1 << AO_CC1120_SPI_CS_PIN));
558 ao_cmd_register(&ao_radio_cmds[0]);