Add 3.3V regulator and USB cable connector

Avoids need for external 3.3V regulator

Signed-off-by: Keith Packard <keithp@keithp.com>

diff --git a/mppogo.pcb b/mppogo.pcb
index 50df16fa42d0ddea0ea24ad51783bb5a5bc16477..e0e9f4bf85202a11c488a17b85cfe6d60c0d7f43 100644 (file)
--- a/mppogo.pcb
+++ b/mppogo.pcb
@@ -10,7 +10,7 @@ Cursor[0.0000 0.0000 0.000000]
 PolyArea[200000000.000000]
 Thermal[0.500000]
 DRC[5.00mil 10.00mil 5.00mil 5.00mil 15.00mil 6.50mil]
-Flags("showdrc,nameonpcb,uniquename,clearnew")
+Flags("showdrc,nameonpcb,uniquename,clearnew,snappin")
 Groups("1,c:2,s:3")
 Styles["Signal,10.00mil,36.00mil,20.00mil,10.00mil:Power,25.00mil,60.00mil,35.00mil,10.00mil:Fat,40.00mil,60.00mil,35.00mil,10.00mil:Skinny,6.00mil,24.02mil,11.81mil,6.00mil"]
 
@@ -892,14 +892,49 @@ Element["" "hole-200" "H1" "unknown" 300.00mil 300.00mil 0.0000 0.0000 0 100 ""]
 
        )
 
-Element["" "100mil2pin" "J2" "unknown" 650.00mil 80.00mil -550.00mil 20.00mil 0 100 ""]
+Element["" "CK05_type_Capacitor" "C2" "0.1uF" 850.00mil 60.00mil 50.00mil 130.00mil 1 150 ""]
+(
+       Pin[0.0000 0.0000 80.00mil 30.00mil 110.00mil 35.00mil "1" "1" "thermal(5)"]
+       Pin[0.0000 200.00mil 80.00mil 30.00mil 110.00mil 35.00mil "2" "2" "thermal(4)"]
+       ElementLine [-50.00mil 0.0000 -45.00mil 0.0000 10.00mil]
+       ElementLine [-50.00mil 0.0000 -50.00mil 200.00mil 10.00mil]
+       ElementLine [-50.00mil 200.00mil -45.00mil 200.00mil 10.00mil]
+       ElementLine [45.00mil 200.00mil 50.00mil 200.00mil 10.00mil]
+       ElementLine [50.00mil 0.0000 50.00mil 200.00mil 10.00mil]
+       ElementLine [45.00mil 0.0000 50.00mil 0.0000 10.00mil]
+
+       )
+
+Element["" "CK05_type_Capacitor" "C1" "0.33uF" 450.00mil 60.00mil -140.00mil 130.00mil 1 150 ""]
+(
+       Pin[0.0000 0.0000 80.00mil 30.00mil 110.00mil 35.00mil "1" "1" "thermal(5)"]
+       Pin[0.0000 200.00mil 80.00mil 30.00mil 110.00mil 35.00mil "2" "2" "thermal(4)"]
+       ElementLine [-50.00mil 0.0000 -45.00mil 0.0000 10.00mil]
+       ElementLine [-50.00mil 0.0000 -50.00mil 200.00mil 10.00mil]
+       ElementLine [-50.00mil 200.00mil -45.00mil 200.00mil 10.00mil]
+       ElementLine [45.00mil 200.00mil 50.00mil 200.00mil 10.00mil]
+       ElementLine [50.00mil 0.0000 50.00mil 200.00mil 10.00mil]
+       ElementLine [45.00mil 0.0000 50.00mil 0.0000 10.00mil]
+
+       )
+
+Element["" "TO92" "U1" "L78Lxx" 550.00mil 120.00mil 10.00mil -130.00mil 0 100 ""]
+(
+       Pin[200.00mil 0.0000 72.00mil 30.00mil 78.00mil 42.00mil "1" "1" "square,edge2"]
+       Pin[100.00mil 0.0000 72.00mil 30.00mil 78.00mil 42.00mil "2" "2" "edge2"]
+       Pin[0.0000 0.0000 72.00mil 30.00mil 78.00mil 42.00mil "3" "3" "edge2"]
+       ElementLine [30.00mil -70.00mil 170.00mil -70.00mil 10.00mil]
+       ElementArc [100.00mil 0.0000 100.00mil 100.00mil 315 270 10.00mil]
+
+       )
+
+Element["" "usbcable" "J2" "unknown" 70.00mil 430.00mil 0.30mil 1.25mil 3 100 ""]
 (
-       Pin[-50.00mil 0.0000 70.00mil 15.00mil 85.00mil 38.00mil "1" "1" "square,edge2"]
-       Pin[50.00mil 0.0000 70.00mil 15.00mil 85.00mil 38.00mil "2" "2" "edge2"]
-       ElementLine [100.00mil -50.00mil -100.00mil -50.00mil 10.00mil]
-       ElementLine [-100.00mil -50.00mil -100.00mil 50.00mil 10.00mil]
-       ElementLine [-100.00mil 50.00mil 100.00mil 50.00mil 10.00mil]
-       ElementLine [100.00mil 50.00mil 100.00mil -50.00mil 10.00mil]
+       Pin[0.0000 0.0000 62.50mil 30.00mil 68.50mil 38.00mil "1" "1" "square"]
+       Pin[0.0000 75.00mil 62.50mil 30.00mil 68.50mil 38.00mil "2" "2" ""]
+       Pin[0.0000 150.00mil 62.50mil 30.00mil 68.50mil 38.00mil "3" "3" ""]
+       Pin[0.0000 225.00mil 62.50mil 30.00mil 68.50mil 38.00mil "4" "4" ""]
+       Pin[0.0000 315.00mil 87.00mil 30.00mil 93.00mil 62.50mil "5" "5" ""]
 
        )
 Layer(1 "component")
@@ -922,13 +957,29 @@ Layer(1 "component")
        Line[534.00mil 329.00mil 930.00mil 725.00mil 10.00mil 20.00mil "clearline"]
        Line[930.00mil 725.00mil 29.8201mm 725.00mil 10.00mil 20.00mil "clearline"]
        Line[29.8201mm 725.00mil 31.0397mm 17.1954mm 10.00mil 20.00mil "clearline"]
-       Line[14.7357mm 330.00mil 14.7357mm 2.5363mm 10.00mil 20.00mil "clearline"]
-       Line[14.7357mm 2.5363mm 600.00mil 80.00mil 10.00mil 20.00mil "clearline"]
-       Line[768.12mil 329.00mil 768.12mil 148.12mil 10.00mil 20.00mil "clearline"]
-       Line[768.12mil 148.12mil 700.00mil 80.00mil 10.00mil 20.00mil "clearline"]
+       Line[70.00mil 430.00mil 350.00mil 430.00mil 25.00mil 20.00mil "clearline"]
+       Line[350.00mil 430.00mil 450.00mil 330.00mil 25.00mil 20.00mil "clearline"]
+       Line[450.00mil 330.00mil 450.00mil 260.00mil 25.00mil 20.00mil "clearline"]
+       Line[550.00mil 120.00mil 550.00mil 160.00mil 25.00mil 20.00mil "clearline"]
+       Line[550.00mil 160.00mil 450.00mil 260.00mil 25.00mil 20.00mil "clearline"]
+       Line[750.00mil 120.00mil 750.00mil 160.00mil 25.00mil 20.00mil "clearline"]
+       Line[750.00mil 160.00mil 850.00mil 260.00mil 25.00mil 20.00mil "clearline"]
+       Line[14.7103mm 329.00mil 14.7103mm 7.3877mm 25.00mil 20.00mil "clearline"]
+       Line[14.7103mm 7.3877mm 750.00mil 120.00mil 25.00mil 20.00mil "clearline"]
 )
 Layer(2 "solder")
 (
+       Line[768.12mil 329.00mil 768.12mil 361.88mil 25.00mil 20.00mil "clearline"]
+       Line[768.12mil 361.88mil 410.00mil 720.00mil 25.00mil 20.00mil "clearline"]
+       Line[410.00mil 720.00mil 95.00mil 720.00mil 25.00mil 20.00mil "clearline"]
+       Line[95.00mil 720.00mil 70.00mil 745.00mil 25.00mil 20.00mil "clearline"]
+       Line[768.12mil 328.12mil 768.12mil 298.12mil 25.00mil 20.00mil "clearline"]
+       Line[768.12mil 298.12mil 650.00mil 180.00mil 25.00mil 20.00mil "clearline"]
+       Line[650.00mil 180.00mil 650.00mil 120.00mil 25.00mil 20.00mil "clearline"]
+       Line[850.00mil 60.00mil 710.00mil 60.00mil 25.00mil 20.00mil "clearline"]
+       Line[710.00mil 60.00mil 650.00mil 120.00mil 25.00mil 20.00mil "clearline"]
+       Line[450.00mil 60.00mil 590.00mil 60.00mil 25.00mil 20.00mil "clearline"]
+       Line[590.00mil 60.00mil 650.00mil 120.00mil 25.00mil 20.00mil "clearline"]
 )
 Layer(3 "outline")
 (
@@ -951,16 +1002,15 @@ Layer(5 "silk")
        Line[670.00mil 810.00mil 1000.00mil 810.00mil 10.00mil 20.00mil "clearline"]
        Line[570.00mil 860.00mil 570.00mil 810.00mil 10.00mil 20.00mil "clearline"]
        Line[570.00mil 810.00mil 300.00mil 810.00mil 10.00mil 20.00mil "clearline"]
-       Text[390.00mil 50.00mil 0 100 "+3.3V" "clearline"]
-       Text[780.00mil 50.00mil 0 100 "GND" "clearline"]
 )
 NetList()
 (
        Net("+3.3V" "(unknown)")
        (
+               Connect("C2-2")
                Connect("J1-2")
-               Connect("J2-1")
                Connect("T2-1")
+               Connect("U1-1")
        )
        Net("\\_reset\\_" "(unknown)")
        (
@@ -972,11 +1022,14 @@ NetList()
                Connect("J1-3")
                Connect("T3-1")
        )
-       Net("gnd" "(unknown)")
+       Net("GND" "(unknown)")
        (
+               Connect("C1-1")
+               Connect("C2-1")
                Connect("J1-6")
-               Connect("J2-2")
+               Connect("J2-5")
                Connect("T6-1")
+               Connect("U1-2")
        )
        Net("miso" "(unknown)")
        (
@@ -990,30 +1043,52 @@ NetList()
        )
        Net("unnamed_net1" "(unknown)")
        (
-               Connect("H3-1")
+               Connect("H1-1")
        )
        Net("unnamed_net2" "(unknown)")
        (
-               Connect("H4-1")
+               Connect("H3-1")
        )
        Net("unnamed_net3" "(unknown)")
        (
-               Connect("H2-1")
+               Connect("H4-1")
        )
        Net("unnamed_net4" "(unknown)")
        (
-               Connect("H5-1")
+               Connect("H2-1")
        )
        Net("unnamed_net5" "(unknown)")
        (
-               Connect("H7-1")
+               Connect("H5-1")
        )
        Net("unnamed_net6" "(unknown)")
        (
-               Connect("H8-1")
+               Connect("H7-1")
        )
        Net("unnamed_net7" "(unknown)")
+       (
+               Connect("H8-1")
+       )
+       Net("unnamed_net8" "(unknown)")
        (
                Connect("H6-1")
        )
+       Net("unnamed_net9" "(unknown)")
+       (
+               Connect("C1-2")
+               Connect("J2-1")
+               Connect("U1-3")
+       )
+       Net("unnamed_net10" "(unknown)")
+       (
+               Connect("J2-2")
+       )
+       Net("unnamed_net11" "(unknown)")
+       (
+               Connect("J2-3")
+       )
+       Net("unnamed_net12" "(unknown)")
+       (
+               Connect("J2-4")
+       )
 )

diff --git a/mppogo.sch b/mppogo.sch
index f52883b20b50baf61198f25cea511e5295a372c8..0e53940b23cf0b19c15e46a02471a32f062b68b2 100644 (file)
--- a/mppogo.sch
+++ b/mppogo.sch
@@ -122,22 +122,22 @@ refdes=H3
 T 47800 48200 5 10 0 0 0 0 1
 footprint=hole-200
 }
-C 47800 43200 1 0 0 hole-1.sym
+C 47800 45700 1 0 0 hole-1.sym
 {
-T 47800 43200 5 10 0 1 0 0 1
+T 47800 45700 5 10 0 1 0 0 1
 device=HOLE
-T 48000 43800 5 10 1 1 0 4 1
+T 48000 46300 5 10 1 1 0 4 1
 refdes=H4
-T 47800 43200 5 10 0 0 0 0 1
+T 47800 45700 5 10 0 0 0 0 1
 footprint=hole-200
 }
-C 42300 43200 1 0 0 hole-1.sym
+C 42300 45700 1 0 0 hole-1.sym
 {
-T 42300 43200 5 10 0 1 0 0 1
+T 42300 45700 5 10 0 1 0 0 1
 device=HOLE
-T 42500 43800 5 10 1 1 0 4 1
+T 42500 46300 5 10 1 1 0 4 1
 refdes=H2
-T 42300 43200 5 10 0 0 0 0 1
+T 42300 45700 5 10 0 0 0 0 1
 footprint=hole-200
 }
 C 41800 49200 1 0 0 hole-1.sym
@@ -158,22 +158,22 @@ refdes=H7
 T 48800 49200 5 10 0 0 0 0 1
 footprint=hole-M3
 }
-C 48800 42200 1 0 0 hole-1.sym
+C 48800 44700 1 0 0 hole-1.sym
 {
-T 48800 42200 5 10 0 1 0 0 1
+T 48800 44700 5 10 0 1 0 0 1
 device=HOLE
-T 49000 42800 5 10 1 1 0 4 1
+T 49000 45300 5 10 1 1 0 4 1
 refdes=H8
-T 48800 42200 5 10 0 0 0 0 1
+T 48800 44700 5 10 0 0 0 0 1
 footprint=hole-M3
 }
-C 41300 42200 1 0 0 hole-1.sym
+C 41300 44700 1 0 0 hole-1.sym
 {
-T 41300 42200 5 10 0 1 0 0 1
+T 41300 44700 5 10 0 1 0 0 1
 device=HOLE
-T 41500 42800 5 10 1 1 0 4 1
+T 41500 45300 5 10 1 1 0 4 1
 refdes=H6
-T 41300 42200 5 10 0 0 0 0 1
+T 41300 44700 5 10 0 0 0 0 1
 footprint=hole-M3
 }
 C 41800 48800 1 0 0 nc-bottom-1.sym
@@ -183,11 +183,11 @@ value=NoConnection
 T 41800 49800 5 10 0 0 0 0 1
 device=DRC_Directive
 }
-C 42300 47850 1 0 0 nc-bottom-1.sym
+C 42300 47800 1 0 0 nc-bottom-1.sym
 {
-T 42300 48450 5 10 0 0 0 0 1
+T 42300 48400 5 10 0 0 0 0 1
 value=NoConnection
-T 42300 48850 5 10 0 0 0 0 1
+T 42300 48800 5 10 0 0 0 0 1
 device=DRC_Directive
 }
 C 47800 47800 1 0 0 nc-bottom-1.sym
@@ -204,48 +204,115 @@ value=NoConnection
 T 48800 49800 5 10 0 0 0 0 1
 device=DRC_Directive
 }
-C 48800 41800 1 0 0 nc-bottom-1.sym
+C 48800 44300 1 0 0 nc-bottom-1.sym
 {
-T 48800 42400 5 10 0 0 0 0 1
+T 48800 44900 5 10 0 0 0 0 1
 value=NoConnection
-T 48800 42800 5 10 0 0 0 0 1
+T 48800 45300 5 10 0 0 0 0 1
 device=DRC_Directive
 }
-C 47800 42800 1 0 0 nc-bottom-1.sym
+C 47800 45300 1 0 0 nc-bottom-1.sym
 {
-T 47800 43400 5 10 0 0 0 0 1
+T 47800 45900 5 10 0 0 0 0 1
 value=NoConnection
-T 47800 43800 5 10 0 0 0 0 1
+T 47800 46300 5 10 0 0 0 0 1
 device=DRC_Directive
 }
-C 42300 42800 1 0 0 nc-bottom-1.sym
+C 42300 45300 1 0 0 nc-bottom-1.sym
 {
-T 42300 43400 5 10 0 0 0 0 1
+T 42300 45900 5 10 0 0 0 0 1
 value=NoConnection
-T 42300 43800 5 10 0 0 0 0 1
+T 42300 46300 5 10 0 0 0 0 1
 device=DRC_Directive
 }
-C 41300 41800 1 0 0 nc-bottom-1.sym
+C 41300 44300 1 0 0 nc-bottom-1.sym
 {
-T 41300 42400 5 10 0 0 0 0 1
+T 41300 44900 5 10 0 0 0 0 1
 value=NoConnection
-T 41300 42800 5 10 0 0 0 0 1
+T 41300 45300 5 10 0 0 0 0 1
 device=DRC_Directive
 }
-C 49850 45400 1 0 1 connector2-1.sym
+C 42700 41200 1 0 1 miniUSB.sym
 {
-T 49650 46400 5 10 0 0 0 6 1
-device=CONNECTOR_2
-T 49550 46200 5 10 1 1 0 6 1
+T 42405 43600 5 10 1 1 0 6 1
 refdes=J2
-T 49850 45400 5 10 0 0 0 0 1
-footprint=100mil2pin
-}
-N 46500 46500 46500 46250 4
-N 46500 46250 48000 46250 4
-N 48000 46250 48000 45900 4
-N 48000 45900 48150 45900 4
-N 46500 44500 46500 44250 4
-N 46500 44250 48000 44250 4
-N 48000 44250 48000 45600 4
-N 48000 45600 48150 45600 4
+T 42345 41595 5 10 0 1 0 6 1
+footprint=usbcable
+}
+C 44000 42500 1 0 0 LC78Lxx.sym
+{
+T 44295 43495 5 10 1 1 0 0 1
+refdes=U1
+T 44895 43495 5 10 1 1 0 0 1
+value=L78Lxx
+T 43995 42495 5 10 0 1 0 0 1
+device=IC
+T 44895 43495 5 10 0 1 0 0 1
+footprint=TO92
+}
+C 43700 42300 1 90 0 capacitor-1.sym
+{
+T 43000 42500 5 10 0 0 90 0 1
+device=CAPACITOR
+T 43600 42900 5 10 1 1 0 0 1
+refdes=C1
+T 42800 42500 5 10 0 0 90 0 1
+symversion=0.1
+T 43600 42500 5 10 1 1 0 0 1
+value=0.33uF
+T 43700 42300 5 10 0 1 0 0 1
+footprint=CK05_type_Capacitor
+T 43700 42300 5 10 0 1 0 0 1
+loadstatus=throughhole
+T 43700 42300 5 10 0 1 0 0 1
+vendor=digikey
+}
+C 46700 42300 1 90 0 capacitor-1.sym
+{
+T 46000 42500 5 10 0 0 90 0 1
+device=CAPACITOR
+T 46600 42900 5 10 1 1 0 0 1
+refdes=C2
+T 45800 42500 5 10 0 0 90 0 1
+symversion=0.1
+T 46700 42300 5 10 0 1 0 0 1
+vendor=digikey
+T 46700 42300 5 10 0 1 0 0 1
+loadstatus=throughhole
+T 46600 42500 5 10 1 1 0 0 1
+value=0.1uF
+T 46700 42300 5 10 0 1 0 0 1
+footprint=CK05_type_Capacitor
+}
+N 42700 43200 44000 43200 4
+N 46000 43200 47000 43200 4
+{
+T 46500 43300 5 10 1 1 0 0 1
+netname=+3.3V
+}
+C 42600 41300 1 0 0 gnd-1.sym
+N 43500 42300 46500 42300 4
+N 45000 42500 45000 42300 4
+C 44900 42000 1 0 0 gnd-1.sym
+C 42700 42700 1 0 0 nc-right-1.sym
+{
+T 42800 43200 5 10 0 0 0 0 1
+value=NoConnection
+T 42800 43400 5 10 0 0 0 0 1
+device=DRC_Directive
+}
+C 42700 42300 1 0 0 nc-right-1.sym
+{
+T 42800 42800 5 10 0 0 0 0 1
+value=NoConnection
+T 42800 43000 5 10 0 0 0 0 1
+device=DRC_Directive
+}
+C 42700 41900 1 0 0 nc-right-1.sym
+{
+T 42800 42400 5 10 0 0 0 0 1
+value=NoConnection
+T 42800 42600 5 10 0 0 0 0 1
+device=DRC_Directive
+}
+C 46075 44200 1 0 0 gnd-1.sym

diff --git a/packages/TO92.fp b/packages/TO92.fp
new file mode 100644 (file)
index 0000000..324bf90
--- /dev/null
+++ b/packages/TO92.fp
@@ -0,0 +1,8 @@
+Element[0x0 "TO92" "" "" 0 0 0 0 0 100 0x0]
+(
+   Pin[-5000 0 4000 600 5000 2500 "" "1" 0x01]
+   Pin[0 0 4000 600 5000 2500 "" "2" 0x01]
+   Pin[5000 0 4000 600 5000 2500 "" "3" 0x01]
+   ElementLine(76 52 -76 52 10)
+   ElementArc(0 0 92 92 146 248 10)
+)

diff --git a/packages/usbcable.fp b/packages/usbcable.fp
new file mode 100644 (file)
index 0000000..b779134
--- /dev/null
+++ b/packages/usbcable.fp
@@ -0,0 +1,10 @@
+# USB Cable, Molex 0887283400
+Element[0x00000000 "USB Cable" "J0" "" 0 0 125 -30 0 100 0x00000000]
+(
+# Pin args:  X Y Thickness Clearance Mask DrillHole
+       Pin[    0 0 6250 3000 6850 3800 "1" "1" 0x04000101]
+       Pin[ 7500 0 6250 3000 6850 3800 "2" "2" 0x04000001]
+       Pin[15000 0 6250 3000 6850 3800 "3" "3" 0x04000001]
+       Pin[22500 0 6250 3000 6850 3800 "4" "4" 0x04000001]
+       Pin[31500 0 8700 3000 9300 6250 "5" "5" 0x04000001]
+)

diff --git a/partslist.dk b/partslist.dk
index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..03d49d4036fa9ed630862b578ef60b541046302f 100644 (file)
--- a/partslist.dk
+++ b/partslist.dk
@@ -0,0 +1,2 @@
+1, unknown, CAPACITOR 0.1uF
+1, unknown, CAPACITOR 0.33uF

diff --git a/symbols/LC78Lxx.sym b/symbols/LC78Lxx.sym
new file mode 100644 (file)
index 0000000..faee446
--- /dev/null
+++ b/symbols/LC78Lxx.sym
@@ -0,0 +1,43 @@
+v 20110115 2
+P 0 700 300 700 1 0 0
+{
+T 0 700 5 10 0 0 0 0 1
+pintype=unknown
+T 355 695 5 10 1 1 0 0 1
+pinlabel=Vin
+T 205 745 5 10 1 1 0 6 1
+pinnumber=3
+T 0 700 5 10 0 0 0 0 1
+pinseq=0
+}
+P 2000 700 1700 700 1 0 0
+{
+T 2000 700 5 10 0 0 0 0 1
+pintype=unknown
+T 1645 695 5 10 1 1 0 6 1
+pinlabel=Vout
+T 1795 745 5 10 1 1 0 0 1
+pinnumber=1
+T 2000 700 5 10 0 0 0 0 1
+pinseq=0
+}
+P 1000 0 1000 300 1 0 0
+{
+T 1000 0 5 10 0 0 0 0 1
+pintype=unknown
+T 1245 500 5 10 1 1 180 0 1
+pinlabel=GND
+T 950 205 5 10 1 1 90 6 1
+pinnumber=2
+T 1000 0 5 10 0 0 0 0 1
+pinseq=0
+}
+B 300 300 1400 600 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
+T 295 995 8 10 1 1 0 0 1
+refdes=U?
+T 895 995 8 10 1 1 0 0 1
+value=L78Lxx
+T -5 -5 8 10 0 1 0 0 1
+device=IC
+T 895 995 8 10 0 1 0 0 1
+footprint=SOT23

diff --git a/symbols/miniUSB.sym b/symbols/miniUSB.sym
new file mode 100644 (file)
index 0000000..6215a66
--- /dev/null
+++ b/symbols/miniUSB.sym
@@ -0,0 +1,63 @@
+v 20070902 1
+P 0 2000 300 2000 1 0 0
+{
+T 0 2000 5 10 0 0 0 0 1
+pintype=pwr
+T 355 1995 5 10 1 1 0 0 1
+pinlabel=VBUS
+T 205 2045 5 10 1 1 0 6 1
+pinnumber=1
+T 0 2000 5 10 0 0 0 0 1
+pinseq=0
+}
+P 0 1600 300 1600 1 0 0
+{
+T 0 1600 5 10 0 0 0 0 1
+pintype=io
+T 355 1595 5 10 1 1 0 0 1
+pinlabel=DATA-
+T 205 1645 5 10 1 1 0 6 1
+pinnumber=2
+T 0 1600 5 10 0 0 0 0 1
+pinseq=0
+}
+P 0 1200 300 1200 1 0 0
+{
+T 0 1200 5 10 0 0 0 0 1
+pintype=io
+T 355 1195 5 10 1 1 0 0 1
+pinlabel=DATA+
+T 205 1245 5 10 1 1 0 6 1
+pinnumber=3
+T 0 1200 5 10 0 0 0 0 1
+pinseq=0
+}
+P 0 800 300 800 1 0 0
+{
+T 0 800 5 10 0 0 0 0 1
+pintype=in
+T 355 795 5 10 1 1 0 0 1
+pinlabel=HS
+T 205 845 5 10 1 1 0 6 1
+pinnumber=4
+T 0 800 5 10 0 0 0 0 1
+pinseq=0
+}
+B 300 200 900 2100 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
+T 295 2400 8 10 1 1 0 0 1
+refdes=J?
+T 400 0 9 10 1 0 0 0 1
+miniUSB
+P 0 400 300 400 1 0 0
+{
+T 0 400 5 10 0 0 0 0 1
+pintype=pwr
+T 355 395 5 10 1 1 0 0 1
+pinlabel=GND
+T 205 445 5 10 1 1 0 6 1
+pinnumber=5
+T 0 400 5 10 0 0 0 0 1
+pinseq=0
+}
+T 355 395 8 10 0 1 0 0 1
+footprint=548190572