more tweaks based on physical analysis of Pluto-P

diff --git a/Notebook b/Notebook
index 654b43360e64486844b94ae9eef27ef5b09156a1..baa810e062b819d18676caa34469c93ab51d2dad 100644 (file)
--- a/Notebook
+++ b/Notebook
@@ -47,6 +47,18 @@ To Do:
 
        **DONE**
 
+    why not treat all the parallel port input pins with transistors?
+
+       http://emergent.unpythonic.net/01165081407 has an answer, that they
+       are used as inverters because the FPGA has weak pull-ups on those
+       pins yet those pins need to be driven low or the PC can't configure
+       the FPGA by "printing to it" .. apparently that only applies to the
+       two pins that have the inverters on them.
+
+       Duh.  Of course they're inverting... how'd I miss that?
+
+       **DONE**
+
     pin 49 hooked to pin 51 .. nCONFIG driven by nConfig
 
        **DONE**
@@ -83,5 +95,3 @@ To Do:
        pin 87 is DEV_CLRn driving nWait to the PC
        pin 90 is CLOCK hooked to db25 pin 1 whcih is nWrite
 
-    why not treat all the parallel port input pins with transistors?
-

diff --git a/cncfpga.sch b/cncfpga.sch
index 1537c477570157bc97bc598518605629641dc745..9e6e46b58119deff83caeceba06702ff0bdabeee 100644 (file)
--- a/cncfpga.sch
+++ b/cncfpga.sch
@@ -543,25 +543,15 @@ netname=dout_9
 }
 C 50400 43500 1 0 0 gnd.sym
 N 50500 43800 50400 43800 4
-N 43400 47400 42000 47400 4
-{
-T 42000 47500 5 10 1 1 0 0 1
-netname=TDI
-}
-N 43400 53800 42000 53800 4
-{
-T 42000 53900 5 10 1 1 0 0 1
-netname=nCE
-}
 N 43400 55000 42000 55000 4
 {
 T 42000 55100 5 10 1 1 0 0 1
-netname=DCLK
+netname=nWrite
 }
 N 43400 47800 42000 47800 4
 {
 T 42000 47900 5 10 1 1 0 0 1
-netname=DATA0
+netname=pport_data_0
 }
 N 43400 48200 42000 48200 4
 {
@@ -1712,3 +1702,5 @@ loadstatus=smt
 }
 N 52200 59400 52400 59400 4
 N 51300 59400 50400 59400 4
+C 43300 47100 1 0 0 gnd.sym
+C 43300 53500 1 0 0 gnd.sym