1 http://www.fourwalledcubicle.com/LUFA.php
2 programmer for TPI is included in the package, boards available online
6 - figure out if all the unconnected pins on the FPGA match the Pluto-P
8 - verify pin configuration seems to match the data in:
9 ~/src/emc2-dev/src/hal/drivers/pluto_servo_firmware/pluto_servo.pin
13 - results of physical inspection of pluto-p board
15 22 ohm series resistors on 7 pins between FPGA and 10 pin header, including
16 pins 5, 8, 9, 10, 13, 16, 93
18 ** these are din_1 through din_7 .. makes sense?
22 pin 50 has an LED and 1k resistor
24 ** my current design has 330 ohms
26 **NOT DONE .. CAN CHANGE IF NEEDED AFTER PCB FAB**
28 10k from pin 25 to pin 44, cap from pin 44 to ground
30 44 is VCCIO, 25 is nSTATUS, so this is a pull-up on nSTATUS
34 db25 pin 11 to sole pin side of one "1L" transistor, one lead to ground,
35 4.7k from remaining lead to pin 87
37 db25 pin 11 is nWait .. so it looks like nWait is being driven by
38 a transistor from the FPGA DEV_CLRn output, not directly
42 db25 pin 12 to sole pin side of one "1L" transistor, one lead to ground,
43 4.7k from remaining lead to pin 6
45 db25 pin 12 is undocumented?
46 so FPGA pin 6 is able to drive that pin through a transistor
50 pin 49 hooked to pin 51 .. nCONFIG driven by nConfig
56 consistent with my design, 40mhz to FPGA
59 26 pin header pins 11 and 12 to sole pin side of "G1" transistor, both other
60 leads have caps to ground, one to pin 24, the other to pin 37, 35
62 those header pins are VCC?
68 SOT-23 with G1 label could be:
70 transistor, 1=B, 2=E, 3(sole)=C
74 TMS is driving base or gate
75 3.3V is on emitter or source
76 header VCC is on collector or drain
78 TMS is 'test mode state' on the jtag interface, which drives the TAP
79 controller state machine. TMS going low starts a cycle?
81 4.7k between pins 87 and 90
83 pin 87 is DEV_CLRn driving nWait to the PC
84 pin 90 is CLOCK hooked to db25 pin 1 whcih is nWrite
86 why not treat all the parallel port input pins with transistors?