altos/stm32f1: Set PLLXTPRE value

This is the pre-PLL divider value which is needed when we want to
use a 16MHz crystal and a 72MHz sysclk

Signed-off-by: Keith Packard <keithp@keithp.com>

diff --git a/src/stm32f1/ao_clock.c b/src/stm32f1/ao_clock.c
index c203b01286f6074ff03b3637097e450c41538d65..3fcf33b81177da379087fdbd72c315b83a95162f 100644 (file)
--- a/src/stm32f1/ao_clock.c
+++ b/src/stm32f1/ao_clock.c
@@ -123,12 +123,15 @@ ao_clock_init(void)
        while (stm_rcc.cr & (1UL << STM_RCC_CR_PLLRDY))
                asm("nop");
 
-       /* PLLVCO */
+       /* PLLMUL */
        cfgr = stm_rcc.cfgr;
        cfgr &= ~(STM_RCC_CFGR_PLLMUL_MASK << STM_RCC_CFGR_PLLMUL);
-
        cfgr |= (AO_RCC_CFGR_PLLMUL << STM_RCC_CFGR_PLLMUL);
 
+       /* PLLXTPRE */
+       cfgr &= ~(STM_RCC_CFGR_PLLXTPRE_MASK << STM_RCC_CFGR_PLLXTPRE);
+       cfgr |= (AO_RCC_CFGR_PLLXTPRE << STM_RCC_CFGR_PLLXTPRE);
+
        /* PLL source */
        cfgr &= ~(1UL << STM_RCC_CFGR_PLLSRC);
        cfgr |= STM_RCC_CFGR_PLLSRC_TARGET_CLOCK;