#define AO_TIM91011_CLK (2 * AO_PCLK2)
#endif
-#define AO_STM_NVIC_HIGH_PRIORITY 4
-#define AO_STM_NVIC_CLOCK_PRIORITY 6
-#define AO_STM_NVIC_MED_PRIORITY 8
-#define AO_STM_NVIC_LOW_PRIORITY 10
+/* The stm32l implements only 4 bits of the priority fields */
+
+#define AO_STM_NVIC_NON_MASK_PRIORITY 0x00
+
+/* Set the basepri register to this value to mask all
+ * non-maskable priorities
+ */
+#define AO_STM_NVIC_BASEPRI_MASK 0x10
+
+#define AO_STM_NVIC_HIGH_PRIORITY 0x40
+#define AO_STM_NVIC_MED_PRIORITY 0x80
+#define AO_STM_NVIC_LOW_PRIORITY 0xC0
+#define AO_STM_NVIC_CLOCK_PRIORITY 0xf0
void ao_lcd_stm_init(void);
}
#endif
stm_nvic_set_enable(STM_ISR_DMA1_CHANNEL1_POS + index);
- stm_nvic_set_priority(STM_ISR_DMA1_CHANNEL1_POS + index, 4);
+ stm_nvic_set_priority(STM_ISR_DMA1_CHANNEL1_POS + index,
+ AO_STM_NVIC_MED_PRIORITY);
ao_dma_allocated[index] = 0;
ao_dma_mutex[index] = 0;
}
(void) gpio;
uint32_t mask = 1 << pin;
-
+
if (mode & AO_EXTI_MODE_RISING)
stm_exti.rtsr |= mask;
else
ao_usart_init(&ao_stm_usart1);
stm_nvic_set_enable(STM_ISR_USART1_POS);
- stm_nvic_set_priority(STM_ISR_USART1_POS, 4);
+ stm_nvic_set_priority(STM_ISR_USART1_POS, AO_STM_NVIC_MED_PRIORITY);
#if USE_SERIAL_1_STDIN && !DELAY_SERIAL_1_STDIN
ao_add_stdio(_ao_serial1_pollchar,
ao_serial1_putchar,
#endif
stm_nvic_set_enable(STM_ISR_USART2_POS);
- stm_nvic_set_priority(STM_ISR_USART2_POS, 4);
+ stm_nvic_set_priority(STM_ISR_USART2_POS, AO_STM_NVIC_MED_PRIORITY);
#if USE_SERIAL_2_STDIN && !DELAY_SERIAL_2_STDIN
ao_add_stdio(_ao_serial2_pollchar,
ao_serial2_putchar,
ao_usart_init(&ao_stm_usart3);
stm_nvic_set_enable(STM_ISR_USART3_POS);
- stm_nvic_set_priority(STM_ISR_USART3_POS, 4);
+ stm_nvic_set_priority(STM_ISR_USART3_POS, AO_STM_NVIC_MED_PRIORITY);
#if USE_SERIAL_3_STDIN && !DELAY_SERIAL_3_STDIN
ao_add_stdio(_ao_serial3_pollchar,
ao_serial3_putchar,
void stm_systick_isr(void)
{
- ao_arch_release_interrupts();
ao_validate_cur_stack();
++ao_tick_count;
#if HAS_TASK_QUEUE
stm_systick.csr = ((1 << STM_SYSTICK_CSR_ENABLE) |
(1 << STM_SYSTICK_CSR_TICKINT) |
(STM_SYSTICK_CSR_CLKSOURCE_HCLK_8 << STM_SYSTICK_CSR_CLKSOURCE));
- stm_nvic.shpr15_12 |= 0xff << 24;
+ stm_nvic.shpr15_12 |= AO_STM_NVIC_CLOCK_PRIORITY << 24;
}
#endif
ao_arch_block_interrupts();
/* Route interrupts */
- stm_nvic_set_priority(STM_ISR_USB_LP_POS, 3);
+ stm_nvic_set_priority(STM_ISR_USB_LP_POS, AO_STM_NVIC_LOW_PRIORITY);
stm_nvic_set_enable(STM_ISR_USB_LP_POS);
ao_usb_configuration = 0;
int line;
char *msg;
uint32_t value;
- uint32_t primask;
+ uint32_t basepri;
#if TX_DBG
uint16_t in_count;
uint32_t in_epr;
#endif
};
-#define NUM_USB_DBG 128
+#define NUM_USB_DBG 16
-static struct ao_usb_dbg dbg[128];
+static struct ao_usb_dbg dbg[NUM_USB_DBG];
static int dbg_i;
static void _dbg(int line, char *msg, uint32_t value)
{
- uint32_t primask;
+ uint32_t basepri;
dbg[dbg_i].line = line;
dbg[dbg_i].msg = msg;
dbg[dbg_i].value = value;
- asm("mrs %0,primask" : "=&r" (primask));
- dbg[dbg_i].primask = primask;
+ asm("mrs %0,basepri" : "=&r" (basepri));
+ dbg[dbg_i].basepri = basepri;
#if TX_DBG
dbg[dbg_i].in_count = in_count;
dbg[dbg_i].in_epr = stm_usb.epr[AO_USB_IN_EPR];