altos/stm: Support SPI modes other than 0

ADXL375 requires SPI mode 3.

Signed-off-by: Keith Packard <keithp@keithp.com>

diff --git a/src/stm/ao_arch_funcs.h b/src/stm/ao_arch_funcs.h
index 9bb598f67fa3d68496c29f1a9ed2f8147957a149..7fe6a732478b442f1b9ce445f7cb253d01cadd88 100644 (file)
--- a/src/stm/ao_arch_funcs.h
+++ b/src/stm/ao_arch_funcs.h
@@ -39,6 +39,9 @@
 
 #define AO_SPI_SPEED_200kHz    AO_SPI_SPEED_125kHz
 
+#define AO_SPI_CPOL_BIT                4
+#define AO_SPI_CPHA_BIT                5
+
 #define AO_SPI_CONFIG_1                0x00
 #define AO_SPI_1_CONFIG_PA5_PA6_PA7    AO_SPI_CONFIG_1
 #define AO_SPI_2_CONFIG_PB13_PB14_PB15 AO_SPI_CONFIG_1
@@ -64,6 +67,15 @@
 
 #define AO_SPI_INDEX(id)       ((id) & AO_SPI_INDEX_MASK)
 #define AO_SPI_CONFIG(id)      ((id) & AO_SPI_CONFIG_MASK)
+#define AO_SPI_PIN_CONFIG(id)  ((id) & (AO_SPI_INDEX_MASK | AO_SPI_CONFIG_MASK))
+#define AO_SPI_CPOL(id)                ((uint32_t) (((id) >> AO_SPI_CPOL_BIT) & 1))
+#define AO_SPI_CPHA(id)                ((uint32_t) (((id) >> AO_SPI_CPHA_BIT) & 1))
+
+#define AO_SPI_MAKE_MODE(pol,pha)      (((pol) << AO_SPI_CPOL_BIT) | ((pha) << AO_SPI_CPHA_BIT))
+#define AO_SPI_MODE_0          AO_SPI_MAKE_MODE(0,0)
+#define AO_SPI_MODE_1          AO_SPI_MAKE_MODE(0,1)
+#define AO_SPI_MODE_2          AO_SPI_MAKE_MODE(1,0)
+#define AO_SPI_MODE_3          AO_SPI_MAKE_MODE(1,1)
 
 uint8_t
 ao_spi_try_get(uint8_t spi_index, uint32_t speed, uint8_t task_id);

diff --git a/src/stm/ao_spi_stm.c b/src/stm/ao_spi_stm.c
index 05078f3b841b203b9b550040bc191b6aeaeda193..1a04a2899a825afa758726d5625d3c11a7536c34 100644 (file)
--- a/src/stm/ao_spi_stm.c
+++ b/src/stm/ao_spi_stm.c
@@ -25,7 +25,7 @@ struct ao_spi_stm_info {
 };
 
 static uint8_t         ao_spi_mutex[STM_NUM_SPI];
-static uint8_t         ao_spi_index[STM_NUM_SPI];
+static uint8_t         ao_spi_pin_config[STM_NUM_SPI];
 
 static const struct ao_spi_stm_info ao_spi_stm_info[STM_NUM_SPI] = {
        {
@@ -285,11 +285,11 @@ ao_spi_duplex(const void *out, void *in, uint16_t len, uint8_t spi_index)
 }
 
 static void
-ao_spi_disable_index(uint8_t spi_index)
+ao_spi_disable_pin_config(uint8_t spi_pin_config)
 {
        /* Disable current config
         */
-       switch (spi_index) {
+       switch (spi_pin_config) {
        case AO_SPI_1_PA5_PA6_PA7:
                stm_gpio_set(&stm_gpioa, 5, 1);
                stm_moder_set(&stm_gpioa, 5, STM_MODER_OUTPUT);
@@ -324,11 +324,11 @@ ao_spi_disable_index(uint8_t spi_index)
 }
 
 static void
-ao_spi_enable_index(uint8_t spi_index)
+ao_spi_enable_pin_config(uint8_t spi_pin_config)
 {
        /* Enable new config
         */
-       switch (spi_index) {
+       switch (spi_pin_config) {
        case AO_SPI_1_PA5_PA6_PA7:
                stm_afr_set(&stm_gpioa, 5, STM_AFR_AF5);
                stm_afr_set(&stm_gpioa, 6, STM_AFR_AF5);
@@ -360,23 +360,26 @@ ao_spi_enable_index(uint8_t spi_index)
 static void
 ao_spi_config(uint8_t spi_index, uint32_t speed)
 {
+       uint8_t         spi_pin_config = AO_SPI_PIN_CONFIG(spi_index);
        uint8_t         id = AO_SPI_INDEX(spi_index);
        struct stm_spi  *stm_spi = ao_spi_stm_info[id].stm_spi;
 
-       if (spi_index != ao_spi_index[id]) {
+       if (spi_pin_config != ao_spi_pin_config[id]) {
 
                /* Disable old config
                 */
-               ao_spi_disable_index(ao_spi_index[id]);
+               ao_spi_disable_pin_config(ao_spi_pin_config[id]);
 
                /* Enable new config
                 */
-               ao_spi_enable_index(spi_index);
+               ao_spi_enable_pin_config(spi_pin_config);
 
                /* Remember current config
                 */
-               ao_spi_index[id] = spi_index;
+               ao_spi_pin_config[id] = spi_pin_config;
        }
+
+       /* Turn the SPI transceiver on and set the mode */
        stm_spi->cr1 = ((0 << STM_SPI_CR1_BIDIMODE) |           /* Three wire mode */
                        (0 << STM_SPI_CR1_BIDIOE) |
                        (0 << STM_SPI_CR1_CRCEN) |              /* CRC disabled */
@@ -389,8 +392,8 @@ ao_spi_config(uint8_t spi_index, uint32_t speed)
                        (1 << STM_SPI_CR1_SPE) |                /* Enable SPI unit */
                        (speed << STM_SPI_CR1_BR) |             /* baud rate to pclk/4 */
                        (1 << STM_SPI_CR1_MSTR) |
-                       (0 << STM_SPI_CR1_CPOL) |               /* Format 0 */
-                       (0 << STM_SPI_CR1_CPHA));
+                       (AO_SPI_CPOL(spi_index) << STM_SPI_CR1_CPOL) |  /* Format */
+                       (AO_SPI_CPHA(spi_index) << STM_SPI_CR1_CPHA));
        validate_spi(stm_spi, 13, 0);
 }
 
@@ -430,7 +433,7 @@ ao_spi_channel_init(uint8_t spi_index)
        uint8_t         id = AO_SPI_INDEX(spi_index);
        struct stm_spi  *stm_spi = ao_spi_stm_info[id].stm_spi;
 
-       ao_spi_disable_index(spi_index);
+       ao_spi_disable_pin_config(AO_SPI_PIN_CONFIG(spi_index));
 
        stm_spi->cr1 = 0;
        stm_spi->cr2 = ((0 << STM_SPI_CR2_TXEIE) |
@@ -512,7 +515,7 @@ ao_spi_init(void)
        stm_ospeedr_set(&stm_gpioe, 15, SPI_1_OSPEEDR);
 # endif
        stm_rcc.apb2enr |= (1 << STM_RCC_APB2ENR_SPI1EN);
-       ao_spi_index[0] = AO_SPI_CONFIG_NONE;
+       ao_spi_pin_config[0] = AO_SPI_CONFIG_NONE;
        ao_spi_channel_init(0);
 #endif
 
@@ -530,7 +533,7 @@ ao_spi_init(void)
        stm_ospeedr_set(&stm_gpiod, 4, SPI_2_OSPEEDR);
 # endif
        stm_rcc.apb1enr |= (1 << STM_RCC_APB1ENR_SPI2EN);
-       ao_spi_index[1] = AO_SPI_CONFIG_NONE;
+       ao_spi_pin_config[1] = AO_SPI_CONFIG_NONE;
        ao_spi_channel_init(1);
 #endif
 #if DEBUG