+/* 16MHz crystal */
+
+#define AO_HSE 1
+#define AO_HSE_BYPASS 0
+
+#define AO_SYSCLK 72000000
+#define AO_HCLK 72000000
+#define AO_APB1CLK 36000000
+#define AO_APB2CLK 72000000
+#define AO_ADCCLK 12000000
+
+/* PLLMUL is 9, PLLXTPRE (pre divider) is 2, so the
+ * overall PLLCLK is 16 * 9/2 = 72MHz (used as SYSCLK)
+ *
+ * HCLK is SYSCLK / 1 (HPRE_DIV) = 72MHz (72MHz max)
+ * USB is PLLCLK / 1.5 (USBPRE)= 48MHz (must be 48MHz)
+ * APB2 is HCLK / 1 (PPRE2_DIV) = 72MHz (72MHz max)
+ * APB1 is HCLK / 2 (PPRE1_DIV) = 36MHz (36MHz max)
+ * ADC is APB2 / 6 (ADCPRE) = 12MHz (14MHz max)
+ */
+
+#define AO_RCC_CFGR_USBPRE STM_RCC_CFGR_USBPRE_1_5
+#define AO_RCC_CFGR_PLLMUL STM_RCC_CFGR_PLLMUL_9
+#define AO_RCC_CFGR_PLLXTPRE STM_RCC_CFGR_PLLXTPRE_2
+#define AO_RCC_CFGR_PPRE2_DIV STM_RCC_CFGR_PPRE2_DIV_1
+#define AO_RCC_CFGR_PPRE1_DIV STM_RCC_CFGR_PPRE1_DIV_2
+#define AO_RCC_CFGR_HPRE_DIV STM_RCC_CFGR_HPRE_DIV_1
+#define AO_RCC_CFGR_ADCPRE STM_RCC_CFGR_ADCPRE_6