+#define STM_SYSCFG_CFGR1_TIM3_DMA_RMP 30
+#define STM_SYSCFG_CFGR1_TIM2_DMA_RMP 29
+#define STM_SYSCFG_CFGR1_TIM1_DMA_RMP 28
+#define STM_SYSCFG_CFGR1_I2C1_DMA_RMP 27
+#define STM_SYSCFG_CFGR1_USART3_DMA_RMP 26
+#define STM_SYSCFG_CFGR1_USART2_DMA_RMP 25
+#define STM_SYSCFG_CFGR1_SPI2_DMA_RMP 24
+#define STM_SYSCFG_CFGR1_I2C_PA10_FMP 23
+#define STM_SYSCFG_CFGR1_I2C_PA9_FMP 22
+#define STM_SYSCFG_CFGR1_I2C2_FMP 21
+#define STM_SYSCFG_CFGR1_I2C1_FMP 20
+#define STM_SYSCFG_CFGR1_I2C_PB9_FMP 19
+#define STM_SYSCFG_CFGR1_I2C_PB8_FMP 18
+#define STM_SYSCFG_CFGR1_I2C_PB7_FMP 17
+#define STM_SYSCFG_CFGR1_I2C_PB6_FMP 16
+#define STM_SYSCFG_CFGR1_TIM17_DMA_RMP2 14
+#define STM_SYSCFG_CFGR1_TIM16_DMA_RMP2 13
+#define STM_SYSCFG_CFGR1_TIM17_DMA_RMP 12
+#define STM_SYSCFG_CFGR1_TIM16_DMA_RMP 11
+#define STM_SYSCFG_CFGR1_USART1_RX_DMA_RMP 10
+#define STM_SYSCFG_CFGR1_USART1_TX_DMA_RMP 9
+#define STM_SYSCFG_CFGR1_ADC_DMA_RMP 8
+#define STM_SYSCFG_CFGR1_IRDA_ENV_SEL 6
+#define STM_SYSCFG_CFGR1_IRDA_ENV_SEL_TIMER16 0
+#define STM_SYSCFG_CFGR1_IRDA_ENV_SEL_USART1 1
+#define STM_SYSCFG_CFGR1_IRDA_ENV_SEL_USART4 2
+#define STM_SYSCFG_CFGR1_PA11_PA12_RMP 4
+#define STM_SYSCFG_CFGR1_MEM_MODE 0
+#define STM_SYSCFG_CFGR1_MEM_MODE_MAIN_FLASH 0
+#define STM_SYSCFG_CFGR1_MEM_MODE_SYSTEM_FLASH 1
+#define STM_SYSCFG_CFGR1_MEM_MODE_SRAM 3
+#define STM_SYSCFG_CFGR1_MEM_MODE_MASK 3
+