2 * Copyright © 2012 Keith Packard <keithp@keithp.com>
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; version 2 of the License.
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
11 * General Public License for more details.
13 * You should have received a copy of the GNU General Public License along
14 * with this program; if not, write to the Free Software Foundation, Inc.,
15 * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
20 #include "ao_product.h"
25 #define USB_DEBUG_DATA 0
28 #ifndef AO_PA11_PA12_RMP
29 #error "must define AO_PA11_PA12_RMP"
33 #define USE_USB_STDIO 1
37 #define AO_USB_OUT_SLEEP_ADDR (&ao_stdin_ready)
39 #define AO_USB_OUT_SLEEP_ADDR (&ao_usb_out_avail)
43 #define debug(format, args...) printf(format, ## args);
45 #define debug(format, args...)
49 #define debug_data(format, args...) printf(format, ## args);
51 #define debug_data(format, args...)
55 uint8_t dir_type_recip;
62 static uint8_t ao_usb_ep0_state;
64 /* Pending EP0 IN data */
65 static const uint8_t *ao_usb_ep0_in_data; /* Remaining data */
66 static uint8_t ao_usb_ep0_in_len; /* Remaining amount */
68 /* Temp buffer for smaller EP0 in data */
69 static uint8_t ao_usb_ep0_in_buf[2];
71 /* Pending EP0 OUT data */
72 static uint8_t *ao_usb_ep0_out_data;
73 static uint8_t ao_usb_ep0_out_len;
76 * Objects allocated in special USB memory
79 /* Buffer description tables */
80 static union stm_usb_bdt *ao_usb_bdt;
81 /* USB address of end of allocated storage */
82 static uint16_t ao_usb_sram_addr;
84 /* Pointer to ep0 tx/rx buffers in USB memory */
85 static uint16_t *ao_usb_ep0_tx_buffer;
86 static uint16_t *ao_usb_ep0_rx_buffer;
88 /* Pointer to interrupt buffer in USB memory */
89 static uint16_t ao_usb_int_tx_offset;
91 /* Pointer to bulk data tx/rx buffers in USB memory */
92 static uint16_t ao_usb_in_tx_offset;
93 static uint16_t *ao_usb_in_tx_buffer;
94 static uint16_t ao_usb_out_rx_offset;
95 static uint16_t *ao_usb_out_rx_buffer;
97 /* System ram shadow of USB buffer; writing individual bytes is
98 * too much of a pain (sigh) */
99 static uint8_t ao_usb_tx_buffer[AO_USB_IN_SIZE];
100 static uint8_t ao_usb_tx_count;
102 static uint8_t ao_usb_rx_buffer[AO_USB_OUT_SIZE];
103 static uint8_t ao_usb_rx_count, ao_usb_rx_pos;
106 * End point register indices
109 #define AO_USB_CONTROL_EPR 0
110 #define AO_USB_INT_EPR 1
111 #define AO_USB_OUT_EPR 2
112 #define AO_USB_IN_EPR 3
114 /* Marks when we don't need to send an IN packet.
115 * This happens only when the last IN packet is not full,
116 * otherwise the host will expect to keep seeing packets.
117 * Send a zero-length packet as required
119 static uint8_t ao_usb_in_flushed;
121 /* Marks when we have delivered an IN packet to the hardware
122 * and it has not been received yet. ao_sleep on this address
123 * to wait for it to be delivered.
125 static uint8_t ao_usb_in_pending;
127 /* Marks when an OUT packet has been received by the hardware
128 * but not pulled to the shadow buffer.
130 static uint8_t ao_usb_out_avail;
131 uint8_t ao_usb_running;
132 static uint8_t ao_usb_configuration;
134 #define AO_USB_EP0_GOT_SETUP 1
135 #define AO_USB_EP0_GOT_RX_DATA 2
136 #define AO_USB_EP0_GOT_TX_ACK 4
138 static uint8_t ao_usb_ep0_receive;
139 static uint8_t ao_usb_address;
140 static uint8_t ao_usb_address_pending;
142 static inline uint32_t set_toggle(uint32_t current_value,
144 uint32_t desired_value)
146 return (current_value ^ desired_value) & mask;
149 static inline uint16_t *ao_usb_packet_buffer_addr(uint16_t sram_addr)
151 return (uint16_t *) (stm_usb_sram + sram_addr);
154 static inline uint16_t ao_usb_packet_buffer_offset(uint16_t *addr)
156 return (uint16_t) ((uint8_t *) addr - stm_usb_sram);
159 static inline uint32_t ao_usb_epr_stat_rx(uint32_t epr) {
160 return (epr >> STM_USB_EPR_STAT_RX) & STM_USB_EPR_STAT_RX_MASK;
163 static inline uint32_t ao_usb_epr_stat_tx(uint32_t epr) {
164 return (epr >> STM_USB_EPR_STAT_TX) & STM_USB_EPR_STAT_TX_MASK;
167 static inline uint32_t ao_usb_epr_ctr_rx(uint32_t epr) {
168 return (epr >> STM_USB_EPR_CTR_RX) & 1;
171 static inline uint32_t ao_usb_epr_ctr_tx(uint32_t epr) {
172 return (epr >> STM_USB_EPR_CTR_TX) & 1;
175 static inline uint32_t ao_usb_epr_setup(uint32_t epr) {
176 return (epr >> STM_USB_EPR_SETUP) & 1;
179 static inline uint32_t ao_usb_epr_dtog_rx(uint32_t epr) {
180 return (epr >> STM_USB_EPR_DTOG_RX) & 1;
183 static inline uint32_t ao_usb_epr_dtog_tx(uint32_t epr) {
184 return (epr >> STM_USB_EPR_DTOG_TX) & 1;
188 * Set current device address and mark the
189 * interface as active
192 ao_usb_set_address(uint8_t address)
194 debug("ao_usb_set_address %02x\n", address);
195 stm_usb.daddr = (1 << STM_USB_DADDR_EF) | address;
196 ao_usb_address_pending = 0;
200 * Write these values to preserve register contents under HW changes
203 #define STM_USB_EPR_INVARIANT ((1 << STM_USB_EPR_CTR_RX) | \
204 (STM_USB_EPR_DTOG_RX_WRITE_INVARIANT << STM_USB_EPR_DTOG_RX) | \
205 (STM_USB_EPR_STAT_RX_WRITE_INVARIANT << STM_USB_EPR_STAT_RX) | \
206 (1 << STM_USB_EPR_CTR_TX) | \
207 (STM_USB_EPR_DTOG_TX_WRITE_INVARIANT << STM_USB_EPR_DTOG_TX) | \
208 (STM_USB_EPR_STAT_TX_WRITE_INVARIANT << STM_USB_EPR_STAT_TX))
210 #define STM_USB_EPR_INVARIANT_MASK ((1 << STM_USB_EPR_CTR_RX) | \
211 (STM_USB_EPR_DTOG_RX_MASK << STM_USB_EPR_DTOG_RX) | \
212 (STM_USB_EPR_STAT_RX_MASK << STM_USB_EPR_STAT_RX) | \
213 (1 << STM_USB_EPR_CTR_TX) | \
214 (STM_USB_EPR_DTOG_TX_MASK << STM_USB_EPR_DTOG_TX) | \
215 (STM_USB_EPR_STAT_TX_MASK << STM_USB_EPR_STAT_TX))
218 * These bits are purely under sw control, so preserve them in the
219 * register by re-writing what was read
221 #define STM_USB_EPR_PRESERVE_MASK ((STM_USB_EPR_EP_TYPE_MASK << STM_USB_EPR_EP_TYPE) | \
222 (1 << STM_USB_EPR_EP_KIND) | \
223 (STM_USB_EPR_EA_MASK << STM_USB_EPR_EA))
229 #define _tx_dbg0(msg) _dbg(__LINE__,msg,0)
230 #define _tx_dbg1(msg,value) _dbg(__LINE__,msg,value)
232 #define _tx_dbg0(msg)
233 #define _tx_dbg1(msg,value)
237 #define _rx_dbg0(msg) _dbg(__LINE__,msg,0)
238 #define _rx_dbg1(msg,value) _dbg(__LINE__,msg,value)
240 #define _rx_dbg0(msg)
241 #define _rx_dbg1(msg,value)
245 static void _dbg(int line, char *msg, uint32_t value);
249 * Set the state of the specified endpoint register to a new
250 * value. This is tricky because the bits toggle where the new
251 * value is one, and we need to write invariant values in other
252 * spots of the register. This hardware is strange...
255 _ao_usb_set_stat_tx(int ep, uint32_t stat_tx)
257 uint16_t epr_write, epr_old;
259 _tx_dbg1("set_stat_tx top", stat_tx);
260 epr_old = epr_write = stm_usb.epr[ep].r;
261 epr_write &= STM_USB_EPR_PRESERVE_MASK;
262 epr_write |= STM_USB_EPR_INVARIANT;
263 epr_write |= set_toggle(epr_old,
264 STM_USB_EPR_STAT_TX_MASK << STM_USB_EPR_STAT_TX,
265 stat_tx << STM_USB_EPR_STAT_TX);
266 stm_usb.epr[ep].r = epr_write;
267 _tx_dbg1("set_stat_tx bottom", epr_write);
271 ao_usb_set_stat_tx(int ep, uint32_t stat_tx)
273 ao_arch_block_interrupts();
274 _ao_usb_set_stat_tx(ep, stat_tx);
275 ao_arch_release_interrupts();
279 _ao_usb_set_stat_rx(int ep, uint32_t stat_rx) {
280 uint16_t epr_write, epr_old;
282 epr_write = epr_old = stm_usb.epr[ep].r;
283 epr_write &= STM_USB_EPR_PRESERVE_MASK;
284 epr_write |= STM_USB_EPR_INVARIANT;
285 epr_write |= set_toggle(epr_old,
286 STM_USB_EPR_STAT_RX_MASK << STM_USB_EPR_STAT_RX,
287 stat_rx << STM_USB_EPR_STAT_RX);
288 stm_usb.epr[ep].r = epr_write;
292 ao_usb_set_stat_rx(int ep, uint32_t stat_rx) {
293 ao_arch_block_interrupts();
294 _ao_usb_set_stat_rx(ep, stat_rx);
295 ao_arch_release_interrupts();
299 * Set just endpoint 0, for use during startup
303 ao_usb_init_ep(uint8_t ep, uint32_t addr, uint32_t type, uint32_t stat_rx, uint32_t stat_tx)
307 ao_arch_block_interrupts();
308 epr = stm_usb.epr[ep].r;
309 epr = ((0 << STM_USB_EPR_CTR_RX) |
310 (epr & (1 << STM_USB_EPR_DTOG_RX)) |
312 (STM_USB_EPR_STAT_RX_MASK << STM_USB_EPR_STAT_RX),
313 (stat_rx << STM_USB_EPR_STAT_RX)) |
314 (type << STM_USB_EPR_EP_TYPE) |
315 (0 << STM_USB_EPR_EP_KIND) |
316 (0 << STM_USB_EPR_CTR_TX) |
317 (epr & (1 << STM_USB_EPR_DTOG_TX)) |
319 (STM_USB_EPR_STAT_TX_MASK << STM_USB_EPR_STAT_TX),
320 (stat_tx << STM_USB_EPR_STAT_TX)) |
321 (addr << STM_USB_EPR_EA));
322 stm_usb.epr[ep].r = epr;
323 ao_arch_release_interrupts();
324 debug ("writing epr[%d] 0x%04x wrote 0x%04x\n",
325 ep, epr, stm_usb.epr[ep].r);
329 ao_usb_alloc_buffers(void)
331 ao_usb_sram_addr = 0;
333 ao_usb_bdt = (void *) stm_usb_sram;
334 ao_usb_sram_addr += 8 * STM_USB_BDT_SIZE;
336 ao_usb_ep0_tx_buffer = ao_usb_packet_buffer_addr(ao_usb_sram_addr);
337 ao_usb_sram_addr += AO_USB_CONTROL_SIZE;
339 ao_usb_ep0_rx_buffer = ao_usb_packet_buffer_addr(ao_usb_sram_addr);
340 ao_usb_sram_addr += AO_USB_CONTROL_SIZE;
342 ao_usb_int_tx_offset = ao_usb_sram_addr;
343 ao_usb_sram_addr += AO_USB_INT_SIZE;
345 ao_usb_out_rx_buffer = ao_usb_packet_buffer_addr(ao_usb_sram_addr);
346 ao_usb_out_rx_offset = ao_usb_sram_addr;
347 ao_usb_sram_addr += AO_USB_OUT_SIZE;
349 ao_usb_in_tx_buffer = ao_usb_packet_buffer_addr(ao_usb_sram_addr);
350 ao_usb_in_tx_offset = ao_usb_sram_addr;
351 ao_usb_sram_addr += AO_USB_IN_SIZE;
355 ao_usb_init_btable(void)
357 /* Set up EP 0 - a Control end point with 32 bytes of in and out buffers */
359 ao_usb_bdt[0].single.addr_tx = ao_usb_packet_buffer_offset(ao_usb_ep0_tx_buffer);
360 ao_usb_bdt[0].single.count_tx = 0;
362 ao_usb_bdt[0].single.addr_rx = ao_usb_packet_buffer_offset(ao_usb_ep0_rx_buffer);
363 ao_usb_bdt[0].single.count_rx = ((1 << STM_USB_BDT_COUNT_RX_BL_SIZE) |
364 (((AO_USB_CONTROL_SIZE / 32) - 1) << STM_USB_BDT_COUNT_RX_NUM_BLOCK));
372 ao_usb_init_btable();
374 /* buffer table is at the start of USB memory */
377 ao_usb_init_ep(AO_USB_CONTROL_EPR, AO_USB_CONTROL_EP,
378 STM_USB_EPR_EP_TYPE_CONTROL,
379 STM_USB_EPR_STAT_RX_VALID,
380 STM_USB_EPR_STAT_TX_NAK);
382 /* Clear all of the other endpoints */
383 for (e = 1; e < 8; e++) {
385 STM_USB_EPR_EP_TYPE_CONTROL,
386 STM_USB_EPR_STAT_RX_DISABLED,
387 STM_USB_EPR_STAT_TX_DISABLED);
390 ao_usb_set_address(0);
396 ao_usb_set_configuration(void)
398 debug ("ao_usb_set_configuration\n");
400 /* Set up the INT end point */
401 ao_usb_bdt[AO_USB_INT_EPR].single.addr_tx = ao_usb_int_tx_offset;
402 ao_usb_bdt[AO_USB_INT_EPR].single.count_tx = 0;
404 ao_usb_init_ep(AO_USB_INT_EPR,
406 STM_USB_EPR_EP_TYPE_INTERRUPT,
407 STM_USB_EPR_STAT_RX_DISABLED,
408 STM_USB_EPR_STAT_TX_NAK);
410 /* Set up the OUT end point */
411 ao_usb_bdt[AO_USB_OUT_EPR].single.addr_rx = ao_usb_out_rx_offset;
412 ao_usb_bdt[AO_USB_OUT_EPR].single.count_rx = ((1 << STM_USB_BDT_COUNT_RX_BL_SIZE) |
413 (((AO_USB_OUT_SIZE / 32) - 1) << STM_USB_BDT_COUNT_RX_NUM_BLOCK));
415 ao_usb_init_ep(AO_USB_OUT_EPR,
417 STM_USB_EPR_EP_TYPE_BULK,
418 STM_USB_EPR_STAT_RX_VALID,
419 STM_USB_EPR_STAT_TX_DISABLED);
421 /* Set up the IN end point */
422 ao_usb_bdt[AO_USB_IN_EPR].single.addr_tx = ao_usb_in_tx_offset;
423 ao_usb_bdt[AO_USB_IN_EPR].single.count_tx = 0;
425 ao_usb_init_ep(AO_USB_IN_EPR,
427 STM_USB_EPR_EP_TYPE_BULK,
428 STM_USB_EPR_STAT_RX_DISABLED,
429 STM_USB_EPR_STAT_TX_NAK);
433 ao_wakeup(&ao_usb_running);
437 static uint16_t control_count;
438 static uint16_t int_count;
439 static uint16_t in_count;
440 static uint16_t out_count;
441 static uint16_t reset_count;
442 static uint16_t suspend_count;
444 /* The USB memory must be accessed in 16-bit units
448 ao_usb_copy_tx(const uint8_t *src, uint16_t *base, uint16_t bytes)
451 *base++ = src[0] | (src[1] << 8);
460 ao_usb_copy_rx(uint8_t *dst, uint16_t *base, uint16_t bytes)
463 uint16_t s = *base++;
473 /* Send an IN data packet */
475 ao_usb_ep0_flush(void)
479 /* Check to see if the endpoint is still busy */
480 if (ao_usb_epr_stat_tx(stm_usb.epr[0].r) == STM_USB_EPR_STAT_TX_VALID) {
481 debug("EP0 not accepting IN data\n");
485 this_len = ao_usb_ep0_in_len;
486 if (this_len > AO_USB_CONTROL_SIZE)
487 this_len = AO_USB_CONTROL_SIZE;
489 if (this_len < AO_USB_CONTROL_SIZE)
490 ao_usb_ep0_state = AO_USB_EP0_IDLE;
492 ao_usb_ep0_in_len -= this_len;
494 debug_data ("Flush EP0 len %d:", this_len);
495 ao_usb_copy_tx(ao_usb_ep0_in_data, ao_usb_ep0_tx_buffer, this_len);
497 ao_usb_ep0_in_data += this_len;
499 /* Mark the endpoint as TX valid to send the packet */
500 ao_usb_bdt[AO_USB_CONTROL_EPR].single.count_tx = this_len;
501 ao_usb_set_stat_tx(AO_USB_CONTROL_EPR, STM_USB_EPR_STAT_TX_VALID);
502 debug ("queue tx. epr 0 now %08x\n", stm_usb.epr[AO_USB_CONTROL_EPR]);
505 /* Read data from the ep0 OUT fifo */
507 ao_usb_ep0_fill(void)
509 uint16_t len = ao_usb_bdt[0].single.count_rx & STM_USB_BDT_COUNT_RX_COUNT_RX_MASK;
511 if (len > ao_usb_ep0_out_len)
512 len = ao_usb_ep0_out_len;
513 ao_usb_ep0_out_len -= len;
515 /* Pull all of the data out of the packet */
516 debug_data ("Fill EP0 len %d:", len);
517 ao_usb_copy_rx(ao_usb_ep0_out_data, ao_usb_ep0_rx_buffer, len);
519 ao_usb_ep0_out_data += len;
522 ao_usb_set_stat_rx(0, STM_USB_EPR_STAT_RX_VALID);
526 ao_usb_ep0_in_reset(void)
528 ao_usb_ep0_in_data = ao_usb_ep0_in_buf;
529 ao_usb_ep0_in_len = 0;
533 ao_usb_ep0_in_queue_byte(uint8_t a)
535 if (ao_usb_ep0_in_len < sizeof (ao_usb_ep0_in_buf))
536 ao_usb_ep0_in_buf[ao_usb_ep0_in_len++] = a;
540 ao_usb_ep0_in_set(const uint8_t *data, uint8_t len)
542 ao_usb_ep0_in_data = data;
543 ao_usb_ep0_in_len = len;
547 ao_usb_ep0_out_set(uint8_t *data, uint8_t len)
549 ao_usb_ep0_out_data = data;
550 ao_usb_ep0_out_len = len;
554 ao_usb_ep0_in_start(uint16_t max)
556 /* Don't send more than asked for */
557 if (ao_usb_ep0_in_len > max)
558 ao_usb_ep0_in_len = max;
562 static struct ao_usb_line_coding ao_usb_line_coding = {115200, 0, 0, 8};
564 /* Walk through the list of descriptors and find a match
567 ao_usb_get_descriptor(uint16_t value)
569 const uint8_t *descriptor;
570 uint8_t type = value >> 8;
571 uint8_t index = value;
573 descriptor = ao_usb_descriptors;
574 while (descriptor[0] != 0) {
575 if (descriptor[1] == type && index-- == 0) {
577 if (type == AO_USB_DESC_CONFIGURATION)
581 ao_usb_ep0_in_set(descriptor, len);
584 descriptor += descriptor[0];
589 ao_usb_ep0_setup(void)
591 /* Pull the setup packet out of the fifo */
592 ao_usb_ep0_out_set((uint8_t *) &ao_usb_setup, 8);
594 if (ao_usb_ep0_out_len != 0) {
595 debug ("invalid setup packet length\n");
599 if ((ao_usb_setup.dir_type_recip & AO_USB_DIR_IN) || ao_usb_setup.length == 0)
600 ao_usb_ep0_state = AO_USB_EP0_DATA_IN;
602 ao_usb_ep0_state = AO_USB_EP0_DATA_OUT;
604 ao_usb_ep0_in_reset();
606 switch(ao_usb_setup.dir_type_recip & AO_USB_SETUP_TYPE_MASK) {
607 case AO_USB_TYPE_STANDARD:
608 debug ("Standard setup packet\n");
609 switch(ao_usb_setup.dir_type_recip & AO_USB_SETUP_RECIP_MASK) {
610 case AO_USB_RECIP_DEVICE:
611 debug ("Device setup packet\n");
612 switch(ao_usb_setup.request) {
613 case AO_USB_REQ_GET_STATUS:
614 debug ("get status\n");
615 ao_usb_ep0_in_queue_byte(0);
616 ao_usb_ep0_in_queue_byte(0);
618 case AO_USB_REQ_SET_ADDRESS:
619 debug ("set address %d\n", ao_usb_setup.value);
620 ao_usb_address = ao_usb_setup.value;
621 ao_usb_address_pending = 1;
623 case AO_USB_REQ_GET_DESCRIPTOR:
624 debug ("get descriptor %d\n", ao_usb_setup.value);
625 ao_usb_get_descriptor(ao_usb_setup.value);
627 case AO_USB_REQ_GET_CONFIGURATION:
628 debug ("get configuration %d\n", ao_usb_configuration);
629 ao_usb_ep0_in_queue_byte(ao_usb_configuration);
631 case AO_USB_REQ_SET_CONFIGURATION:
632 ao_usb_configuration = ao_usb_setup.value;
633 debug ("set configuration %d\n", ao_usb_configuration);
634 ao_usb_set_configuration();
638 case AO_USB_RECIP_INTERFACE:
639 debug ("Interface setup packet\n");
640 switch(ao_usb_setup.request) {
641 case AO_USB_REQ_GET_STATUS:
642 ao_usb_ep0_in_queue_byte(0);
643 ao_usb_ep0_in_queue_byte(0);
645 case AO_USB_REQ_GET_INTERFACE:
646 ao_usb_ep0_in_queue_byte(0);
648 case AO_USB_REQ_SET_INTERFACE:
652 case AO_USB_RECIP_ENDPOINT:
653 debug ("Endpoint setup packet\n");
654 switch(ao_usb_setup.request) {
655 case AO_USB_REQ_GET_STATUS:
656 ao_usb_ep0_in_queue_byte(0);
657 ao_usb_ep0_in_queue_byte(0);
663 case AO_USB_TYPE_CLASS:
664 debug ("Class setup packet\n");
665 switch (ao_usb_setup.request) {
666 case AO_USB_SET_LINE_CODING:
667 debug ("set line coding\n");
668 ao_usb_ep0_out_set((uint8_t *) &ao_usb_line_coding, 7);
670 case AO_USB_GET_LINE_CODING:
671 debug ("get line coding\n");
672 ao_usb_ep0_in_set((const uint8_t *) &ao_usb_line_coding, 7);
674 case AO_USB_SET_CONTROL_LINE_STATE:
680 /* If we're not waiting to receive data from the host,
681 * queue an IN response
683 if (ao_usb_ep0_state == AO_USB_EP0_DATA_IN)
684 ao_usb_ep0_in_start(ao_usb_setup.length);
688 ao_usb_ep0_handle(uint8_t receive)
690 ao_usb_ep0_receive = 0;
691 if (receive & AO_USB_EP0_GOT_SETUP) {
695 if (receive & AO_USB_EP0_GOT_RX_DATA) {
696 debug ("\tgot rx data\n");
697 if (ao_usb_ep0_state == AO_USB_EP0_DATA_OUT) {
699 if (ao_usb_ep0_out_len == 0) {
700 ao_usb_ep0_state = AO_USB_EP0_DATA_IN;
701 ao_usb_ep0_in_start(0);
705 if (receive & AO_USB_EP0_GOT_TX_ACK) {
706 debug ("\tgot tx ack\n");
708 #if HAS_FLIGHT && AO_USB_FORCE_IDLE
709 ao_flight_force_idle = 1;
711 /* Wait until the IN packet is received from addr 0
712 * before assigning our local address
714 if (ao_usb_address_pending)
715 ao_usb_set_address(ao_usb_address);
716 if (ao_usb_ep0_state == AO_USB_EP0_DATA_IN)
724 stm_usb.cntr |= (1 << STM_USB_CNTR_FSUSP);
726 stm_usb.cntr |= (1 << STM_USB_CNTR_LP_MODE);
734 stm_usb.cntr &= ~(1 << STM_USB_CNTR_FSUSP);
741 uint32_t istr = stm_usb.istr;
743 stm_usb.istr = ~istr;
744 if (istr & (1 << STM_USB_ISTR_CTR)) {
745 uint8_t ep = istr & STM_USB_ISTR_EP_ID_MASK;
746 uint16_t epr, epr_write;
748 /* Preserve the SW write bits, don't mess with most HW writable bits,
749 * clear the CTR_RX and CTR_TX bits
751 epr = stm_usb.epr[ep].r;
753 epr_write &= STM_USB_EPR_PRESERVE_MASK;
754 epr_write |= STM_USB_EPR_INVARIANT;
755 epr_write &= ~(1 << STM_USB_EPR_CTR_RX);
756 epr_write &= ~(1 << STM_USB_EPR_CTR_TX);
757 stm_usb.epr[ep].r = epr_write;
762 if (ao_usb_epr_ctr_rx(epr)) {
763 if (ao_usb_epr_setup(epr))
764 ao_usb_ep0_receive |= AO_USB_EP0_GOT_SETUP;
766 ao_usb_ep0_receive |= AO_USB_EP0_GOT_RX_DATA;
768 if (ao_usb_epr_ctr_tx(epr))
769 ao_usb_ep0_receive |= AO_USB_EP0_GOT_TX_ACK;
770 ao_usb_ep0_handle(ao_usb_ep0_receive);
774 if (ao_usb_epr_ctr_rx(epr)) {
775 _rx_dbg1("RX ISR", epr);
776 ao_usb_out_avail = 1;
777 _rx_dbg0("out avail set");
778 ao_wakeup(AO_USB_OUT_SLEEP_ADDR);
779 _rx_dbg0("stdin awoken");
784 _tx_dbg1("TX ISR", epr);
785 if (ao_usb_epr_ctr_tx(epr)) {
786 ao_usb_in_pending = 0;
787 ao_wakeup(&ao_usb_in_pending);
792 if (ao_usb_epr_ctr_tx(epr))
793 _ao_usb_set_stat_tx(AO_USB_INT_EPR, STM_USB_EPR_STAT_TX_NAK);
799 if (istr & (1 << STM_USB_ISTR_RESET)) {
804 if (istr & (1 << STM_USB_ISTR_SUSP)) {
806 debug ("\tsuspend\n");
809 if (istr & (1 << STM_USB_ISTR_WKUP)) {
810 debug ("\twakeup\n");
815 /* Queue the current IN buffer for transmission */
817 _ao_usb_in_send(void)
819 _tx_dbg0("in_send start");
820 debug ("send %d\n", ao_usb_tx_count);
821 while (ao_usb_in_pending)
822 ao_sleep(&ao_usb_in_pending);
823 ao_usb_in_pending = 1;
824 if (ao_usb_tx_count != AO_USB_IN_SIZE)
825 ao_usb_in_flushed = 1;
826 ao_usb_copy_tx(ao_usb_tx_buffer, ao_usb_in_tx_buffer, ao_usb_tx_count);
827 ao_usb_bdt[AO_USB_IN_EPR].single.addr_tx = ao_usb_in_tx_offset;
828 ao_usb_bdt[AO_USB_IN_EPR].single.count_tx = ao_usb_tx_count;
830 _ao_usb_set_stat_tx(AO_USB_IN_EPR, STM_USB_EPR_STAT_TX_VALID);
831 _tx_dbg0("in_send end");
834 /* Wait for a free IN buffer. Interrupts are blocked */
836 _ao_usb_in_wait(void)
839 /* Check if the current buffer is writable */
840 if (ao_usb_tx_count < AO_USB_IN_SIZE)
843 _tx_dbg0("in_wait top");
844 /* Wait for an IN buffer to be ready */
845 while (ao_usb_in_pending)
846 ao_sleep(&ao_usb_in_pending);
847 _tx_dbg0("in_wait bottom");
857 /* Anytime we've sent a character since
858 * the last time we flushed, we'll need
859 * to send a packet -- the only other time
860 * we would send a packet is when that
861 * packet was full, in which case we now
862 * want to send an empty packet
864 ao_arch_block_interrupts();
865 while (!ao_usb_in_flushed) {
866 _tx_dbg0("flush top");
868 _tx_dbg0("flush end");
870 ao_arch_release_interrupts();
874 ao_usb_putchar(char c)
879 ao_arch_block_interrupts();
882 ao_usb_in_flushed = 0;
883 ao_usb_tx_buffer[ao_usb_tx_count++] = (uint8_t) c;
885 /* Send the packet when full */
886 if (ao_usb_tx_count == AO_USB_IN_SIZE) {
887 _tx_dbg0("putchar full");
889 _tx_dbg0("putchar flushed");
891 ao_arch_release_interrupts();
895 _ao_usb_out_recv(void)
897 _rx_dbg0("out_recv top");
898 ao_usb_out_avail = 0;
900 ao_usb_rx_count = ao_usb_bdt[AO_USB_OUT_EPR].single.count_rx & STM_USB_BDT_COUNT_RX_COUNT_RX_MASK;
902 _rx_dbg1("out_recv count", ao_usb_rx_count);
903 debug ("recv %d\n", ao_usb_rx_count);
904 debug_data("Fill OUT len %d:", ao_usb_rx_count);
905 ao_usb_copy_rx(ao_usb_rx_buffer, ao_usb_out_rx_buffer, ao_usb_rx_count);
910 _ao_usb_set_stat_rx(AO_USB_OUT_EPR, STM_USB_EPR_STAT_RX_VALID);
914 _ao_usb_pollchar(void)
919 return AO_READ_AGAIN;
922 if (ao_usb_rx_pos != ao_usb_rx_count)
925 _rx_dbg0("poll check");
926 /* Check to see if a packet has arrived */
927 if (!ao_usb_out_avail) {
928 _rx_dbg0("poll none");
929 return AO_READ_AGAIN;
934 /* Pull a character out of the fifo */
935 c = ao_usb_rx_buffer[ao_usb_rx_pos++];
944 ao_arch_block_interrupts();
945 while ((c = _ao_usb_pollchar()) == AO_READ_AGAIN)
946 ao_sleep(AO_USB_OUT_SLEEP_ADDR);
947 ao_arch_release_interrupts();
957 buffer = ao_usb_packet_buffer_addr(ao_usb_sram_addr);
958 ao_usb_sram_addr += AO_USB_IN_SIZE;
963 ao_usb_free(uint16_t *addr)
965 uint16_t offset = ao_usb_packet_buffer_offset(addr);
966 if (offset < ao_usb_sram_addr)
967 ao_usb_sram_addr = offset;
971 ao_usb_write(uint16_t *buffer, uint16_t len)
973 ao_arch_block_interrupts();
975 /* Wait for everything to be ready at the same time */
977 /* Make sure USB is connected */
978 if (!ao_usb_running) {
979 ao_sleep(&ao_usb_running);
983 /* Flush any pending regular I/O */
984 if (ao_usb_tx_count) {
989 /* Wait for an idle IN buffer */
990 if (ao_usb_in_pending) {
991 ao_sleep(&ao_usb_in_pending);
997 ao_usb_in_pending = 1;
998 ao_usb_in_flushed = (len != AO_USB_IN_SIZE);
999 ao_usb_bdt[AO_USB_IN_EPR].single.addr_tx = ao_usb_packet_buffer_offset(buffer);
1000 ao_usb_bdt[AO_USB_IN_EPR].single.count_tx = len;
1001 _ao_usb_set_stat_tx(AO_USB_IN_EPR, STM_USB_EPR_STAT_TX_VALID);
1002 ao_arch_release_interrupts();
1007 ao_usb_disable(void)
1009 ao_arch_block_interrupts();
1010 stm_usb.cntr = (1 << STM_USB_CNTR_FRES);
1013 /* Disable USB pull-up */
1014 stm_usb.bcdr &= ~(1 << STM_USB_BCDR_DPPU);
1016 /* Switch off the device */
1017 stm_usb.cntr = (1 << STM_USB_CNTR_PDWN) | (1 << STM_USB_CNTR_FRES);
1019 /* Disable the interface */
1020 stm_rcc.apb1enr &= ~(1 << STM_RCC_APB1ENR_USBEN);
1021 ao_arch_release_interrupts();
1029 /* Select HSI48 as USB clock source */
1030 stm_rcc.cfgr3 &= ~(1 << STM_RCC_CFGR3_USBSW);
1032 /* Enable USB device */
1033 stm_rcc.apb1enr |= (1 << STM_RCC_APB1ENR_USBEN);
1035 /* Clear reset condition */
1036 stm_rcc.apb1rstr &= ~(1 << STM_RCC_APB1RSTR_USBRST);
1038 /* Disable USB pull-up */
1039 stm_usb.bcdr &= ~(1 << STM_USB_BCDR_DPPU);
1041 /* Do not touch the GPIOA configuration; USB takes priority
1042 * over GPIO on pins A11 and A12, but if you select alternate
1043 * input 10 (the documented correct selection), then USB is
1044 * pulled low and doesn't work at all
1047 ao_arch_block_interrupts();
1049 /* Route interrupts */
1050 stm_nvic_set_enable(STM_ISR_USB_POS);
1051 stm_nvic_set_priority(STM_ISR_USB_POS, 3);
1053 ao_usb_configuration = 0;
1055 /* Set up buffer descriptors */
1056 ao_usb_init_btable();
1058 /* Reset the USB controller */
1059 stm_usb.cntr = (1 << STM_USB_CNTR_FRES);
1061 /* Clear the reset bit */
1064 /* Clear any spurious interrupts */
1069 debug ("ao_usb_enable\n");
1071 /* Enable interrupts */
1072 stm_usb.cntr = ((1 << STM_USB_CNTR_CTRM) |
1073 (0 << STM_USB_CNTR_PMAOVRM) |
1074 (0 << STM_USB_CNTR_ERRM) |
1075 (1 << STM_USB_CNTR_WKUPM) |
1076 (1 << STM_USB_CNTR_SUSPM) |
1077 (1 << STM_USB_CNTR_RESETM) |
1078 (0 << STM_USB_CNTR_SOFM) |
1079 (0 << STM_USB_CNTR_ESOFM) |
1080 (0 << STM_USB_CNTR_RESUME) |
1081 (0 << STM_USB_CNTR_FSUSP) |
1082 (0 << STM_USB_CNTR_LP_MODE) |
1083 (0 << STM_USB_CNTR_PDWN) |
1084 (0 << STM_USB_CNTR_FRES));
1086 ao_arch_release_interrupts();
1088 for (t = 0; t < 1000; t++)
1091 /* Enable USB pull-up */
1092 stm_usb.bcdr |= (1 << STM_USB_BCDR_DPPU);
1096 struct ao_task ao_usb_echo_task;
1104 c = ao_usb_getchar();
1115 printf ("control: %d out: %d in: %d int: %d reset: %d suspend %d\n",
1116 control_count, out_count, in_count, int_count, reset_count, suspend_count);
1119 __code struct ao_cmds ao_usb_cmds[] = {
1120 { ao_usb_irq, "I\0Show USB interrupt counts" },
1128 /* Turn on syscfg */
1129 stm_rcc.apb2enr |= (1 << STM_RCC_APB2ENR_SYSCFGCOMPEN);
1131 /* Set PA11/PA12 remapping bit */
1132 stm_syscfg.cfgr1 |= (AO_PA11_PA12_RMP << STM_SYSCFG_CFGR1_PA11_PA12_RMP);
1136 debug ("ao_usb_init\n");
1137 ao_usb_ep0_state = AO_USB_EP0_IDLE;
1139 ao_usb_alloc_buffers();
1142 ao_add_task(&ao_usb_echo_task, ao_usb_echo, "usb echo");
1145 ao_cmd_register(&ao_usb_cmds[0]);
1149 ao_add_stdio(_ao_usb_pollchar, ao_usb_putchar, ao_usb_flush);
1154 #if TX_DBG || RX_DBG
1164 uint32_t in_pending;
1166 uint32_t in_flushed;
1176 #define NUM_USB_DBG 128
1178 static struct ao_usb_dbg dbg[128];
1181 static void _dbg(int line, char *msg, uint32_t value)
1184 dbg[dbg_i].line = line;
1185 dbg[dbg_i].msg = msg;
1186 dbg[dbg_i].value = value;
1187 asm("mrs %0,primask" : "=&r" (primask));
1188 dbg[dbg_i].primask = primask;
1190 dbg[dbg_i].in_count = in_count;
1191 dbg[dbg_i].in_epr = stm_usb.epr[AO_USB_IN_EPR];
1192 dbg[dbg_i].in_pending = ao_usb_in_pending;
1193 dbg[dbg_i].tx_count = ao_usb_tx_count;
1194 dbg[dbg_i].in_flushed = ao_usb_in_flushed;
1197 dbg[dbg_i].rx_count = ao_usb_rx_count;
1198 dbg[dbg_i].rx_pos = ao_usb_rx_pos;
1199 dbg[dbg_i].out_avail = ao_usb_out_avail;
1200 dbg[dbg_i].out_epr = stm_usb.epr[AO_USB_OUT_EPR];
1202 if (++dbg_i == NUM_USB_DBG)