git.gag.com Git - fw/altos/blob - src/stm32f1/stm32f1.h

   1 /*
   2  * Copyright © 2023 Keith Packard <keithp@keithp.com>
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation, either version 2 of the License, or
   7  * (at your option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful, but
  10  * WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  12  * General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along
  15  * with this program; if not, write to the Free Software Foundation, Inc.,
  16  * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
  17  */
  18
  19 #ifndef _STM32F1_H_
  20 #define _STM32F1_H_
  21
  22 #include <stdint.h>
  23
  24 typedef volatile uint32_t       vuint32_t;
  25 typedef volatile uint16_t       vuint16_t;
  26 typedef volatile void *         vvoid_t;
  27
  28 struct stm_rcc {
  29         vuint32_t       cr;
  30         vuint32_t       cfgr;
  31         vuint32_t       cir;
  32         vuint32_t       apb2rstr;
  33
  34         vuint32_t       apb1rstr;
  35         vuint32_t       ahbenr;
  36         vuint32_t       apb2enr;
  37         vuint32_t       apb1enr;
  38
  39         vuint32_t       bdcr;
  40         vuint32_t       csr;
  41         vuint32_t       ahbstr;
  42         vuint32_t       cfgr2;
  43 };
  44
  45 extern struct stm_rcc stm_rcc;
  46
  47 //#define stm_rcc    (*((struct stm_rcc *) 0x40021000))
  48
  49 #define STM_RCC_CR_RTCPRE       (29)
  50 #define  STM_RCC_CR_RTCPRE_HSE_DIV_2    0
  51 #define  STM_RCC_CR_RTCPRE_HSE_DIV_4    1
  52 #define  STM_RCC_CR_RTCPRE_HSE_DIV_8    2
  53 #define  STM_RCC_CR_RTCPRE_HSE_DIV_16   3
  54 #define  STM_RCC_CR_RTCPRE_HSE_MASK     3UL
  55
  56 #define STM_RCC_CR_PLL3RDY      (29)
  57 #define STM_RCC_CR_PLL3ON       (28)
  58 #define STM_RCC_CR_PLL2RDY      (27)
  59 #define STM_RCC_CR_PLL2ON       (26)
  60 #define STM_RCC_CR_PLLRDY       (25)
  61 #define STM_RCC_CR_PLLON        (24)
  62 #define STM_RCC_CR_CSSON        (19)
  63 #define STM_RCC_CR_HSEBYP       (18)
  64 #define STM_RCC_CR_HSERDY       (17)
  65 #define STM_RCC_CR_HSEON        (16)
  66 #define STM_RCC_CR_HSICAL       (8)
  67 #define STM_RCC_CR_HSITRIM      (3)
  68 #define STM_RCC_CR_HSIRDY       (1)
  69 #define STM_RCC_CR_HSION        (0)
  70
  71 #define STM_RCC_CFGR_MCOPRE     (28)
  72 #define  STM_RCC_CFGR_MCOPRE_DIV_1      0
  73 #define  STM_RCC_CFGR_MCOPRE_DIV_2      1
  74 #define  STM_RCC_CFGR_MCOPRE_DIV_4      2
  75 #define  STM_RCC_CFGR_MCOPRE_DIV_8      3
  76 #define  STM_RCC_CFGR_MCOPRE_DIV_16     4
  77 #define  STM_RCC_CFGR_MCOPRE_MASK       7UL
  78
  79 #define STM_RCC_CFGR_MCO        (24)
  80 #define  STM_RCC_CFGR_MCO_DISABLE       0
  81 #define  STM_RCC_CFGR_MCO_SYSCLK        4
  82 #define  STM_RCC_CFGR_MCO_HSI   5
  83 #define  STM_RCC_CFGR_MCO_HSE   6
  84 #define  STM_RCC_CFGR_MCO_PLL_2 7
  85 #define  STM_RCC_CFGR_MCO_MASK  7UL
  86
  87 #define STM_RCC_CFGR_USBPRE     (22)
  88 #define  STM_RCC_CFGR_USBPRE_1_5        0
  89 #define  STM_RCC_CFGR_USBPRE_1          1
  90
  91 #define STM_RCC_CFGR_PLLMUL     (18)
  92 #define  STM_RCC_CFGR_PLLMUL_2          0
  93 #define  STM_RCC_CFGR_PLLMUL_3          1
  94 #define  STM_RCC_CFGR_PLLMUL_4          2
  95 #define  STM_RCC_CFGR_PLLMUL_5          3
  96 #define  STM_RCC_CFGR_PLLMUL_6          4
  97 #define  STM_RCC_CFGR_PLLMUL_7          5
  98 #define  STM_RCC_CFGR_PLLMUL_8          6
  99 #define  STM_RCC_CFGR_PLLMUL_9          7
 100 #define  STM_RCC_CFGR_PLLMUL_10         8
 101 #define  STM_RCC_CFGR_PLLMUL_11         9
 102 #define  STM_RCC_CFGR_PLLMUL_12         10
 103 #define  STM_RCC_CFGR_PLLMUL_13         11
 104 #define  STM_RCC_CFGR_PLLMUL_14         12
 105 #define  STM_RCC_CFGR_PLLMUL_15         13
 106 #define  STM_RCC_CFGR_PLLMUL_16         14
 107 #define  STM_RCC_CFGR_PLLMUL_MASK       0xfUL
 108
 109 #define STM_RCC_CFGR_PLLXTPRE   (17)
 110 #define  STM_RCC_CFGR_PLLXTPRE_1        0
 111 #define  STM_RCC_CFGR_PLLXTPRE_2        1
 112
 113 #define STM_RCC_CFGR_PLLSRC     (16)
 114 #define  STM_RCC_CFGR_PLLSRC_HSI_2      0
 115 #define  STM_RCC_CFGR_PLLSRC_HSE        1
 116
 117 #define STM_RCC_CFGR_ADCPRE     (14)
 118 #define  STM_RCC_CFGR_ADCPRE_2          0
 119 #define  STM_RCC_CFGR_ADCPRE_4          1
 120 #define  STM_RCC_CFGR_ADCPRE_6          2
 121 #define  STM_RCC_CFGR_ADCPRE_8          3
 122
 123 #define STM_RCC_CFGR_PPRE2      (11)
 124 #define  STM_RCC_CFGR_PPRE2_DIV_1       0
 125 #define  STM_RCC_CFGR_PPRE2_DIV_2       4
 126 #define  STM_RCC_CFGR_PPRE2_DIV_4       5
 127 #define  STM_RCC_CFGR_PPRE2_DIV_8       6
 128 #define  STM_RCC_CFGR_PPRE2_DIV_16      7
 129 #define  STM_RCC_CFGR_PPRE2_MASK        7UL
 130
 131 #define STM_RCC_CFGR_PPRE1      (8)
 132 #define  STM_RCC_CFGR_PPRE1_DIV_1       0
 133 #define  STM_RCC_CFGR_PPRE1_DIV_2       4
 134 #define  STM_RCC_CFGR_PPRE1_DIV_4       5
 135 #define  STM_RCC_CFGR_PPRE1_DIV_8       6
 136 #define  STM_RCC_CFGR_PPRE1_DIV_16      7
 137 #define  STM_RCC_CFGR_PPRE1_MASK        7UL
 138
 139 #define STM_RCC_CFGR_HPRE       (4)
 140 #define  STM_RCC_CFGR_HPRE_DIV_1        0
 141 #define  STM_RCC_CFGR_HPRE_DIV_2        8
 142 #define  STM_RCC_CFGR_HPRE_DIV_4        9
 143 #define  STM_RCC_CFGR_HPRE_DIV_8        0xa
 144 #define  STM_RCC_CFGR_HPRE_DIV_16       0xb
 145 #define  STM_RCC_CFGR_HPRE_DIV_64       0xc
 146 #define  STM_RCC_CFGR_HPRE_DIV_128      0xd
 147 #define  STM_RCC_CFGR_HPRE_DIV_256      0xe
 148 #define  STM_RCC_CFGR_HPRE_DIV_512      0xf
 149 #define  STM_RCC_CFGR_HPRE_MASK         0xfUL
 150
 151 #define STM_RCC_CFGR_SWS        (2)
 152 #define  STM_RCC_CFGR_SWS_HSI           0
 153 #define  STM_RCC_CFGR_SWS_HSE           1
 154 #define  STM_RCC_CFGR_SWS_PLL           2
 155 #define  STM_RCC_CFGR_SWS_MASK          3UL
 156
 157 #define STM_RCC_CFGR_SW         (0)
 158 #define  STM_RCC_CFGR_SW_HSI            0
 159 #define  STM_RCC_CFGR_SW_HSE            1
 160 #define  STM_RCC_CFGR_SW_PLL            2
 161 #define  STM_RCC_CFGR_SW_MASK           3UL
 162
 163 #define STM_RCC_AHBENR_CRCEN    6
 164 #define STM_RCC_AHBENR_FLITFEN  4
 165 #define STM_RCC_AHBENR_SRAMEN   2
 166 #define STM_RCC_AHBENR_DMA2EN   1
 167 #define STM_RCC_AHBENR_DMA1EN   0
 168
 169
 170 #define STM_RCC_APB2ENR_USART1EN        14
 171 #define STM_RCC_APB2ENR_SPI1EN          12
 172 #define STM_RCC_APB2ENR_TIM1EN          11
 173 #define STM_RCC_APB2ENR_ADC2EN          10
 174 #define STM_RCC_APB2ENR_ADC1EN          9
 175 #define STM_RCC_APB2ENR_IOPEEN          6
 176 #define STM_RCC_APB2ENR_IOPDEN          5
 177 #define STM_RCC_APB2ENR_IOPCEN          4
 178 #define STM_RCC_APB2ENR_IOPBEN          3
 179 #define STM_RCC_APB2ENR_IOPAEN          2
 180 #define STM_RCC_APB2ENR_AFIOEN          0
 181
 182 #define STM_RCC_APB1ENR_DACEN           29
 183 #define STM_RCC_APB1ENR_PWREN           28
 184 #define STM_RCC_APB1ENR_BKPEN           27
 185 #define STM_RCC_APB1ENR_CANEN           26
 186 #define STM_RCC_APB1ENR_USBEN           23
 187 #define STM_RCC_APB1ENR_I2C2EN          22
 188 #define STM_RCC_APB1ENR_I2C1EN          21
 189 #define STM_RCC_APB1ENR_UART5EN         20
 190 #define STM_RCC_APB1ENR_UART4EN         19
 191 #define STM_RCC_APB1ENR_USART3EN        18
 192 #define STM_RCC_APB1ENR_USART2EN        17
 193 #define STM_RCC_APB1ENR_SPI3EN          15
 194 #define STM_RCC_APB1ENR_SPI2EN          14
 195 #define STM_RCC_APB1ENR_WWDGEN          11
 196 #define STM_RCC_APB1ENR_TIM14EN         8
 197 #define STM_RCC_APB1ENR_TIM13EN         7
 198 #define STM_RCC_APB1ENR_TIM12EN         6
 199 #define STM_RCC_APB1ENR_TIM7EN          5
 200 #define STM_RCC_APB1ENR_TIM6EN          4
 201 #define STM_RCC_APB1ENR_TIM5EN          3
 202 #define STM_RCC_APB1ENR_TIM4EN          2
 203 #define STM_RCC_APB1ENR_TIM3EN          1
 204 #define STM_RCC_APB1ENR_TIM2EN          0
 205
 206 #define STM_RCC_CSR_LPWRRSTF            (31)
 207 #define STM_RCC_CSR_WWDGRSTF            (30)
 208 #define STM_RCC_CSR_IWDGRSTF            (29)
 209 #define STM_RCC_CSR_SFTRSTF             (28)
 210 #define STM_RCC_CSR_PORRSTF             (27)
 211 #define STM_RCC_CSR_PINRSTF             (26)
 212 #define STM_RCC_CSR_RMVF                (24)
 213 #define STM_RCC_CSR_LSIRDY              (1)
 214 #define STM_RCC_CSR_LSION               (0)
 215
 216 struct stm_systick {
 217         vuint32_t       ctrl;
 218         vuint32_t       load;
 219         vuint32_t       val;
 220         vuint32_t       calib;
 221 };
 222
 223 extern struct stm_systick stm_systick;
 224
 225 //#define stm_systick   (*((struct stm_systick *) 0xe000e010))
 226
 227 #define STM_SYSTICK_CTRL_ENABLE         0
 228 #define STM_SYSTICK_CTRL_TICKINT        1
 229 #define STM_SYSTICK_CTRL_CLKSOURCE      2
 230 #define  STM_SYSTICK_CTRL_CLKSOURCE_HCLK_8              0
 231 #define  STM_SYSTICK_CTRL_CLKSOURCE_HCLK                1
 232 #define STM_SYSTICK_CTRL_COUNTFLAG      16
 233
 234 /* The NVIC starts at 0xe000e100, so add that to the offsets to find the absolute address */
 235
 236 struct stm_nvic {
 237         vuint32_t       iser[3];        /* 0x000 0xe000e100 Set Enable Register */
 238
 239         uint8_t         _unused00c[0x080 - 0x00c];
 240
 241         vuint32_t       icer[3];        /* 0x080 0xe000e180 Clear Enable Register */
 242
 243         uint8_t         _unused08c[0x100 - 0x08c];
 244
 245         vuint32_t       ispr[3];        /* 0x100 0xe000e200 Set Pending Register */
 246
 247         uint8_t         _unused10c[0x180 - 0x10c];
 248
 249         vuint32_t       icpr[3];        /* 0x180 0xe000e280 Clear Pending Register */
 250
 251         uint8_t         _unused18c[0x200 - 0x18c];
 252
 253         vuint32_t       iabr[3];        /* 0x200 0xe000e300 Active Bit Register */
 254
 255         uint8_t         _unused20c[0x300 - 0x20c];
 256
 257         vuint32_t       ipr[31];        /* 0x300 0xe000e400 Priority Register */
 258
 259         uint8_t         _unused37c[0xe00 - 0x37c];      /* covers SCB */
 260
 261         vuint32_t       stir;           /* 0xe00 0xe000ee00 Software Trigger Interrupt Register */
 262 };
 263
 264 extern struct stm_nvic stm_nvic;
 265
 266 //#define stm_nvic (*((struct stm_nvic *) 0xe000e100))
 267
 268 #define IRQ_REG(irq)    ((irq) >> 5)
 269 #define IRQ_BIT(irq)    ((irq) & 0x1f)
 270 #define IRQ_MASK(irq)   (1 << IRQ_BIT(irq))
 271 #define IRQ_BOOL(v,irq) (((v) >> IRQ_BIT(irq)) & 1)
 272
 273 static inline void
 274 stm_nvic_set_enable(int irq) {
 275         stm_nvic.iser[IRQ_REG(irq)] = IRQ_MASK(irq);
 276 }
 277
 278 static inline void
 279 stm_nvic_clear_enable(int irq) {
 280         stm_nvic.icer[IRQ_REG(irq)] = IRQ_MASK(irq);
 281 }
 282
 283 static inline int
 284 stm_nvic_enabled(int irq) {
 285         return IRQ_BOOL(stm_nvic.iser[IRQ_REG(irq)], irq);
 286 }
 287
 288 static inline void
 289 stm_nvic_set_pending(int irq) {
 290         stm_nvic.ispr[IRQ_REG(irq)] = IRQ_MASK(irq);
 291 }
 292
 293 static inline void
 294 stm_nvic_clear_pending(int irq) {
 295         stm_nvic.icpr[IRQ_REG(irq)] = IRQ_MASK(irq);
 296 }
 297
 298 static inline int
 299 stm_nvic_pending(int irq) {
 300         return IRQ_BOOL(stm_nvic.ispr[IRQ_REG(irq)], irq);
 301 }
 302
 303 static inline int
 304 stm_nvic_active(int irq) {
 305         return IRQ_BOOL(stm_nvic.iabr[IRQ_REG(irq)], irq);
 306 }
 307
 308 #define IRQ_PRIO_REG(irq)       ((irq) >> 2)
 309 #define IRQ_PRIO_BIT(irq)       (((irq) & 3) << 3)
 310 #define IRQ_PRIO_MASK(irq)      (0xff << IRQ_PRIO_BIT(irq))
 311
 312 static inline void
 313 stm_nvic_set_priority(int irq, uint8_t prio) {
 314         int             n = IRQ_PRIO_REG(irq);
 315         uint32_t        v;
 316
 317         v = stm_nvic.ipr[n];
 318         v &= (uint32_t) ~IRQ_PRIO_MASK(irq);
 319         v |= (prio) << IRQ_PRIO_BIT(irq);
 320         stm_nvic.ipr[n] = v;
 321 }
 322
 323 static inline uint8_t
 324 stm_nvic_get_priority(int irq) {
 325         return (stm_nvic.ipr[IRQ_PRIO_REG(irq)] >> IRQ_PRIO_BIT(irq)) & IRQ_PRIO_MASK(0);
 326 }
 327
 328 struct stm_scb {
 329         vuint32_t       cpuid;
 330         vuint32_t       icsr;
 331         vuint32_t       vtor;
 332         vuint32_t       aircr;
 333
 334         vuint32_t       scr;
 335         vuint32_t       ccr;
 336         vuint32_t       shpr1;
 337         vuint32_t       shpr2;
 338
 339         vuint32_t       shpr3;
 340         vuint32_t       shcrs;
 341         vuint32_t       cfsr;
 342         vuint32_t       hfsr;
 343
 344         uint32_t        unused_30;
 345         vuint32_t       mmar;
 346         vuint32_t       bfar;
 347 };
 348
 349 extern struct stm_scb stm_scb;
 350
 351 #define STM_SCB_AIRCR_VECTKEY           16
 352 #define  STM_SCB_AIRCR_VECTKEY_KEY              0x05fa
 353 #define STM_SCB_AIRCR_PRIGROUP          8
 354 #define STM_SCB_AIRCR_SYSRESETREQ       2
 355 #define STM_SCB_AIRCR_VECTCLRACTIVE     1
 356 #define STM_SCB_AIRCR_VECTRESET         0
 357
 358 struct stm_dbgmcu {
 359         uint32_t        idcode;
 360 };
 361
 362 extern struct stm_dbgmcu        stm_dbgmcu;
 363
 364 static inline uint16_t
 365 stm_dev_id(void) {
 366         return stm_dbgmcu.idcode & 0xfff;
 367 }
 368
 369 struct stm_flash {
 370         vuint32_t       acr;
 371         vuint32_t       keyr;
 372         vuint32_t       optkeyr;
 373         vuint32_t       sr;
 374
 375         vuint32_t       cr;
 376         vuint32_t       ar;
 377         uint32_t        _unused018;
 378         vuint32_t       obr;
 379
 380         vuint32_t       wrpr;
 381 };
 382
 383 extern struct stm_flash stm_flash;
 384
 385 //#define stm_flash (*((struct stm_flash *) 0x40022000))
 386
 387 #define STM_FLASH_ACR_PRFTBS    5
 388 #define STM_FLASH_ACR_PRFTBE    4
 389 #define STM_FLASH_ACR_HLFCYA    3
 390 #define STM_FLASH_ACR_LATENCY   0
 391 #define  STM_FLASH_ACR_LATENCY_0        0
 392 #define  STM_FLASH_ACR_LATENCY_1        1
 393 #define  STM_FLASH_ACR_LATENCY_2        2
 394
 395 #define STM_FLASH_SR_EOP        5
 396 #define STM_FLASH_SR_WRPRTERR   4
 397 #define STM_FLASH_SR_PGERR      2
 398 #define STM_FLASH_SR_BSY        0
 399
 400 #define STM_FLASH_CR_EOPIE      12
 401 #define STM_FLASH_CR_ERRIE      10
 402 #define STM_FLASH_CR_OPTWRE     9
 403 #define STM_FLASH_CR_LOCK       7
 404 #define STM_FLASH_CR_STRT       6
 405 #define STM_FLASH_CR_OPTER      5
 406 #define STM_FLASH_CR_OPTPG      4
 407 #define STM_FLASH_CR_MER        2
 408 #define STM_FLASH_CR_PER        1
 409 #define STM_FLASH_CR_PG         0
 410
 411 #define STM_FLASH_RDPRT_KEY     0x00A5
 412 #define STM_FLASH_KEYR_KEY1     0x45670123
 413 #define STM_FLASH_KEYR_KEY2     0xCDEF89AB
 414
 415
 416 struct stm_flash_data {
 417         vuint16_t       f_size;
 418         vuint16_t       unused02;
 419         vuint32_t       unused04;
 420         vuint32_t       device_id[3];
 421 };
 422
 423 extern struct stm_flash_data    stm_flash_data;
 424
 425 static inline uint32_t stm_flash_size(void) { return (uint32_t) stm_flash_data.f_size * 1024; }
 426
 427 //#define stm_flash_data        (*((struct stm_flash_data *) 0x1ffff7e0))
 428
 429 struct stm_gpio {
 430         vuint32_t       cr[2];
 431         vuint32_t       idr;
 432         vuint32_t       odr;
 433
 434         vuint32_t       bsrr;
 435         vuint32_t       brr;
 436         vuint32_t       lckr;
 437 };
 438
 439 #define STM_GPIO_CR(y)          ((uint8_t) (y) >> 3)
 440 #define STM_GPIO_CR_CNF(y)      ((((uint8_t) (y) & 7) << 2) + 2)
 441 #define  STM_GPIO_CR_CNF_INPUT_ANALOG           0
 442 #define  STM_GPIO_CR_CNF_INPUT_FLOATING         1
 443 #define  STM_GPIO_CR_CNF_INPUT_PULL             2
 444 #define  STM_GPIO_CR_CNF_OUTPUT_PUSH_PULL       0
 445 #define  STM_GPIO_CR_CNF_OUTPUT_OPEN_DRAIN      1
 446 #define  STM_GPIO_CR_CNF_OUTPUT_AF_PUSH_PULL    2
 447 #define  STM_GPIO_CR_CNF_OUTPUT_AF_OPEN_DRAIN   3
 448 #define  STM_GPIO_CR_CNF_MASK                   3U
 449 #define STM_GPIO_CR_MODE(y)     ((((y) & 7) << 2))
 450 #define  STM_GPIO_CR_MODE_INPUT                 0
 451 #define  STM_GPIO_CR_MODE_OUTPUT_10MHZ          1
 452 #define  STM_GPIO_CR_MODE_OUTPUT_2MHZ           2
 453 #define  STM_GPIO_CR_MODE_OUTPUT_50MHZ          3
 454 #define  STM_GPIO_CR_MODE_MASK                  3U
 455
 456 static inline void
 457 stm_gpio_conf(struct stm_gpio *gpio, int pin, uint8_t mode, uint8_t cnf)
 458 {
 459         uint8_t         cr = STM_GPIO_CR(pin);
 460         uint32_t        v = gpio->cr[cr];
 461
 462         v &= ~((STM_GPIO_CR_CNF_MASK << STM_GPIO_CR_CNF(pin)) |
 463                (STM_GPIO_CR_MODE_MASK << STM_GPIO_CR_MODE(pin)));
 464         v |= (mode << STM_GPIO_CR_MODE(pin)) | (cnf << STM_GPIO_CR_CNF(pin));
 465         gpio->cr[cr] = v;
 466 }
 467
 468 static inline void
 469 stm_gpio_set(struct stm_gpio *gpio, int pin, uint8_t value) {
 470         /* Use the bit set/reset register to do this atomically */
 471         gpio->bsrr = ((uint32_t) (value ^ 1) << (pin + 16)) | ((uint32_t) value << pin);
 472 }
 473
 474 static inline void
 475 stm_gpio_set_mask(struct stm_gpio *gpio, uint16_t bits, uint16_t mask) {
 476         /* Use the bit set/reset register to do this atomically */
 477         gpio->bsrr = ((uint32_t) (~bits & mask) << 16) | ((uint32_t) (bits & mask));
 478 }
 479
 480 static inline void
 481 stm_gpio_set_bits(struct stm_gpio *gpio, uint16_t bits) {
 482         gpio->bsrr = bits;
 483 }
 484
 485 static inline void
 486 stm_gpio_clr_bits(struct stm_gpio *gpio, uint16_t bits) {
 487         gpio->bsrr = ((uint32_t) bits) << 16;
 488 }
 489
 490 static inline uint8_t
 491 stm_gpio_get(struct stm_gpio *gpio, int pin) {
 492         return (gpio->idr >> pin) & 1;
 493 }
 494
 495 static inline uint16_t
 496 stm_gpio_get_all(struct stm_gpio *gpio) {
 497         return (uint16_t) gpio->idr;
 498 }
 499
 500 extern struct stm_gpio stm_gpioa;
 501 extern struct stm_gpio stm_gpiob;
 502 extern struct stm_gpio stm_gpioc;
 503 extern struct stm_gpio stm_gpiod;
 504 extern struct stm_gpio stm_gpioe;
 505
 506 #define stm_gpioe  (*((struct stm_gpio *) 0x40011800))
 507 #define stm_gpiod  (*((struct stm_gpio *) 0x40011400))
 508 #define stm_gpioc  (*((struct stm_gpio *) 0x40011000))
 509 #define stm_gpiob  (*((struct stm_gpio *) 0x40010c00))
 510 #define stm_gpioa  (*((struct stm_gpio *) 0x40010800))
 511
 512 struct stm_afio {
 513         vuint32_t       evcr;
 514         vuint32_t       mapr;
 515         vuint32_t       exticr[4];
 516         vuint32_t       mapr2;
 517 };
 518
 519 extern struct stm_afio stm_afio;
 520
 521 #define stm_afio        (*((struct stm_afio *) 0x40010000))
 522
 523 #define STM_AFIO_MAPR_ADC2_ETRGREG_REMAP        20
 524 #define STM_AFIO_MAPR_ADC2_ETRGINJ_REMAP        19
 525 #define STM_AFIO_MAPR_ADC1_ETRGREG_REMAP        18
 526 #define STM_AFIO_MAPR_ADC1_ETRGINJ_REMAP        17
 527 #define STM_AFIO_MAPR_TIM5CH4_IREMAP            16
 528 #define STM_AFIO_MAPR_PD01_REMAP                15
 529 #define STM_AFIO_MAPR_CAN_REMAP                 13
 530 #define  STM_AFIO_MAPR_CAN_REMAP_PA11_PA12              0
 531 #define  STM_AFIO_MAPR_CAN_REMAP_PB8_PB9                2
 532 #define  STM_AFIO_MAPR_CAN_REMAP_PD0_PD1                3
 533 #define  STM_AFIO_MAPR_CAN_REMAP_MASK                   3
 534 #define STM_AFIO_MAPR_TIM4_REMAP                12
 535 #define STM_AFIO_MAPR_TIM3_REMAP                10
 536 #define  STM_AFIO_MAPR_TIM3_REMAP_PA6_PA7_PB0_PB1       0
 537 #define  STM_AFIO_MAPR_TIM3_REMAP_PB4_PB5_PB0_PB1       2
 538 #define  STM_AFIO_MAPR_TIM3_REMAP_PC6_PC7_PC8_PC9       3
 539 #define  STM_AFIO_MAPR_TIM3_REMAP_MASK                  3
 540 #define STM_AFIO_MAPR_TIM2_REMAP                8
 541 #define  STM_AFIO_MAPR_TIM2_REMAP_PA0_PA1_PA2_PA3       0
 542 #define  STM_AFIO_MAPR_TIM2_REMAP_PA15_PB3_PA2_PA3      1
 543 #define  STM_AFIO_MAPR_TIM2_REMAP_PA0_PA1_PB10_PB11     2
 544 #define  STM_AFIO_MAPR_TIM2_REMAP_PA15_PB3_PB10_PB11    3
 545 #define  STM_AFIO_MAPR_TIM2_REMAP_MASK                  3
 546 #define STM_AFIO_MAPR_TIM1_REMAP                6
 547 #define  STM_AFIO_MAPR_TIM1_REMAP_PA12_PA8_PA9_PA10_PA11_PB12_PB13_PB14_PB15    0
 548 #define  STM_AFIO_MAPR_TIM1_REMAP_PA12_PA8_PA9_PA10_PA11_PA6_PA7_PB0_PB1        1
 549 #define  STM_AFIO_MAPR_TIM1_REMAP_PE7_PE9_PE11_PE13_PE14_PE15_PE8_PE10_PE12     3
 550 #define  STM_AFIO_MAPR_TIM1_REMAP_MASK                                          3
 551 #define STM_AFIO_MAPR_USART3_REMAP              4
 552 #define  STM_AFIO_MAPR_USART3_REMAP_PB10_PB11_PB12_PB13_PB14    0
 553 #define  STM_AFIO_MAPR_USART3_REMAP_PC10_PC11_PC12_PB13_PB14    1
 554 #define  STM_AFIO_MAPR_USART3_REMAP_PD8_PD9_PD10_PD11_PD12      3
 555 #define  STM_AFIO_MAPR_USART3_REMAP_MASK                        3
 556 #define STM_AFIO_MAPR_USART2_REMAP              3
 557 #define  STM_AFIO_MAPR_USART2_REMAP_PA0_PA1_PA2_PA3_PA4 0
 558 #define  STM_AFIO_MAPR_USART2_REMAP_PD3_PD4_PD5_PD6_PD7 1
 559 #define  STM_AFIO_MAPR_USART2_REMAP_MASK                1
 560 #define STM_AFIO_MAPR_USART1_REMAP              2
 561 #define  STM_AFIO_MAPR_USART1_REMAP_PA9_PA10            0
 562 #define  STM_AFIO_MAPR_USART1_REMAP_PB6_PB7             1
 563 #define  STM_AFIO_MAPR_USART1_REMAP_MASK                1
 564 #define STM_AFIO_MAPR_I2C1_REMAP                1
 565 #define  STM_AFIO_MAPR_I2C1_REMAP_PB6_PB7               0
 566 #define  STM_AFIO_MAPR_I2C1_REMAP_PB8_PB9               1
 567 #define  STM_AFIO_MAPR_I2C1_REMAP_MASK                  1
 568 #define STM_AFIO_MAPR_SPI1_REMAP                0
 569 #define  STM_AFIO_MAPR_SPI1_REMAP_PA4_PA5_PA6_PA7       0
 570 #define  STM_AFIO_MAPR_SPI1_REMAP_PA15_PB3_PB4_PB5      1
 571 #define  STM_AFIO_MAPR_SPI1_REMAP_MASK                  1
 572
 573 #define STM_AFIO_EXTICR_PA              0
 574 #define STM_AFIO_EXTICR_PB              1
 575 #define STM_AFIO_EXTICR_PC              2
 576 #define STM_AFIO_EXTICR_PD              3
 577 #define STM_AFIO_EXTICR_PE              4
 578 #define STM_AFIO_EXTICR_PF              5
 579 #define STM_AFIO_EXTICR_PG              6
 580
 581 static inline void
 582 stm_set_afio_mapr(uint8_t bit, uint32_t val, uint32_t mask) {
 583         uint32_t        mapr = stm_afio.mapr;
 584
 585         mapr &= ~(mask << bit);
 586         mapr |= (val << bit);
 587         stm_afio.mapr = mapr;
 588 }
 589
 590 struct stm_usart {
 591         vuint32_t       sr;     /* status register */
 592         vuint32_t       dr;     /* data register */
 593         vuint32_t       brr;    /* baud rate register */
 594         vuint32_t       cr1;    /* control register 1 */
 595
 596         vuint32_t       cr2;    /* control register 2 */
 597         vuint32_t       cr3;    /* control register 3 */
 598         vuint32_t       gtpr;   /* guard time and prescaler */
 599 };
 600
 601 extern struct stm_usart stm_usart1;
 602 extern struct stm_usart stm_usart2;
 603 extern struct stm_usart stm_usart3;
 604
 605 //#define stm_usart1    (*((struct stm_usart *) 0x40013800))
 606 //#define stm_usart2    (*((struct stm_usart *) 0x40004800))
 607 //#define stm_usart3    (*((struct stm_usart *) 0x40004400))
 608
 609 #define STM_USART_SR_CTS        (9)     /* CTS flag */
 610 #define STM_USART_SR_LBD        (8)     /* LIN break detection flag */
 611 #define STM_USART_SR_TXE        (7)     /* Transmit data register empty */
 612 #define STM_USART_SR_TC         (6)     /* Transmission complete */
 613 #define STM_USART_SR_RXNE       (5)     /* Read data register not empty */
 614 #define STM_USART_SR_IDLE       (4)     /* IDLE line detected */
 615 #define STM_USART_SR_ORE        (3)     /* Overrun error */
 616 #define STM_USART_SR_NE         (2)     /* Noise detected flag */
 617 #define STM_USART_SR_FE         (1)     /* Framing error */
 618 #define STM_USART_SR_PE         (0)     /* Parity error */
 619
 620 #define STM_USART_BRR_DIV_MANTISSA      (4)
 621 #define STM_USART_BRR_DIV_FRACTION      (0)
 622
 623 #define STM_USART_CR1_UE        (13)    /* USART enable */
 624 #define STM_USART_CR1_M         (12)    /* Word length */
 625 #define STM_USART_CR1_WAKE      (11)    /* Wakeup method */
 626 #define STM_USART_CR1_PCE       (10)    /* Parity control enable */
 627 #define STM_USART_CR1_PS        (9)     /* Parity selection */
 628 #define STM_USART_CR1_PEIE      (8)     /* PE interrupt enable */
 629 #define STM_USART_CR1_TXEIE     (7)     /* TXE interrupt enable */
 630 #define STM_USART_CR1_TCIE      (6)     /* Transmission complete interrupt enable */
 631 #define STM_USART_CR1_RXNEIE    (5)     /* RXNE interrupt enable */
 632 #define STM_USART_CR1_IDLEIE    (4)     /* IDLE interrupt enable */
 633 #define STM_USART_CR1_TE        (3)     /* Transmitter enable */
 634 #define STM_USART_CR1_RE        (2)     /* Receiver enable */
 635 #define STM_USART_CR1_RWU       (1)     /* Receiver wakeup */
 636 #define STM_USART_CR1_SBK       (0)     /* Send break */
 637
 638 #define STM_USART_CR2_LINEN     (14)    /* LIN mode enable */
 639 #define STM_USART_CR2_STOP      (12)    /* STOP bits */
 640 #define STM_USART_CR2_STOP_MASK 3UL
 641 #define STM_USART_CR2_STOP_1    0
 642 #define STM_USART_CR2_STOP_0_5  1
 643 #define STM_USART_CR2_STOP_2    2
 644 #define STM_USART_CR2_STOP_1_5  3
 645
 646 #define STM_USART_CR2_CLKEN     (11)    /* Clock enable */
 647 #define STM_USART_CR2_CPOL      (10)    /* Clock polarity */
 648 #define STM_USART_CR2_CPHA      (9)     /* Clock phase */
 649 #define STM_USART_CR2_LBCL      (8)     /* Last bit clock pulse */
 650 #define STM_USART_CR2_LBDIE     (6)     /* LIN break detection interrupt enable */
 651 #define STM_USART_CR2_LBDL      (5)     /* lin break detection length */
 652 #define STM_USART_CR2_ADD       (0)
 653 #define STM_USART_CR2_ADD_MASK  0xfUL
 654
 655 #define STM_USART_CR3_CTSIE     (10)    /* CTS interrupt enable */
 656 #define STM_USART_CR3_CTSE      (9)     /* CTS enable */
 657 #define STM_USART_CR3_RTSE      (8)     /* RTS enable */
 658 #define STM_USART_CR3_DMAT      (7)     /* DMA enable transmitter */
 659 #define STM_USART_CR3_DMAR      (6)     /* DMA enable receiver */
 660 #define STM_USART_CR3_SCEN      (5)     /* Smartcard mode enable */
 661 #define STM_USART_CR3_NACK      (4)     /* Smartcard NACK enable */
 662 #define STM_USART_CR3_HDSEL     (3)     /* Half-duplex selection */
 663 #define STM_USART_CR3_IRLP      (2)     /* IrDA low-power */
 664 #define STM_USART_CR3_IREN      (1)     /* IrDA mode enable */
 665 #define STM_USART_CR3_EIE       (0)     /* Error interrupt enable */
 666
 667 struct stm_usb {
 668         vuint32_t       epr[8];
 669         uint8_t         reserved_20[0x40 - 0x20];
 670         vuint32_t       cntr;
 671         vuint32_t       istr;
 672         vuint32_t       fnr;
 673         vuint32_t       daddr;
 674         vuint32_t       btable;
 675 };
 676
 677 /*
 678  * USB DM: PA11
 679  * USB DP: PA12
 680  *
 681  * Need a pull-up on a separate GPIO
 682  */
 683 #define STM_USB_EPR_CTR_RX      15
 684 #define  STM_USB_EPR_CTR_RX_WRITE_INVARIANT             1
 685 #define STM_USB_EPR_DTOG_RX     14
 686 #define STM_USB_EPR_DTOG_RX_WRITE_INVARIANT             0
 687 #define STM_USB_EPR_STAT_RX     12
 688 #define  STM_USB_EPR_STAT_RX_DISABLED                   0
 689 #define  STM_USB_EPR_STAT_RX_STALL                      1
 690 #define  STM_USB_EPR_STAT_RX_NAK                        2
 691 #define  STM_USB_EPR_STAT_RX_VALID                      3
 692 #define  STM_USB_EPR_STAT_RX_MASK                       3UL
 693 #define  STM_USB_EPR_STAT_RX_WRITE_INVARIANT            0
 694 #define STM_USB_EPR_SETUP       11
 695 #define STM_USB_EPR_EP_TYPE     9
 696 #define  STM_USB_EPR_EP_TYPE_BULK                       0
 697 #define  STM_USB_EPR_EP_TYPE_CONTROL                    1
 698 #define  STM_USB_EPR_EP_TYPE_ISO                        2
 699 #define  STM_USB_EPR_EP_TYPE_INTERRUPT                  3
 700 #define  STM_USB_EPR_EP_TYPE_MASK                       3UL
 701 #define STM_USB_EPR_EP_KIND     8
 702 #define  STM_USB_EPR_EP_KIND_DBL_BUF                    1       /* Bulk */
 703 #define  STM_USB_EPR_EP_KIND_STATUS_OUT                 1       /* Control */
 704 #define STM_USB_EPR_CTR_TX      7
 705 #define  STM_USB_CTR_TX_WRITE_INVARIANT                 1
 706 #define STM_USB_EPR_DTOG_TX     6
 707 #define  STM_USB_EPR_DTOG_TX_WRITE_INVARIANT            0
 708 #define STM_USB_EPR_STAT_TX     4
 709 #define  STM_USB_EPR_STAT_TX_DISABLED                   0
 710 #define  STM_USB_EPR_STAT_TX_STALL                      1
 711 #define  STM_USB_EPR_STAT_TX_NAK                        2
 712 #define  STM_USB_EPR_STAT_TX_VALID                      3
 713 #define  STM_USB_EPR_STAT_TX_WRITE_INVARIANT            0
 714 #define  STM_USB_EPR_STAT_TX_MASK                       3UL
 715 #define STM_USB_EPR_EA          0
 716 #define  STM_USB_EPR_EA_MASK                            0xfUL
 717
 718 #define STM_USB_CNTR_CTRM       15
 719 #define STM_USB_CNTR_PMAOVRM    14
 720 #define STM_USB_CNTR_ERRM       13
 721 #define STM_USB_CNTR_WKUPM      12
 722 #define STM_USB_CNTR_SUSPM      11
 723 #define STM_USB_CNTR_RESETM     10
 724 #define STM_USB_CNTR_SOFM       9
 725 #define STM_USB_CNTR_ESOFM      8
 726 #define STM_USB_CNTR_RESUME     4
 727 #define STM_USB_CNTR_FSUSP      3
 728 #define STM_USB_CNTR_LP_MODE    2
 729 #define STM_USB_CNTR_PDWN       1
 730 #define STM_USB_CNTR_FRES       0
 731
 732 #define STM_USB_ISTR_CTR        15
 733 #define STM_USB_ISTR_PMAOVR     14
 734 #define STM_USB_ISTR_ERR        13
 735 #define STM_USB_ISTR_WKUP       12
 736 #define STM_USB_ISTR_SUSP       11
 737 #define STM_USB_ISTR_RESET      10
 738 #define STM_USB_ISTR_SOF        9
 739 #define STM_USB_ISTR_ESOF       8
 740 #define STM_USB_ISTR_DIR        4
 741 #define STM_USB_ISTR_EP_ID      0
 742 #define  STM_USB_ISTR_EP_ID_MASK                0xfUL
 743
 744 #define STM_USB_FNR_RXDP        15
 745 #define STM_USB_FNR_RXDM        14
 746 #define STM_USB_FNR_LCK         13
 747 #define STM_USB_FNR_LSOF        11
 748 #define  STM_USB_FNR_LSOF_MASK                  0x3UL
 749 #define STM_USB_FNR_FN          0
 750 #define  STM_USB_FNR_FN_MASK                    0x7ffUL
 751
 752 #define STM_USB_DADDR_EF        7
 753 #define STM_USB_DADDR_ADD       0
 754 #define  STM_USB_DADDR_ADD_MASK                 0x7fUL
 755
 756 extern struct stm_usb stm_usb;
 757
 758 #define stm_usb (*((struct stm_usb *) 0x40005c00))
 759
 760 union stm_usb_bdt {
 761         struct {
 762                 vuint32_t       addr_tx;
 763                 vuint32_t       count_tx;
 764                 vuint32_t       addr_rx;
 765                 vuint32_t       count_rx;
 766         } single;
 767         struct {
 768                 vuint32_t       addr;
 769                 vuint32_t       count;
 770         } double_tx[2];
 771         struct {
 772                 vuint32_t       addr;
 773                 vuint32_t       count;
 774         } double_rx[2];
 775 };
 776
 777 #define STM_USB_BDT_COUNT_RX_BL_SIZE    15
 778 #define STM_USB_BDT_COUNT_RX_NUM_BLOCK  10
 779 #define  STM_USB_BDT_COUNT_RX_NUM_BLOCK_MASK    0x1fUL
 780 #define STM_USB_BDT_COUNT_RX_COUNT_RX   0
 781 #define  STM_USB_BDT_COUNT_RX_COUNT_RX_MASK     0x3ffUL
 782
 783 #define STM_USB_BDT_SIZE        8
 784
 785 extern uint8_t stm_usb_sram[] __attribute__ ((aligned(4)));
 786
 787 //#define stm_usb_sram ((uint8_t *)0x40006000)
 788
 789 struct stm_dma_channel {
 790         vuint32_t       ccr;
 791         vuint32_t       cndtr;
 792         vvoid_t         cpar;
 793         vvoid_t         cmar;
 794         vuint32_t       reserved;
 795 };
 796
 797 #define STM_NUM_DMA     7
 798
 799 struct stm_dma {
 800         vuint32_t               isr;
 801         vuint32_t               ifcr;
 802         struct stm_dma_channel  channel[STM_NUM_DMA];
 803 };
 804
 805 extern struct stm_dma stm_dma;
 806
 807 #define stm_dma (*((struct stm_dma *) 0x40020000))
 808
 809 /* DMA channels go from 1 to 7, instead of 0 to 6 (sigh)
 810  */
 811
 812 #define STM_DMA_INDEX(channel)          ((channel) - 1)
 813
 814 #define STM_DMA_ISR(index)              ((index) << 2)
 815 #define STM_DMA_ISR_MASK                        0xfUL
 816 #define STM_DMA_ISR_TEIF                        3
 817 #define STM_DMA_ISR_HTIF                        2
 818 #define STM_DMA_ISR_TCIF                        1
 819 #define STM_DMA_ISR_GIF                         0
 820
 821 #define STM_DMA_IFCR(index)             ((index) << 2)
 822 #define STM_DMA_IFCR_MASK                       0xfUL
 823 #define STM_DMA_IFCR_CTEIF                      3
 824 #define STM_DMA_IFCR_CHTIF                      2
 825 #define STM_DMA_IFCR_CTCIF                      1
 826 #define STM_DMA_IFCR_CGIF                       0
 827
 828 #define STM_DMA_CCR_MEM2MEM             (14)
 829
 830 #define STM_DMA_CCR_PL                  (12)
 831 #define  STM_DMA_CCR_PL_LOW                     (0)
 832 #define  STM_DMA_CCR_PL_MEDIUM                  (1)
 833 #define  STM_DMA_CCR_PL_HIGH                    (2)
 834 #define  STM_DMA_CCR_PL_VERY_HIGH               (3)
 835 #define  STM_DMA_CCR_PL_MASK                    (3)
 836
 837 #define STM_DMA_CCR_MSIZE               (10)
 838 #define  STM_DMA_CCR_MSIZE_8                    (0)
 839 #define  STM_DMA_CCR_MSIZE_16                   (1)
 840 #define  STM_DMA_CCR_MSIZE_32                   (2)
 841 #define  STM_DMA_CCR_MSIZE_MASK                 (3)
 842
 843 #define STM_DMA_CCR_PSIZE               (8)
 844 #define  STM_DMA_CCR_PSIZE_8                    (0)
 845 #define  STM_DMA_CCR_PSIZE_16                   (1)
 846 #define  STM_DMA_CCR_PSIZE_32                   (2)
 847 #define  STM_DMA_CCR_PSIZE_MASK                 (3)
 848
 849 #define STM_DMA_CCR_MINC                (7)
 850 #define STM_DMA_CCR_PINC                (6)
 851 #define STM_DMA_CCR_CIRC                (5)
 852 #define STM_DMA_CCR_DIR                 (4)
 853 #define  STM_DMA_CCR_DIR_PER_TO_MEM             0
 854 #define  STM_DMA_CCR_DIR_MEM_TO_PER             1
 855 #define STM_DMA_CCR_TEIE                (3)
 856 #define STM_DMA_CCR_HTIE                (2)
 857 #define STM_DMA_CCR_TCIE                (1)
 858 #define STM_DMA_CCR_EN                  (0)
 859
 860 #define STM_DMA_CHANNEL_ADC1            1
 861 #define STM_DMA_CHANNEL_SPI1_RX         2
 862 #define STM_DMA_CHANNEL_SPI1_TX         3
 863 #define STM_DMA_CHANNEL_SPI2_RX         4
 864 #define STM_DMA_CHANNEL_SPI2_TX         5
 865 #define STM_DMA_CHANNEL_USART3_TX       2
 866 #define STM_DMA_CHANNEL_USART3_RX       3
 867 #define STM_DMA_CHANNEL_USART1_TX       4
 868 #define STM_DMA_CHANNEL_USART1_RX       5
 869 #define STM_DMA_CHANNEL_USART2_RX       6
 870 #define STM_DMA_CHANNEL_USART2_TX       7
 871 #define STM_DMA_CHANNEL_I2C2_TX         4
 872 #define STM_DMA_CHANNEL_I2C2_RX         5
 873 #define STM_DMA_CHANNEL_I2C1_TX         6
 874 #define STM_DMA_CHANNEL_I2C1_RX         7
 875 #define STM_DMA_CHANNEL_TIM1_CH1        2
 876 #define STM_DMA_CHANNEL_TIM1_CH4        4
 877 #define STM_DMA_CHANNEL_TIM1_TRIG       4
 878 #define STM_DMA_CHANNEL_TIM1_COM        4
 879 #define STM_DMA_CHANNEL_TIM1_UP         5
 880 #define STM_DMA_CHANNEL_TIM1_CH3        6
 881 #define STM_DMA_CHANNEL_TIM2_CH3        1
 882 #define STM_DMA_CHANNEL_TIM2_UP         2
 883 #define STM_DMA_CHANNEL_TIM2_CH1        5
 884 #define STM_DMA_CHANNEL_TIM2_CH2        7
 885 #define STM_DMA_CHANNEL_TIM2_CH4        7
 886 #define STM_DMA_CHANNEL_TIM3_CH3        2
 887 #define STM_DMA_CHANNEL_TIM3_CH4        3
 888 #define STM_DMA_CHANNEL_TIM3_UP         3
 889 #define STM_DMA_CHANNEL_TIM3_CH1        6
 890 #define STM_DMA_CHANNEL_TIM3_TRIG       6
 891 #define STM_DMA_CHANNEL_TIM4_CH1        1
 892 #define STM_DMA_CHANNEL_TIM4_CH2        4
 893 #define STM_DMA_CHANNEL_TIM4_CH3        5
 894 #define STM_DMA_CHANNEL_TIM4_UP         7
 895
 896 /* high density, xl-density and connectivity devices also have dma2 */
 897
 898 #define STM_DMA2_CHANNEL_ADC3           5
 899 #define STM_DMA2_CHANNEL_SPI3_RX        1
 900 #define STM_DMA2_CHANNEL_SPI3_TX        2
 901 #define STM_DMA2_CHANNEL_UART4_RX       3
 902 #define STM_DMA2_CHANNEL_UART4_TX       5
 903 #define STM_DMA2_CHANNEL_TIM5_CH4       1
 904 #define STM_DMA2_CHANNEL_TIM5_TRIG      1
 905 #define STM_DMA2_CHANNEL_TIM5_CH3       2
 906 #define STM_DMA2_CHANNEL_TIM5_UP        2
 907 #define STM_DMA2_CHANNEL_TIM5_CH2       4
 908 #define STM_DMA2_CHANNEL_TIM5_CH1       5
 909 #define STM_DMA2_CHANNEL_TIM6_UP        3
 910 #define STM_DMA2_CHANNEL_DAC_CHANNEL1   3
 911 #define STM_DMA2_CHANNEL_TIM7_UP        4
 912 #define STM_DMA2_CHANNEL_DAC_CHANNEL2   4
 913 #define STM_DMA2_CHANNEL_TIM8_CH3       1
 914 #define STM_DMA2_CHANNEL_TIM8_UP        1
 915 #define STM_DMA2_CHANNEL_TIM8_CH4       2
 916 #define STM_DMA2_CHANNEL_TIM8_TRIG      2
 917 #define STM_DMA2_CHANNEL_TIM8_COM       2
 918 #define STM_DMA2_CHANNEL_TIM8_CH1       3
 919 #define STM_DMA2_CHANNEL_TIM8_CH2       5
 920
 921 struct stm_spi {
 922         vuint32_t       cr1;
 923         vuint32_t       cr2;
 924         vuint32_t       sr;
 925         vuint32_t       dr;
 926
 927         vuint32_t       crcpr;
 928         vuint32_t       rxcrcr;
 929         vuint32_t       txcrcr;
 930         vuint32_t       i2scfgr;
 931
 932         vuint32_t       i2spr;
 933 };
 934
 935 extern struct stm_spi stm_spi1, stm_spi2;
 936
 937 #define stm_spi1 (*((struct stm_spi *) 0x40013000))
 938 #define stm_spi2 (*((struct stm_spi *) 0x40003800))
 939
 940 /* SPI channels go from 1 to 2, instead of 0 to 1 (sigh)
 941  */
 942
 943 #define STM_NUM_SPI     2
 944
 945 #define STM_SPI_INDEX(channel)          ((channel) - 1)
 946
 947 #define STM_SPI_CR1_BIDIMODE            15
 948 #define STM_SPI_CR1_BIDIOE              14
 949 #define STM_SPI_CR1_CRCEN               13
 950 #define STM_SPI_CR1_CRCNEXT             12
 951 #define STM_SPI_CR1_DFF                 11
 952 #define STM_SPI_CR1_RXONLY              10
 953 #define STM_SPI_CR1_SSM                 9
 954 #define STM_SPI_CR1_SSI                 8
 955 #define STM_SPI_CR1_LSBFIRST            7
 956 #define STM_SPI_CR1_SPE                 6
 957 #define STM_SPI_CR1_BR                  3
 958 #define  STM_SPI_CR1_BR_PCLK_2                  0
 959 #define  STM_SPI_CR1_BR_PCLK_4                  1
 960 #define  STM_SPI_CR1_BR_PCLK_8                  2
 961 #define  STM_SPI_CR1_BR_PCLK_16                 3
 962 #define  STM_SPI_CR1_BR_PCLK_32                 4
 963 #define  STM_SPI_CR1_BR_PCLK_64                 5
 964 #define  STM_SPI_CR1_BR_PCLK_128                6
 965 #define  STM_SPI_CR1_BR_PCLK_256                7
 966 #define  STM_SPI_CR1_BR_MASK                    7UL
 967
 968 #define STM_SPI_CR1_MSTR                2
 969 #define STM_SPI_CR1_CPOL                1
 970 #define STM_SPI_CR1_CPHA                0
 971
 972 #define STM_SPI_CR2_TXEIE       7
 973 #define STM_SPI_CR2_RXNEIE      6
 974 #define STM_SPI_CR2_ERRIE       5
 975 #define STM_SPI_CR2_SSOE        2
 976 #define STM_SPI_CR2_TXDMAEN     1
 977 #define STM_SPI_CR2_RXDMAEN     0
 978
 979 #define STM_SPI_SR_FRE          8
 980 #define STM_SPI_SR_BSY          7
 981 #define STM_SPI_SR_OVR          6
 982 #define STM_SPI_SR_MODF         5
 983 #define STM_SPI_SR_CRCERR       4
 984 #define STM_SPI_SR_UDR          3
 985 #define STM_SPI_SR_CHSIDE       2
 986 #define STM_SPI_SR_TXE          1
 987 #define STM_SPI_SR_RXNE         0
 988
 989 #define STM_NUM_I2C     2
 990
 991 #define STM_I2C_INDEX(channel)  ((channel) - 1)
 992
 993 struct stm_i2c {
 994         vuint32_t       cr1;
 995         vuint32_t       cr2;
 996         vuint32_t       oar1;
 997         vuint32_t       oar2;
 998         vuint32_t       dr;
 999         vuint32_t       sr1;
1000         vuint32_t       sr2;
1001         vuint32_t       ccr;
1002         vuint32_t       trise;
1003 };
1004
1005 extern struct stm_i2c stm_i2c1, stm_i2c2;
1006
1007 #define stm_i2c1        (*((struct stm_i2c *) 0x40005400))
1008 #define stm_i2c2        (*((struct stm_i2c *) 0x40005800))
1009
1010 #define STM_I2C_CR1_SWRST       15
1011 #define STM_I2C_CR1_ALERT       13
1012 #define STM_I2C_CR1_PEC         12
1013 #define STM_I2C_CR1_POS         11
1014 #define STM_I2C_CR1_ACK         10
1015 #define STM_I2C_CR1_STOP        9
1016 #define STM_I2C_CR1_START       8
1017 #define STM_I2C_CR1_NOSTRETCH   7
1018 #define STM_I2C_CR1_ENGC        6
1019 #define STM_I2C_CR1_ENPEC       5
1020 #define STM_I2C_CR1_ENARP       4
1021 #define STM_I2C_CR1_SMBTYPE     3
1022 #define STM_I2C_CR1_SMBUS       1
1023 #define STM_I2C_CR1_PE          0
1024
1025 #define STM_I2C_CR2_LAST        12
1026 #define STM_I2C_CR2_DMAEN       11
1027 #define STM_I2C_CR2_ITBUFEN     10
1028 #define STM_I2C_CR2_ITEVTEN     9
1029 #define STM_I2C_CR2_ITERREN     8
1030 #define STM_I2C_CR2_FREQ        0
1031 #define  STM_I2C_CR2_FREQ_MASK          0x3fUL
1032
1033 #define STM_I2C_SR1_SMBALERT    15
1034 #define STM_I2C_SR1_TIMEOUT     14
1035 #define STM_I2C_SR1_PECERR      12
1036 #define STM_I2C_SR1_OVR         11
1037 #define STM_I2C_SR1_AF          10
1038 #define STM_I2C_SR1_ARLO        9
1039 #define STM_I2C_SR1_BERR        8
1040 #define STM_I2C_SR1_TXE         7
1041 #define STM_I2C_SR1_RXNE        6
1042 #define STM_I2C_SR1_STOPF       4
1043 #define STM_I2C_SR1_ADD10       3
1044 #define STM_I2C_SR1_BTF         2
1045 #define STM_I2C_SR1_ADDR        1
1046 #define STM_I2C_SR1_SB          0
1047
1048 #define STM_I2C_SR2_PEC         8
1049 #define  STM_I2C_SR2_PEC_MASK   0xff00UL
1050 #define STM_I2C_SR2_DUALF       7
1051 #define STM_I2C_SR2_SMBHOST     6
1052 #define STM_I2C_SR2_SMBDEFAULT  5
1053 #define STM_I2C_SR2_GENCALL     4
1054 #define STM_I2C_SR2_TRA         2
1055 #define STM_I2C_SR2_BUSY        1
1056 #define STM_I2C_SR2_MSL         0
1057
1058 #define STM_I2C_CCR_FS          15
1059 #define STM_I2C_CCR_DUTY        14
1060 #define STM_I2C_CCR_CCR         0
1061 #define  STM_I2C_CCR_MASK       0x7ffUL
1062
1063 struct stm_adc {
1064         vuint32_t       sr;
1065         vuint32_t       cr1;
1066         vuint32_t       cr2;
1067         vuint32_t       smpr1;
1068
1069         vuint32_t       smpr2;
1070         vuint32_t       jofr1;
1071         vuint32_t       jofr2;
1072         vuint32_t       jofr3;
1073
1074         vuint32_t       jofr4;
1075         vuint32_t       htr;
1076         vuint32_t       ltr;
1077         vuint32_t       sqr1;
1078
1079         vuint32_t       sqr2;
1080         vuint32_t       sqr3;
1081         vuint32_t       jsqr;
1082         vuint32_t       jdr1;
1083
1084         vuint32_t       jdr2;
1085         vuint32_t       jdr3;
1086         vuint32_t       jdr4;
1087         vuint32_t       dr;
1088 };
1089
1090 extern struct stm_adc stm_adc;
1091
1092 #define stm_adc (*((struct stm_adc *) 0x40012400))
1093
1094 #define STM_ADC_SQ_TEMP         16
1095 #define STM_ADC_SQ_V_REF        17
1096
1097 #define STM_ADC_SR_STRT         4
1098 #define STM_ADC_SR_JSTRT        3
1099 #define STM_ADC_SR_JEOC         2
1100 #define STM_ADC_SR_EOC          1
1101 #define STM_ADC_SR_AWD          0
1102
1103 #define STM_ADC_CR1_AWDEN       23
1104 #define STM_ADC_CR1_JAWDEN      22
1105 #define STM_ADC_CR1_DUALMOD     16
1106 # define STM_ADC_CR1_DUALMOD_INDEPENDENT                0
1107 # define STM_ADC_CR1_DUALMOD_COMB_REG_SIM_INJ_SIM       1
1108 # define STM_ADC_CR1_DUALMOD_COMB_REG_SIM_ALT_TRIG      2
1109 # define STM_ADC_CR1_DUALMOD_COMB_INJ_SIM_FAST_INT      3
1110 # define STM_ADC_CR1_DUALMOD_COMB_INJ_SIM_SLOW_INT      4
1111 # define STM_ADC_CR1_DUALMOD_INJ_SIM                    5
1112 # define STM_ADC_CR1_DUALMOD_REG_SIM                    6
1113 # define STM_ADC_CR1_DUALMOD_FAST_INT                   7
1114 # define STM_ADC_CR1_DUALMOD_SLOW_INT                   8
1115 # define STM_ADC_CR1_DUALMOD_ALT_TRIG                   9
1116
1117 #define STM_ADC_CR1_DISCNUM     13
1118 #define  STM_ADC_CR1_DISCNUM_1          0
1119 #define  STM_ADC_CR1_DISCNUM_2          1
1120 #define  STM_ADC_CR1_DISCNUM_3          2
1121 #define  STM_ADC_CR1_DISCNUM_4          3
1122 #define  STM_ADC_CR1_DISCNUM_5          4
1123 #define  STM_ADC_CR1_DISCNUM_6          5
1124 #define  STM_ADC_CR1_DISCNUM_7          6
1125 #define  STM_ADC_CR1_DISCNUM_8          7
1126 #define  STM_ADC_CR1_DISCNUM_MASK       7UL
1127 #define STM_ADC_CR1_JDISCEN     12
1128 #define STM_ADC_CR1_DISCEN      11
1129 #define STM_ADC_CR1_JAUTO       10
1130 #define STM_ADC_CR1_AWDSGL      9
1131 #define STM_ADC_CR1_SCAN        8
1132 #define STM_ADC_CR1_JEOCIE      7
1133 #define STM_ADC_CR1_AWDIE       6
1134 #define STM_ADC_CR1_EOCIE       5
1135 #define STM_ADC_CR1_AWDCH       0
1136 #define  STM_ADC_CR1_AWDCH_MASK         0x1fUL
1137
1138 #define STM_ADC_CR2_TSVREF      23
1139 #define STM_ADC_CR2_SWSTART     21
1140 #define STM_ADC_CR2_JWSTART     21
1141 #define STM_ADC_CR2_EXTTRIG     20
1142 #define STM_ADC_CR2_EXTSEL      17
1143 #define  STM_ADC_CR2_EXTSEL_TIM1_CC1    0
1144 #define  STM_ADC_CR2_EXTSEL_TIM1_CC2    1
1145 #define  STM_ADC_CR2_EXTSEL_TIM1_CC3    2
1146 #define  STM_ADC_CR2_EXTSEL_TIM2_CC2    3
1147 #define  STM_ADC_CR2_EXTSEL_TIM3_TRGO   4
1148 #define  STM_ADC_CR2_EXTSEL_TIM4_CC4    5
1149 #define  STM_ADC_CR2_EXTSEL_EXTI        6
1150 #define  STM_ADC_CR2_EXTSEL_SWSTART     7
1151 #define  STM_ADC_CR2_EXTSEL_MASK        7UL
1152 #define STM_ADC_CR2_JEXTTRIG    15
1153 #define STM_ADC_CR2_JEXTSEL     12
1154 #define  STM_ADC_CR2_JEXTSEL_TIM1_TRGO  0
1155 #define  STM_ADC_CR2_JEXTSEL_TIM1_CC4   1
1156 #define  STM_ADC_CR2_JEXTSEL_TIM2_TRGO  2
1157 #define  STM_ADC_CR2_JEXTSEL_TIM2_CC1   3
1158 #define  STM_ADC_CR2_JEXTSEL_TIM3_CC4   4
1159 #define  STM_ADC_CR2_JEXTSEL_TIM4_TRGO  5
1160 #define  STM_ADC_CR2_JEXTSEL_EXTI_15    6
1161 #define  STM_ADC_CR2_JEXTSEL_JSWSTART   7
1162 #define  STM_ADC_CR2_JEXTSEL_MASK       7UL
1163 #define STM_ADC_CR2_ALIGN       11
1164 #define STM_ADC_CR2_DMA         8
1165 #define STM_ADC_CR2_RSTCAL      3
1166 #define STM_ADC_CR2_CAL         2
1167 #define STM_ADC_CR2_CONT        1
1168 #define STM_ADC_CR2_ADON        0
1169
1170 struct stm_exti {
1171         vuint32_t       imr;
1172         vuint32_t       emr;
1173         vuint32_t       rtsr;
1174         vuint32_t       ftsr;
1175
1176         vuint32_t       swier;
1177         vuint32_t       pr;
1178 };
1179
1180 extern struct stm_exti stm_exti;
1181
1182 #define stm_exti        (*((struct stm_exti *) 0x40010400))
1183
1184 static inline void
1185 stm_exticr_set(struct stm_gpio *gpio, int pin) {
1186         uint8_t reg = (uint8_t) (pin >> 2);
1187         uint8_t shift = (pin & 3) << 2;
1188         uint8_t val = 0;
1189
1190         /* Enable AFIO */
1191         stm_rcc.apb2enr |= (1 << STM_RCC_APB2ENR_AFIOEN);
1192
1193         if (gpio == &stm_gpioa)
1194                 val = STM_AFIO_EXTICR_PA;
1195         else if (gpio == &stm_gpiob)
1196                 val = STM_AFIO_EXTICR_PB;
1197         else if (gpio == &stm_gpioc)
1198                 val = STM_AFIO_EXTICR_PC;
1199         else if (gpio == &stm_gpiod)
1200                 val = STM_AFIO_EXTICR_PD;
1201         else if (gpio == &stm_gpioe)
1202                 val = STM_AFIO_EXTICR_PE;
1203
1204         stm_afio.exticr[reg] = (stm_afio.exticr[reg] & (uint32_t) ~(0xf << shift)) | val << shift;
1205 }
1206
1207 struct stm_tim18 {
1208         vuint32_t       cr1;
1209         vuint32_t       cr2;
1210         vuint32_t       smcr;
1211         vuint32_t       dier;
1212
1213         vuint32_t       sr;
1214         vuint32_t       egr;
1215         vuint32_t       ccmr1;
1216         vuint32_t       ccmr2;
1217
1218         vuint32_t       ccer;
1219         vuint32_t       cnt;
1220         vuint32_t       psc;
1221         vuint32_t       arr;
1222
1223         vuint32_t       rcr;
1224         vuint32_t       ccr1;
1225         vuint32_t       ccr2;
1226         vuint32_t       ccr3;
1227
1228         vuint32_t       ccr4;
1229         uint32_t        bdtr;
1230         vuint32_t       dcr;
1231         vuint32_t       dmar;
1232 };
1233
1234 extern struct stm_tim18 stm_tim1, stm_tim8;
1235
1236 #define stm_tim1        (*((struct stm_tim18 *) 0x40012c00))
1237 #define stm_tim8        (*((struct stm_tim18 *) 0x40013400))
1238
1239 #define STM_TIM18_CR1_CKD       8
1240 #define  STM_TIM18_CR1_CKD_1            0
1241 #define  STM_TIM18_CR1_CKD_2            1
1242 #define  STM_TIM18_CR1_CKD_4            2
1243 #define  STM_TIM18_CR1_CKD_MASK 3UL
1244 #define STM_TIM18_CR1_ARPE      7
1245 #define STM_TIM18_CR1_CMS       5
1246 #define  STM_TIM18_CR1_CMS_EDGE 0
1247 #define  STM_TIM18_CR1_CMS_CENTER_1     1
1248 #define  STM_TIM18_CR1_CMS_CENTER_2     2
1249 #define  STM_TIM18_CR1_CMS_CENTER_3     3
1250 #define  STM_TIM18_CR1_CMS_MASK 3UL
1251 #define STM_TIM18_CR1_DIR       4
1252 #define  STM_TIM18_CR1_DIR_UP           0
1253 #define  STM_TIM18_CR1_DIR_DOWN 1
1254 #define STM_TIM18_CR1_OPM       3
1255 #define STM_TIM18_CR1_URS       2
1256 #define STM_TIM18_CR1_UDIS      1
1257 #define STM_TIM18_CR1_CEN       0
1258
1259 #define STM_TIM18_CR2_TI1S      7
1260 #define STM_TIM18_CR2_MMS       4
1261 #define  STM_TIM18_CR2_MMS_RESET                0
1262 #define  STM_TIM18_CR2_MMS_ENABLE               1
1263 #define  STM_TIM18_CR2_MMS_UPDATE               2
1264 #define  STM_TIM18_CR2_MMS_COMPARE_PULSE        3
1265 #define  STM_TIM18_CR2_MMS_COMPARE_OC1REF       4
1266 #define  STM_TIM18_CR2_MMS_COMPARE_OC2REF       5
1267 #define  STM_TIM18_CR2_MMS_COMPARE_OC3REF       6
1268 #define  STM_TIM18_CR2_MMS_COMPARE_OC4REF       7
1269 #define  STM_TIM18_CR2_MMS_MASK         7UL
1270 #define STM_TIM18_CR2_CCDS      3
1271
1272 #define STM_TIM18_SMCR_ETP      15
1273 #define STM_TIM18_SMCR_ECE      14
1274 #define STM_TIM18_SMCR_ETPS     12
1275 #define  STM_TIM18_SMCR_ETPS_OFF                0
1276 #define  STM_TIM18_SMCR_ETPS_DIV_2              1
1277 #define  STM_TIM18_SMCR_ETPS_DIV_4              2
1278 #define  STM_TIM18_SMCR_ETPS_DIV_8              3
1279 #define  STM_TIM18_SMCR_ETPS_MASK               3UL
1280 #define STM_TIM18_SMCR_ETF      8
1281 #define  STM_TIM18_SMCR_ETF_NONE                0
1282 #define  STM_TIM18_SMCR_ETF_INT_N_2             1
1283 #define  STM_TIM18_SMCR_ETF_INT_N_4             2
1284 #define  STM_TIM18_SMCR_ETF_INT_N_8             3
1285 #define  STM_TIM18_SMCR_ETF_DTS_2_N_6           4
1286 #define  STM_TIM18_SMCR_ETF_DTS_2_N_8           5
1287 #define  STM_TIM18_SMCR_ETF_DTS_4_N_6           6
1288 #define  STM_TIM18_SMCR_ETF_DTS_4_N_8           7
1289 #define  STM_TIM18_SMCR_ETF_DTS_8_N_6           8
1290 #define  STM_TIM18_SMCR_ETF_DTS_8_N_8           9
1291 #define  STM_TIM18_SMCR_ETF_DTS_16_N_5          10
1292 #define  STM_TIM18_SMCR_ETF_DTS_16_N_6          11
1293 #define  STM_TIM18_SMCR_ETF_DTS_16_N_8          12
1294 #define  STM_TIM18_SMCR_ETF_DTS_32_N_5          13
1295 #define  STM_TIM18_SMCR_ETF_DTS_32_N_6          14
1296 #define  STM_TIM18_SMCR_ETF_DTS_32_N_8          15
1297 #define  STM_TIM18_SMCR_ETF_MASK                15UL
1298 #define STM_TIM18_SMCR_MSM      7
1299 #define STM_TIM18_SMCR_TS       4
1300 #define  STM_TIM18_SMCR_TS_ITR0         0
1301 #define  STM_TIM18_SMCR_TS_ITR1         1
1302 #define  STM_TIM18_SMCR_TS_ITR2         2
1303 #define  STM_TIM18_SMCR_TS_ITR3         3
1304 #define  STM_TIM18_SMCR_TS_TI1F_ED              4
1305 #define  STM_TIM18_SMCR_TS_TI1FP1               5
1306 #define  STM_TIM18_SMCR_TS_TI2FP2               6
1307 #define  STM_TIM18_SMCR_TS_ETRF         7
1308 #define  STM_TIM18_SMCR_TS_MASK         7UL
1309 #define STM_TIM18_SMCR_SMS      0
1310 #define  STM_TIM18_SMCR_SMS_DISABLE             0
1311 #define  STM_TIM18_SMCR_SMS_ENCODER_MODE_1      1
1312 #define  STM_TIM18_SMCR_SMS_ENCODER_MODE_2      2
1313 #define  STM_TIM18_SMCR_SMS_ENCODER_MODE_3      3
1314 #define  STM_TIM18_SMCR_SMS_RESET_MODE          4
1315 #define  STM_TIM18_SMCR_SMS_GATED_MODE          5
1316 #define  STM_TIM18_SMCR_SMS_TRIGGER_MODE        6
1317 #define  STM_TIM18_SMCR_SMS_EXTERNAL_CLOCK      7
1318 #define  STM_TIM18_SMCR_SMS_MASK                7UL
1319
1320 #define STM_TIM18_DIER_TDE              14
1321 #define STM_TIM18_DIER_CC4DE            12
1322 #define STM_TIM18_DIER_CC3DE            11
1323 #define STM_TIM18_DIER_CC2DE            10
1324 #define STM_TIM18_DIER_CC1DE            9
1325 #define STM_TIM18_DIER_UDE              8
1326
1327 #define STM_TIM18_DIER_TIE              6
1328 #define STM_TIM18_DIER_CC4IE            4
1329 #define STM_TIM18_DIER_CC3IE            3
1330 #define STM_TIM18_DIER_CC2IE            2
1331 #define STM_TIM18_DIER_CC1IE            1
1332 #define STM_TIM18_DIER_UIE              0
1333
1334 #define STM_TIM18_SR_CC4OF      12
1335 #define STM_TIM18_SR_CC3OF      11
1336 #define STM_TIM18_SR_CC2OF      10
1337 #define STM_TIM18_SR_CC1OF      9
1338 #define STM_TIM18_SR_TIF        6
1339 #define STM_TIM18_SR_CC4IF      4
1340 #define STM_TIM18_SR_CC3IF      3
1341 #define STM_TIM18_SR_CC2IF      2
1342 #define STM_TIM18_SR_CC1IF      1
1343 #define STM_TIM18_SR_UIF        0
1344
1345 #define STM_TIM18_EGR_TG        6
1346 #define STM_TIM18_EGR_CC4G      4
1347 #define STM_TIM18_EGR_CC3G      3
1348 #define STM_TIM18_EGR_CC2G      2
1349 #define STM_TIM18_EGR_CC1G      1
1350 #define STM_TIM18_EGR_UG        0
1351
1352 #define STM_TIM18_CCMR1_OC2CE   15
1353 #define STM_TIM18_CCMR1_OC2M    12
1354 #define  STM_TIM18_CCMR1_OC2M_FROZEN                    0
1355 #define  STM_TIM18_CCMR1_OC2M_SET_HIGH_ON_MATCH 1
1356 #define  STM_TIM18_CCMR1_OC2M_SET_LOW_ON_MATCH          2
1357 #define  STM_TIM18_CCMR1_OC2M_TOGGLE                    3
1358 #define  STM_TIM18_CCMR1_OC2M_FORCE_LOW         4
1359 #define  STM_TIM18_CCMR1_OC2M_FORCE_HIGH                5
1360 #define  STM_TIM18_CCMR1_OC2M_PWM_MODE_1                6
1361 #define  STM_TIM18_CCMR1_OC2M_PWM_MODE_2                7
1362 #define  STM_TIM18_CCMR1_OC2M_MASK                      7UL
1363 #define STM_TIM18_CCMR1_OC2PE   11
1364 #define STM_TIM18_CCMR1_OC2FE   10
1365 #define STM_TIM18_CCMR1_CC2S    8
1366 #define  STM_TIM18_CCMR1_CC2S_OUTPUT                    0
1367 #define  STM_TIM18_CCMR1_CC2S_INPUT_TI2         1
1368 #define  STM_TIM18_CCMR1_CC2S_INPUT_TI1         2
1369 #define  STM_TIM18_CCMR1_CC2S_INPUT_TRC         3
1370 #define  STM_TIM18_CCMR1_CC2S_MASK                      3UL
1371
1372 #define STM_TIM18_CCMR1_OC1CE   7
1373 #define STM_TIM18_CCMR1_OC1M    4
1374 #define  STM_TIM18_CCMR1_OC1M_FROZEN                    0
1375 #define  STM_TIM18_CCMR1_OC1M_SET_HIGH_ON_MATCH 1
1376 #define  STM_TIM18_CCMR1_OC1M_SET_LOW_ON_MATCH          2
1377 #define  STM_TIM18_CCMR1_OC1M_TOGGLE                    3
1378 #define  STM_TIM18_CCMR1_OC1M_FORCE_LOW         4
1379 #define  STM_TIM18_CCMR1_OC1M_FORCE_HIGH                5
1380 #define  STM_TIM18_CCMR1_OC1M_PWM_MODE_1                6
1381 #define  STM_TIM18_CCMR1_OC1M_PWM_MODE_2                7
1382 #define  STM_TIM18_CCMR1_OC1M_MASK                      7UL
1383 #define STM_TIM18_CCMR1_OC1PE   3
1384 #define STM_TIM18_CCMR1_OC1FE   2
1385 #define STM_TIM18_CCMR1_CC1S    0
1386 #define  STM_TIM18_CCMR1_CC1S_OUTPUT                    0
1387 #define  STM_TIM18_CCMR1_CC1S_INPUT_TI1         1
1388 #define  STM_TIM18_CCMR1_CC1S_INPUT_TI2         2
1389 #define  STM_TIM18_CCMR1_CC1S_INPUT_TRC         3
1390 #define  STM_TIM18_CCMR1_CC1S_MASK                      3UL
1391
1392 #define STM_TIM18_CCMR1_IC2F    12
1393 #define  STM_TIM18_CCMR1_IC2F_NONE                      0
1394 #define  STM_TIM18_CCMR1_IC2F_CK_INT_N_2                1
1395 #define  STM_TIM18_CCMR1_IC2F_CK_INT_N_4                2
1396 #define  STM_TIM18_CCMR1_IC2F_CK_INT_N_8                3
1397 #define  STM_TIM18_CCMR1_IC2F_DTS_2_N_6         4
1398 #define  STM_TIM18_CCMR1_IC2F_DTS_2_N_8         5
1399 #define  STM_TIM18_CCMR1_IC2F_DTS_4_N_6         6
1400 #define  STM_TIM18_CCMR1_IC2F_DTS_4_N_8         7
1401 #define  STM_TIM18_CCMR1_IC2F_DTS_8_N_6         8
1402 #define  STM_TIM18_CCMR1_IC2F_DTS_8_N_8         9
1403 #define  STM_TIM18_CCMR1_IC2F_DTS_16_N_5                10
1404 #define  STM_TIM18_CCMR1_IC2F_DTS_16_N_6                11
1405 #define  STM_TIM18_CCMR1_IC2F_DTS_16_N_8                12
1406 #define  STM_TIM18_CCMR1_IC2F_DTS_32_N_5                13
1407 #define  STM_TIM18_CCMR1_IC2F_DTS_32_N_6                14
1408 #define  STM_TIM18_CCMR1_IC2F_DTS_32_N_8                15
1409 #define STM_TIM18_CCMR1_IC2PSC  10
1410 #define  STM_TIM18_CCMR1_IC2PSC_NONE                    0
1411 #define  STM_TIM18_CCMR1_IC2PSC_2                       1
1412 #define  STM_TIM18_CCMR1_IC2PSC_4                       2
1413 #define  STM_TIM18_CCMR1_IC2PSC_8                       3
1414 #define STM_TIM18_CCMR1_IC1F    4
1415 #define  STM_TIM18_CCMR1_IC1F_NONE                      0
1416 #define  STM_TIM18_CCMR1_IC1F_CK_INT_N_2                1
1417 #define  STM_TIM18_CCMR1_IC1F_CK_INT_N_4                2
1418 #define  STM_TIM18_CCMR1_IC1F_CK_INT_N_8                3
1419 #define  STM_TIM18_CCMR1_IC1F_DTS_2_N_6         4
1420 #define  STM_TIM18_CCMR1_IC1F_DTS_2_N_8         5
1421 #define  STM_TIM18_CCMR1_IC1F_DTS_4_N_6         6
1422 #define  STM_TIM18_CCMR1_IC1F_DTS_4_N_8         7
1423 #define  STM_TIM18_CCMR1_IC1F_DTS_8_N_6         8
1424 #define  STM_TIM18_CCMR1_IC1F_DTS_8_N_8         9
1425 #define  STM_TIM18_CCMR1_IC1F_DTS_16_N_5                10
1426 #define  STM_TIM18_CCMR1_IC1F_DTS_16_N_6                11
1427 #define  STM_TIM18_CCMR1_IC1F_DTS_16_N_8                12
1428 #define  STM_TIM18_CCMR1_IC1F_DTS_32_N_5                13
1429 #define  STM_TIM18_CCMR1_IC1F_DTS_32_N_6                14
1430 #define  STM_TIM18_CCMR1_IC1F_DTS_32_N_8                15
1431 #define STM_TIM18_CCMR1_IC1PSC  2
1432 #define  STM_TIM18_CCMR1_IC1PSC_NONE                    0
1433 #define  STM_TIM18_CCMR1_IC1PSC_2                       1
1434 #define  STM_TIM18_CCMR1_IC1PSC_4                       2
1435 #define  STM_TIM18_CCMR1_IC1PSC_8                       3
1436
1437 #define STM_TIM18_CCMR2_OC4CE   15
1438 #define STM_TIM18_CCMR2_OC4M    12
1439 #define  STM_TIM18_CCMR2_OC4M_FROZEN                    0
1440 #define  STM_TIM18_CCMR2_OC4M_SET_HIGH_ON_MATCH 1
1441 #define  STM_TIM18_CCMR2_OC4M_SET_LOW_ON_MATCH          2
1442 #define  STM_TIM18_CCMR2_OC4M_TOGGLE                    3
1443 #define  STM_TIM18_CCMR2_OC4M_FORCE_LOW         4
1444 #define  STM_TIM18_CCMR2_OC4M_FORCE_HIGH                5
1445 #define  STM_TIM18_CCMR2_OC4M_PWM_MODE_1                6
1446 #define  STM_TIM18_CCMR2_OC4M_PWM_MODE_2                7
1447 #define  STM_TIM18_CCMR2_OC4M_MASK                      7UL
1448 #define STM_TIM18_CCMR2_OC4PE   11
1449 #define STM_TIM18_CCMR2_OC4FE   10
1450 #define STM_TIM18_CCMR2_CC4S    8
1451 #define  STM_TIM18_CCMR2_CC4S_OUTPUT                    0
1452 #define  STM_TIM18_CCMR2_CC4S_INPUT_TI4         1
1453 #define  STM_TIM18_CCMR2_CC4S_INPUT_TI3         2
1454 #define  STM_TIM18_CCMR2_CC4S_INPUT_TRC         3
1455 #define  STM_TIM18_CCMR2_CC4S_MASK                      3UL
1456
1457 #define STM_TIM18_CCMR2_OC3CE   7
1458 #define STM_TIM18_CCMR2_OC3M    4
1459 #define  STM_TIM18_CCMR2_OC3M_FROZEN                    0
1460 #define  STM_TIM18_CCMR2_OC3M_SET_HIGH_ON_MATCH 1
1461 #define  STM_TIM18_CCMR2_OC3M_SET_LOW_ON_MATCH          2
1462 #define  STM_TIM18_CCMR2_OC3M_TOGGLE                    3
1463 #define  STM_TIM18_CCMR2_OC3M_FORCE_LOW         4
1464 #define  STM_TIM18_CCMR2_OC3M_FORCE_HIGH                5
1465 #define  STM_TIM18_CCMR2_OC3M_PWM_MODE_1                6
1466 #define  STM_TIM18_CCMR2_OC3M_PWM_MODE_2                7
1467 #define  STM_TIM18_CCMR2_OC3M_MASK                      7UL
1468 #define STM_TIM18_CCMR2_OC3PE   3
1469 #define STM_TIM18_CCMR2_OC3FE   2
1470 #define STM_TIM18_CCMR2_CC3S    0
1471 #define  STM_TIM18_CCMR2_CC3S_OUTPUT                    0
1472 #define  STM_TIM18_CCMR2_CC3S_INPUT_TI3         1
1473 #define  STM_TIM18_CCMR2_CC3S_INPUT_TI4         2
1474 #define  STM_TIM18_CCMR2_CC3S_INPUT_TRC         3
1475 #define  STM_TIM18_CCMR2_CC3S_MASK                      3UL
1476
1477 #define STM_TIM18_CCER_CC4NP    15
1478 #define STM_TIM18_CCER_CC4P     13
1479 #define  STM_TIM18_CCER_CC4P_ACTIVE_HIGH        0
1480 #define  STM_TIM18_CCER_CC4P_ACTIVE_LOW 1
1481 #define STM_TIM18_CCER_CC4E     12
1482 #define STM_TIM18_CCER_CC3NP    11
1483 #define STM_TIM18_CCER_CC3P     9
1484 #define  STM_TIM18_CCER_CC3P_ACTIVE_HIGH        0
1485 #define  STM_TIM18_CCER_CC3P_ACTIVE_LOW 1
1486 #define STM_TIM18_CCER_CC3E     8
1487 #define STM_TIM18_CCER_CC2NP    7
1488 #define STM_TIM18_CCER_CC2P     5
1489 #define  STM_TIM18_CCER_CC2P_ACTIVE_HIGH        0
1490 #define  STM_TIM18_CCER_CC2P_ACTIVE_LOW 1
1491 #define STM_TIM18_CCER_CC2E     4
1492 #define STM_TIM18_CCER_CC1NP    3
1493 #define STM_TIM18_CCER_CC1P     1
1494 #define  STM_TIM18_CCER_CC1P_ACTIVE_HIGH        0
1495 #define  STM_TIM18_CCER_CC1P_ACTIVE_LOW 1
1496 #define STM_TIM18_CCER_CC1E     0
1497
1498 struct stm_tim234 {
1499         vuint32_t       cr1;
1500         vuint32_t       cr2;
1501         vuint32_t       smcr;
1502         vuint32_t       dier;
1503
1504         vuint32_t       sr;
1505         vuint32_t       egr;
1506         vuint32_t       ccmr1;
1507         vuint32_t       ccmr2;
1508
1509         vuint32_t       ccer;
1510         vuint32_t       cnt;
1511         vuint32_t       psc;
1512         vuint32_t       arr;
1513
1514         uint32_t        reserved_30;
1515         vuint32_t       ccr1;
1516         vuint32_t       ccr2;
1517         vuint32_t       ccr3;
1518
1519         vuint32_t       ccr4;
1520         uint32_t        reserved_44;
1521         vuint32_t       dcr;
1522         vuint32_t       dmar;
1523 };
1524
1525 extern struct stm_tim234 stm_tim2, stm_tim3, stm_tim4;
1526
1527 #define stm_tim2        (*((struct stm_tim234 *) 0x40000000))
1528 #define stm_tim3        (*((struct stm_tim234 *) 0x40000400))
1529 #define stm_tim4        (*((struct stm_tim234 *) 0x40000800))
1530
1531 #define STM_TIM234_CR1_CKD      8
1532 #define  STM_TIM234_CR1_CKD_1           0
1533 #define  STM_TIM234_CR1_CKD_2           1
1534 #define  STM_TIM234_CR1_CKD_4           2
1535 #define  STM_TIM234_CR1_CKD_MASK        3UL
1536 #define STM_TIM234_CR1_ARPE     7
1537 #define STM_TIM234_CR1_CMS      5
1538 #define  STM_TIM234_CR1_CMS_EDGE        0
1539 #define  STM_TIM234_CR1_CMS_CENTER_1    1
1540 #define  STM_TIM234_CR1_CMS_CENTER_2    2
1541 #define  STM_TIM234_CR1_CMS_CENTER_3    3
1542 #define  STM_TIM234_CR1_CMS_MASK        3UL
1543 #define STM_TIM234_CR1_DIR      4
1544 #define  STM_TIM234_CR1_DIR_UP          0
1545 #define  STM_TIM234_CR1_DIR_DOWN        1
1546 #define STM_TIM234_CR1_OPM      3
1547 #define STM_TIM234_CR1_URS      2
1548 #define STM_TIM234_CR1_UDIS     1
1549 #define STM_TIM234_CR1_CEN      0
1550
1551 #define STM_TIM234_CR2_TI1S     7
1552 #define STM_TIM234_CR2_MMS      4
1553 #define  STM_TIM234_CR2_MMS_RESET               0
1554 #define  STM_TIM234_CR2_MMS_ENABLE              1
1555 #define  STM_TIM234_CR2_MMS_UPDATE              2
1556 #define  STM_TIM234_CR2_MMS_COMPARE_PULSE       3
1557 #define  STM_TIM234_CR2_MMS_COMPARE_OC1REF      4
1558 #define  STM_TIM234_CR2_MMS_COMPARE_OC2REF      5
1559 #define  STM_TIM234_CR2_MMS_COMPARE_OC3REF      6
1560 #define  STM_TIM234_CR2_MMS_COMPARE_OC4REF      7
1561 #define  STM_TIM234_CR2_MMS_MASK                7UL
1562 #define STM_TIM234_CR2_CCDS     3
1563
1564 #define STM_TIM234_SMCR_ETP     15
1565 #define STM_TIM234_SMCR_ECE     14
1566 #define STM_TIM234_SMCR_ETPS    12
1567 #define  STM_TIM234_SMCR_ETPS_OFF               0
1568 #define  STM_TIM234_SMCR_ETPS_DIV_2             1
1569 #define  STM_TIM234_SMCR_ETPS_DIV_4             2
1570 #define  STM_TIM234_SMCR_ETPS_DIV_8             3
1571 #define  STM_TIM234_SMCR_ETPS_MASK              3UL
1572 #define STM_TIM234_SMCR_ETF     8
1573 #define  STM_TIM234_SMCR_ETF_NONE               0
1574 #define  STM_TIM234_SMCR_ETF_INT_N_2            1
1575 #define  STM_TIM234_SMCR_ETF_INT_N_4            2
1576 #define  STM_TIM234_SMCR_ETF_INT_N_8            3
1577 #define  STM_TIM234_SMCR_ETF_DTS_2_N_6          4
1578 #define  STM_TIM234_SMCR_ETF_DTS_2_N_8          5
1579 #define  STM_TIM234_SMCR_ETF_DTS_4_N_6          6
1580 #define  STM_TIM234_SMCR_ETF_DTS_4_N_8          7
1581 #define  STM_TIM234_SMCR_ETF_DTS_8_N_6          8
1582 #define  STM_TIM234_SMCR_ETF_DTS_8_N_8          9
1583 #define  STM_TIM234_SMCR_ETF_DTS_16_N_5         10
1584 #define  STM_TIM234_SMCR_ETF_DTS_16_N_6         11
1585 #define  STM_TIM234_SMCR_ETF_DTS_16_N_8         12
1586 #define  STM_TIM234_SMCR_ETF_DTS_32_N_5         13
1587 #define  STM_TIM234_SMCR_ETF_DTS_32_N_6         14
1588 #define  STM_TIM234_SMCR_ETF_DTS_32_N_8         15
1589 #define  STM_TIM234_SMCR_ETF_MASK               15UL
1590 #define STM_TIM234_SMCR_MSM     7
1591 #define STM_TIM234_SMCR_TS      4
1592 #define  STM_TIM234_SMCR_TS_ITR0                0
1593 #define  STM_TIM234_SMCR_TS_ITR1                1
1594 #define  STM_TIM234_SMCR_TS_ITR2                2
1595 #define  STM_TIM234_SMCR_TS_ITR3                3
1596 #define  STM_TIM234_SMCR_TS_TI1F_ED             4
1597 #define  STM_TIM234_SMCR_TS_TI1FP1              5
1598 #define  STM_TIM234_SMCR_TS_TI2FP2              6
1599 #define  STM_TIM234_SMCR_TS_ETRF                7
1600 #define  STM_TIM234_SMCR_TS_MASK                7UL
1601 #define STM_TIM234_SMCR_SMS     0
1602 #define  STM_TIM234_SMCR_SMS_DISABLE            0
1603 #define  STM_TIM234_SMCR_SMS_ENCODER_MODE_1     1
1604 #define  STM_TIM234_SMCR_SMS_ENCODER_MODE_2     2
1605 #define  STM_TIM234_SMCR_SMS_ENCODER_MODE_3     3
1606 #define  STM_TIM234_SMCR_SMS_RESET_MODE         4
1607 #define  STM_TIM234_SMCR_SMS_GATED_MODE         5
1608 #define  STM_TIM234_SMCR_SMS_TRIGGER_MODE       6
1609 #define  STM_TIM234_SMCR_SMS_EXTERNAL_CLOCK     7
1610 #define  STM_TIM234_SMCR_SMS_MASK               7UL
1611
1612 #define STM_TIM234_DIER_TDE             14
1613 #define STM_TIM234_DIER_CC4DE           12
1614 #define STM_TIM234_DIER_CC3DE           11
1615 #define STM_TIM234_DIER_CC2DE           10
1616 #define STM_TIM234_DIER_CC1DE           9
1617 #define STM_TIM234_DIER_UDE             8
1618
1619 #define STM_TIM234_DIER_TIE             6
1620 #define STM_TIM234_DIER_CC4IE           4
1621 #define STM_TIM234_DIER_CC3IE           3
1622 #define STM_TIM234_DIER_CC2IE           2
1623 #define STM_TIM234_DIER_CC1IE           1
1624 #define STM_TIM234_DIER_UIE             0
1625
1626 #define STM_TIM234_SR_CC4OF     12
1627 #define STM_TIM234_SR_CC3OF     11
1628 #define STM_TIM234_SR_CC2OF     10
1629 #define STM_TIM234_SR_CC1OF     9
1630 #define STM_TIM234_SR_TIF       6
1631 #define STM_TIM234_SR_CC4IF     4
1632 #define STM_TIM234_SR_CC3IF     3
1633 #define STM_TIM234_SR_CC2IF     2
1634 #define STM_TIM234_SR_CC1IF     1
1635 #define STM_TIM234_SR_UIF       0
1636
1637 #define STM_TIM234_EGR_TG       6
1638 #define STM_TIM234_EGR_CC4G     4
1639 #define STM_TIM234_EGR_CC3G     3
1640 #define STM_TIM234_EGR_CC2G     2
1641 #define STM_TIM234_EGR_CC1G     1
1642 #define STM_TIM234_EGR_UG       0
1643
1644 #define STM_TIM234_CCMR1_OC2CE  15
1645 #define STM_TIM234_CCMR1_OC2M   12
1646 #define  STM_TIM234_CCMR1_OC2M_FROZEN                   0
1647 #define  STM_TIM234_CCMR1_OC2M_SET_HIGH_ON_MATCH        1
1648 #define  STM_TIM234_CCMR1_OC2M_SET_LOW_ON_MATCH         2
1649 #define  STM_TIM234_CCMR1_OC2M_TOGGLE                   3
1650 #define  STM_TIM234_CCMR1_OC2M_FORCE_LOW                4
1651 #define  STM_TIM234_CCMR1_OC2M_FORCE_HIGH               5
1652 #define  STM_TIM234_CCMR1_OC2M_PWM_MODE_1               6
1653 #define  STM_TIM234_CCMR1_OC2M_PWM_MODE_2               7
1654 #define  STM_TIM234_CCMR1_OC2M_MASK                     7UL
1655 #define STM_TIM234_CCMR1_OC2PE  11
1656 #define STM_TIM234_CCMR1_OC2FE  10
1657 #define STM_TIM234_CCMR1_CC2S   8
1658 #define  STM_TIM234_CCMR1_CC2S_OUTPUT                   0
1659 #define  STM_TIM234_CCMR1_CC2S_INPUT_TI2                1
1660 #define  STM_TIM234_CCMR1_CC2S_INPUT_TI1                2
1661 #define  STM_TIM234_CCMR1_CC2S_INPUT_TRC                3
1662 #define  STM_TIM234_CCMR1_CC2S_MASK                     3UL
1663
1664 #define STM_TIM234_CCMR1_OC1CE  7
1665 #define STM_TIM234_CCMR1_OC1M   4
1666 #define  STM_TIM234_CCMR1_OC1M_FROZEN                   0
1667 #define  STM_TIM234_CCMR1_OC1M_SET_HIGH_ON_MATCH        1
1668 #define  STM_TIM234_CCMR1_OC1M_SET_LOW_ON_MATCH         2
1669 #define  STM_TIM234_CCMR1_OC1M_TOGGLE                   3
1670 #define  STM_TIM234_CCMR1_OC1M_FORCE_LOW                4
1671 #define  STM_TIM234_CCMR1_OC1M_FORCE_HIGH               5
1672 #define  STM_TIM234_CCMR1_OC1M_PWM_MODE_1               6
1673 #define  STM_TIM234_CCMR1_OC1M_PWM_MODE_2               7
1674 #define  STM_TIM234_CCMR1_OC1M_MASK                     7UL
1675 #define STM_TIM234_CCMR1_OC1PE  3
1676 #define STM_TIM234_CCMR1_OC1FE  2
1677 #define STM_TIM234_CCMR1_CC1S   0
1678 #define  STM_TIM234_CCMR1_CC1S_OUTPUT                   0
1679 #define  STM_TIM234_CCMR1_CC1S_INPUT_TI1                1
1680 #define  STM_TIM234_CCMR1_CC1S_INPUT_TI2                2
1681 #define  STM_TIM234_CCMR1_CC1S_INPUT_TRC                3
1682 #define  STM_TIM234_CCMR1_CC1S_MASK                     3UL
1683
1684 #define STM_TIM234_CCMR1_IC2F   12
1685 #define  STM_TIM234_CCMR1_IC2F_NONE                     0
1686 #define  STM_TIM234_CCMR1_IC2F_CK_INT_N_2               1
1687 #define  STM_TIM234_CCMR1_IC2F_CK_INT_N_4               2
1688 #define  STM_TIM234_CCMR1_IC2F_CK_INT_N_8               3
1689 #define  STM_TIM234_CCMR1_IC2F_DTS_2_N_6                4
1690 #define  STM_TIM234_CCMR1_IC2F_DTS_2_N_8                5
1691 #define  STM_TIM234_CCMR1_IC2F_DTS_4_N_6                6
1692 #define  STM_TIM234_CCMR1_IC2F_DTS_4_N_8                7
1693 #define  STM_TIM234_CCMR1_IC2F_DTS_8_N_6                8
1694 #define  STM_TIM234_CCMR1_IC2F_DTS_8_N_8                9
1695 #define  STM_TIM234_CCMR1_IC2F_DTS_16_N_5               10
1696 #define  STM_TIM234_CCMR1_IC2F_DTS_16_N_6               11
1697 #define  STM_TIM234_CCMR1_IC2F_DTS_16_N_8               12
1698 #define  STM_TIM234_CCMR1_IC2F_DTS_32_N_5               13
1699 #define  STM_TIM234_CCMR1_IC2F_DTS_32_N_6               14
1700 #define  STM_TIM234_CCMR1_IC2F_DTS_32_N_8               15
1701 #define STM_TIM234_CCMR1_IC2PSC 10
1702 #define  STM_TIM234_CCMR1_IC2PSC_NONE                   0
1703 #define  STM_TIM234_CCMR1_IC2PSC_2                      1
1704 #define  STM_TIM234_CCMR1_IC2PSC_4                      2
1705 #define  STM_TIM234_CCMR1_IC2PSC_8                      3
1706 #define STM_TIM234_CCMR1_IC1F   4
1707 #define  STM_TIM234_CCMR1_IC1F_NONE                     0
1708 #define  STM_TIM234_CCMR1_IC1F_CK_INT_N_2               1
1709 #define  STM_TIM234_CCMR1_IC1F_CK_INT_N_4               2
1710 #define  STM_TIM234_CCMR1_IC1F_CK_INT_N_8               3
1711 #define  STM_TIM234_CCMR1_IC1F_DTS_2_N_6                4
1712 #define  STM_TIM234_CCMR1_IC1F_DTS_2_N_8                5
1713 #define  STM_TIM234_CCMR1_IC1F_DTS_4_N_6                6
1714 #define  STM_TIM234_CCMR1_IC1F_DTS_4_N_8                7
1715 #define  STM_TIM234_CCMR1_IC1F_DTS_8_N_6                8
1716 #define  STM_TIM234_CCMR1_IC1F_DTS_8_N_8                9
1717 #define  STM_TIM234_CCMR1_IC1F_DTS_16_N_5               10
1718 #define  STM_TIM234_CCMR1_IC1F_DTS_16_N_6               11
1719 #define  STM_TIM234_CCMR1_IC1F_DTS_16_N_8               12
1720 #define  STM_TIM234_CCMR1_IC1F_DTS_32_N_5               13
1721 #define  STM_TIM234_CCMR1_IC1F_DTS_32_N_6               14
1722 #define  STM_TIM234_CCMR1_IC1F_DTS_32_N_8               15
1723 #define STM_TIM234_CCMR1_IC1PSC 2
1724 #define  STM_TIM234_CCMR1_IC1PSC_NONE                   0
1725 #define  STM_TIM234_CCMR1_IC1PSC_2                      1
1726 #define  STM_TIM234_CCMR1_IC1PSC_4                      2
1727 #define  STM_TIM234_CCMR1_IC1PSC_8                      3
1728
1729 #define STM_TIM234_CCMR2_OC4CE  15
1730 #define STM_TIM234_CCMR2_OC4M   12
1731 #define  STM_TIM234_CCMR2_OC4M_FROZEN                   0
1732 #define  STM_TIM234_CCMR2_OC4M_SET_HIGH_ON_MATCH        1
1733 #define  STM_TIM234_CCMR2_OC4M_SET_LOW_ON_MATCH         2
1734 #define  STM_TIM234_CCMR2_OC4M_TOGGLE                   3
1735 #define  STM_TIM234_CCMR2_OC4M_FORCE_LOW                4
1736 #define  STM_TIM234_CCMR2_OC4M_FORCE_HIGH               5
1737 #define  STM_TIM234_CCMR2_OC4M_PWM_MODE_1               6
1738 #define  STM_TIM234_CCMR2_OC4M_PWM_MODE_2               7
1739 #define  STM_TIM234_CCMR2_OC4M_MASK                     7UL
1740 #define STM_TIM234_CCMR2_OC4PE  11
1741 #define STM_TIM234_CCMR2_OC4FE  10
1742 #define STM_TIM234_CCMR2_CC4S   8
1743 #define  STM_TIM234_CCMR2_CC4S_OUTPUT                   0
1744 #define  STM_TIM234_CCMR2_CC4S_INPUT_TI4                1
1745 #define  STM_TIM234_CCMR2_CC4S_INPUT_TI3                2
1746 #define  STM_TIM234_CCMR2_CC4S_INPUT_TRC                3
1747 #define  STM_TIM234_CCMR2_CC4S_MASK                     3UL
1748
1749 #define STM_TIM234_CCMR2_OC3CE  7
1750 #define STM_TIM234_CCMR2_OC3M   4
1751 #define  STM_TIM234_CCMR2_OC3M_FROZEN                   0
1752 #define  STM_TIM234_CCMR2_OC3M_SET_HIGH_ON_MATCH        1
1753 #define  STM_TIM234_CCMR2_OC3M_SET_LOW_ON_MATCH         2
1754 #define  STM_TIM234_CCMR2_OC3M_TOGGLE                   3
1755 #define  STM_TIM234_CCMR2_OC3M_FORCE_LOW                4
1756 #define  STM_TIM234_CCMR2_OC3M_FORCE_HIGH               5
1757 #define  STM_TIM234_CCMR2_OC3M_PWM_MODE_1               6
1758 #define  STM_TIM234_CCMR2_OC3M_PWM_MODE_2               7
1759 #define  STM_TIM234_CCMR2_OC3M_MASK                     7UL
1760 #define STM_TIM234_CCMR2_OC3PE  3
1761 #define STM_TIM234_CCMR2_OC3FE  2
1762 #define STM_TIM234_CCMR2_CC3S   0
1763 #define  STM_TIM234_CCMR2_CC3S_OUTPUT                   0
1764 #define  STM_TIM234_CCMR2_CC3S_INPUT_TI3                1
1765 #define  STM_TIM234_CCMR2_CC3S_INPUT_TI4                2
1766 #define  STM_TIM234_CCMR2_CC3S_INPUT_TRC                3
1767 #define  STM_TIM234_CCMR2_CC3S_MASK                     3UL
1768
1769 #define STM_TIM234_CCER_CC4NP   15
1770 #define STM_TIM234_CCER_CC4P    13
1771 #define  STM_TIM234_CCER_CC4P_ACTIVE_HIGH       0
1772 #define  STM_TIM234_CCER_CC4P_ACTIVE_LOW        1
1773 #define STM_TIM234_CCER_CC4E    12
1774 #define STM_TIM234_CCER_CC3NP   11
1775 #define STM_TIM234_CCER_CC3P    9
1776 #define  STM_TIM234_CCER_CC3P_ACTIVE_HIGH       0
1777 #define  STM_TIM234_CCER_CC3P_ACTIVE_LOW        1
1778 #define STM_TIM234_CCER_CC3E    8
1779 #define STM_TIM234_CCER_CC2NP   7
1780 #define STM_TIM234_CCER_CC2P    5
1781 #define  STM_TIM234_CCER_CC2P_ACTIVE_HIGH       0
1782 #define  STM_TIM234_CCER_CC2P_ACTIVE_LOW        1
1783 #define STM_TIM234_CCER_CC2E    4
1784 #define STM_TIM234_CCER_CC1NP   3
1785 #define STM_TIM234_CCER_CC1P    1
1786 #define  STM_TIM234_CCER_CC1P_ACTIVE_HIGH       0
1787 #define  STM_TIM234_CCER_CC1P_ACTIVE_LOW        1
1788 #define STM_TIM234_CCER_CC1E    0
1789
1790 struct stm_tim67 {
1791         vuint32_t       cr1;
1792         vuint32_t       cr2;
1793         uint32_t        _unused_08;
1794         vuint32_t       dier;
1795
1796         vuint32_t       sr;
1797         vuint32_t       egr;
1798         uint32_t        _unused_18;
1799         uint32_t        _unused_1c;
1800
1801         uint32_t        _unused_20;
1802         vuint32_t       cnt;
1803         vuint32_t       psc;
1804         vuint32_t       arr;
1805 };
1806
1807 extern struct stm_tim67 stm_tim6;
1808
1809 #define STM_TIM67_CR1_ARPE      (7)
1810 #define STM_TIM67_CR1_OPM       (3)
1811 #define STM_TIM67_CR1_URS       (2)
1812 #define STM_TIM67_CR1_UDIS      (1)
1813 #define STM_TIM67_CR1_CEN       (0)
1814
1815 #define STM_TIM67_CR2_MMS       (4)
1816 #define  STM_TIM67_CR2_MMS_RESET        0
1817 #define  STM_TIM67_CR2_MMS_ENABLE       1
1818 #define  STM_TIM67_CR2_MMS_UPDATE       2
1819 #define  STM_TIM67_CR2_MMS_MASK         7UL
1820
1821 #define STM_TIM67_DIER_UDE      (8)
1822 #define STM_TIM67_DIER_UIE      (0)
1823
1824 #define STM_TIM67_SR_UIF        (0)
1825
1826 #define STM_TIM67_EGR_UG        (0)
1827
1828 #define isr_decl(name) void stm_ ## name ## _isr(void)
1829
1830 isr_decl(halt);
1831 isr_decl(ignore);
1832
1833 isr_decl(nmi);
1834 isr_decl(hardfault);
1835 isr_decl(memmanage);
1836 isr_decl(busfault);
1837 isr_decl(usagefault);
1838 isr_decl(svc);
1839 isr_decl(debugmon);
1840 isr_decl(pendsv);
1841 isr_decl(systick);
1842 isr_decl(wwdg);
1843 isr_decl(pvd);
1844 isr_decl(tamper_stamp);
1845 isr_decl(rtc_wkup);
1846 isr_decl(flash);
1847 isr_decl(rcc);
1848 isr_decl(exti0);
1849 isr_decl(exti1);
1850 isr_decl(exti2);
1851 isr_decl(exti3);
1852 isr_decl(exti4);
1853 isr_decl(dma1_channel1);
1854 isr_decl(dma1_channel2);
1855 isr_decl(dma1_channel3);
1856 isr_decl(dma1_channel4);
1857 isr_decl(dma1_channel5);
1858 isr_decl(dma1_channel6);
1859 isr_decl(dma1_channel7);
1860 isr_decl(adc1_2);
1861 isr_decl(usb_hp);
1862 isr_decl(usb_lp);
1863 isr_decl(can_rx1);
1864 isr_decl(can_sce);
1865 isr_decl(exti9_5);
1866 isr_decl(tim1_brk);
1867 isr_decl(tim1_up);
1868 isr_decl(tim1_trg_com);
1869 isr_decl(tim1_cc);
1870 isr_decl(tim2);
1871 isr_decl(tim3);
1872 isr_decl(tim4);
1873 isr_decl(i2c1_ev);
1874 isr_decl(i2c1_er);
1875 isr_decl(i2c2_ev);
1876 isr_decl(i2c2_er);
1877 isr_decl(spi1);
1878 isr_decl(spi2);
1879 isr_decl(usart1);
1880 isr_decl(usart2);
1881 isr_decl(usart3);
1882 isr_decl(exti15_10);
1883 isr_decl(rtc_alarm);
1884 isr_decl(usb_wakeup);
1885 isr_decl(tim8_brk);
1886 isr_decl(tim8_up);
1887 isr_decl(tim8_trg_com);
1888 isr_decl(tim8_cc);
1889 isr_decl(adc3);
1890 isr_decl(fsmc);
1891 isr_decl(sdio);
1892 isr_decl(tim5);
1893 isr_decl(spi3);
1894 isr_decl(uart4);
1895 isr_decl(uart5);
1896 isr_decl(tim6);
1897 isr_decl(tim7);
1898 isr_decl(dma2_channel1);
1899 isr_decl(dma2_channel2);
1900 isr_decl(dma2_channel3);
1901 isr_decl(dma2_channel4_5);
1902
1903 #undef isr_decl
1904
1905 #define STM_ISR_WWDG_POS                0
1906 #define STM_ISR_PVD_POS                 1
1907 #define STM_ISR_TAMPER_STAMP_POS        2
1908 #define STM_ISR_RTC_WKUP_POS            3
1909 #define STM_ISR_FLASH_POS               4
1910 #define STM_ISR_RCC_POS                 5
1911 #define STM_ISR_EXTI0_POS               6
1912 #define STM_ISR_EXTI1_POS               7
1913 #define STM_ISR_EXTI2_POS               8
1914 #define STM_ISR_EXTI3_POS               9
1915 #define STM_ISR_EXTI4_POS               10
1916 #define STM_ISR_DMA1_CHANNEL1_POS       11
1917 #define STM_ISR_DMA1_CHANNEL2_POS       12
1918 #define STM_ISR_DMA1_CHANNEL3_POS       13
1919 #define STM_ISR_DMA1_CHANNEL4_POS       14
1920 #define STM_ISR_DMA1_CHANNEL5_POS       15
1921 #define STM_ISR_DMA1_CHANNEL6_POS       16
1922 #define STM_ISR_DMA1_CHANNEL7_POS       17
1923 #define STM_ISR_ADC1_2_POS              18
1924 #define STM_ISR_USB_HP_POS              19
1925 #define STM_ISR_USB_LP_POS              20
1926 #define STM_ISR_CAN_RX1_POS             21
1927 #define STM_ISR_CAN_SCE_POS             22
1928 #define STM_ISR_EXTI9_5_POS             23
1929 #define STM_ISR_TIM1_BRK_POS            24
1930 #define STM_ISR_TIM1_UP_POS             25
1931 #define STM_ISR_TIM1_TRG_COM_POS        26
1932 #define STM_ISR_TIM1_CC_POS             27
1933 #define STM_ISR_TIM2_POS                28
1934 #define STM_ISR_TIM3_POS                29
1935 #define STM_ISR_TIM4_POS                30
1936 #define STM_ISR_I2C1_EV_POS             31
1937 #define STM_ISR_I2C1_ER_POS             32
1938 #define STM_ISR_I2C2_EV_POS             33
1939 #define STM_ISR_I2C2_ER_POS             34
1940 #define STM_ISR_SPI1_POS                35
1941 #define STM_ISR_SPI2_POS                36
1942 #define STM_ISR_USART1_POS              37
1943 #define STM_ISR_USART2_POS              38
1944 #define STM_ISR_USART3_POS              39
1945 #define STM_ISR_EXTI15_10_POS           40
1946 #define STM_ISR_RTC_ALARM_POS           41
1947 #define STM_ISR_USB_WAKEUP_POS          42
1948 #define STM_ISR_TIM8_BRK_POS            43
1949 #define STM_ISR_TIM8_UP_POS             44
1950 #define STM_ISR_TIM8_TRG_COM_POS        45
1951 #define STM_ISR_TIM8_CC_POS             46
1952 #define STM_ISR_ADC3_POS                47
1953 #define STM_ISR_FSMC_POS                48
1954 #define STM_ISR_SDIO_POS                49
1955 #define STM_ISR_TIM5_POS                50
1956 #define STM_ISR_SPI3_POS                51
1957 #define STM_ISR_UART4_POS               52
1958 #define STM_ISR_UART5_POS               53
1959 #define STM_ISR_TIM6_POS                54
1960 #define STM_ISR_TIM7_POS                55
1961 #define STM_ISR_DMA2_CHANNEL1_POS       56
1962 #define STM_ISR_DMA2_CHANNEL2_POS       57
1963 #define STM_ISR_DMA2_CHANNEL3_POS       58
1964 #define STM_ISR_DMA3_CHANNEL4_5_POS     59
1965
1966 #endif