2 * Copyright © 2023 Keith Packard <keithp@keithp.com>
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation, either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
12 * General Public License for more details.
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
26 /* Switch to HSI while messing about */
27 stm_rcc.cr |= (1 << STM_RCC_CR_HSION);
28 while (!(stm_rcc.cr & (1 << STM_RCC_CR_HSIRDY)))
31 stm_rcc.cfgr = (stm_rcc.cfgr & ~(uint32_t) (STM_RCC_CFGR_SW_MASK << STM_RCC_CFGR_SW)) |
32 (STM_RCC_CFGR_SW_HSI << STM_RCC_CFGR_SW);
34 /* wait for system to switch to HSI */
35 while ((stm_rcc.cfgr & (STM_RCC_CFGR_SWS_MASK << STM_RCC_CFGR_SWS)) !=
36 (STM_RCC_CFGR_SWS_HSI << STM_RCC_CFGR_SWS))
39 /* Disable all interrupts */
44 stm_rcc.cr |= (1 << STM_RCC_CR_HSEBYP);
46 stm_rcc.cr &= ~(uint32_t) (1 << STM_RCC_CR_HSEBYP);
48 /* Enable HSE clock */
49 stm_rcc.cr |= (1 << STM_RCC_CR_HSEON);
50 while (!(stm_rcc.cr & (1 << STM_RCC_CR_HSERDY)))
53 #define STM_RCC_CFGR_SWS_TARGET_CLOCK (STM_RCC_CFGR_SWS_HSE << STM_RCC_CFGR_SWS)
54 #define STM_RCC_CFGR_SW_TARGET_CLOCK (STM_RCC_CFGR_SW_HSE)
55 #define STM_PLLSRC AO_HSE
56 #define STM_RCC_CFGR_PLLSRC_TARGET_CLOCK (STM_RCC_CFGR_PLLSRC_HSE << STM_RCC_CFGR_PLLSRC)
58 #define STM_HSI 16000000
59 #define STM_RCC_CFGR_SWS_TARGET_CLOCK (STM_RCC_CFGR_SWS_HSI << STM_RCC_CFGR_SWS)
60 #define STM_RCC_CFGR_SW_TARGET_CLOCK (STM_RCC_CFGR_SW_HSI)
61 #define STM_PLLSRC (STM_HSI/2)
62 #define STM_RCC_CFGR_PLLSRC_TARGET_CLOCK (STM_RCC_CFGR_PLLSRC_HSI_2 << STM_RCC_CFGR_PLLSRC)
65 #if !AO_HSE || HAS_ADC || HAS_ADC_SINGLE
66 /* Enable HSI RC clock 16MHz */
67 stm_rcc.cr |= (1 << STM_RCC_CR_HSION);
68 while (!(stm_rcc.cr & (1 << STM_RCC_CR_HSIRDY)))
73 /* Set flash latency to tolerate 32MHz SYSCLK -> 1 wait state */
75 /* Enable 64-bit access and prefetch */
76 stm_flash.acr |= (1 << STM_FLASH_ACR_ACC64);
77 stm_flash.acr |= (1 << STM_FLASH_ACR_PRFEN);
79 /* Enable 1 wait state so the CPU can run at 32MHz */
80 stm_flash.acr |= (1 << STM_FLASH_ACR_LATENCY);
83 /* Enable power interface clock */
84 stm_rcc.apb1enr |= (1 << STM_RCC_APB1ENR_PWREN);
87 /* Set voltage range to 1.8V */
89 /* poll VOSF bit in PWR_CSR. Wait until it is reset to 0 */
90 while ((stm_pwr.csr & (1 << STM_PWR_CSR_VOSF)) != 0)
93 /* Configure voltage scaling range */
95 cr &= ~(STM_PWR_CR_VOS_MASK << STM_PWR_CR_VOS);
96 cr |= (STM_PWR_CR_VOS_1_8 << STM_PWR_CR_VOS);
99 /* poll VOSF bit in PWR_CSR. Wait until it is reset to 0 */
100 while ((stm_pwr.csr & (1 << STM_PWR_CSR_VOSF)) != 0)
106 cfgr &= ~(STM_RCC_CFGR_HPRE_MASK << STM_RCC_CFGR_HPRE);
107 cfgr |= (AO_RCC_CFGR_HPRE_DIV << STM_RCC_CFGR_HPRE);
109 while ((stm_rcc.cfgr & (STM_RCC_CFGR_HPRE_MASK << STM_RCC_CFGR_HPRE)) !=
110 (AO_RCC_CFGR_HPRE_DIV << STM_RCC_CFGR_HPRE))
113 /* APB1 Prescaler = AO_APB1_PRESCALER */
115 cfgr &= ~(STM_RCC_CFGR_PPRE1_MASK << STM_RCC_CFGR_PPRE1);
116 cfgr |= (AO_RCC_CFGR_PPRE1_DIV << STM_RCC_CFGR_PPRE1);
119 /* APB2 Prescaler = AO_APB2_PRESCALER */
121 cfgr &= ~(STM_RCC_CFGR_PPRE2_MASK << STM_RCC_CFGR_PPRE2);
122 cfgr |= (AO_RCC_CFGR_PPRE2_DIV << STM_RCC_CFGR_PPRE2);
125 /* Disable the PLL */
126 stm_rcc.cr &= ~(1UL << STM_RCC_CR_PLLON);
127 while (stm_rcc.cr & (1UL << STM_RCC_CR_PLLRDY))
132 cfgr &= ~(STM_RCC_CFGR_PLLMUL_MASK << STM_RCC_CFGR_PLLMUL);
134 cfgr |= (AO_RCC_CFGR_PLLMUL << STM_RCC_CFGR_PLLMUL);
137 cfgr &= ~(1UL << STM_RCC_CFGR_PLLSRC);
138 cfgr |= STM_RCC_CFGR_PLLSRC_TARGET_CLOCK;
142 /* Enable the PLL and wait for it */
143 stm_rcc.cr |= (1 << STM_RCC_CR_PLLON);
144 while (!(stm_rcc.cr & (1 << STM_RCC_CR_PLLRDY)))
147 /* Switch to the PLL for the system clock */
150 cfgr &= ~(STM_RCC_CFGR_SW_MASK << STM_RCC_CFGR_SW);
151 cfgr |= (STM_RCC_CFGR_SW_PLL << STM_RCC_CFGR_SW);
154 uint32_t c, part, mask, val;
157 mask = (STM_RCC_CFGR_SWS_MASK << STM_RCC_CFGR_SWS);
158 val = (STM_RCC_CFGR_SWS_PLL << STM_RCC_CFGR_SWS);
165 stm_rcc.apb2rstr = 0xffff;
166 stm_rcc.apb1rstr = 0xffff;
167 stm_rcc.ahbrstr = 0x3f;
168 stm_rcc.ahbenr = (1 << STM_RCC_AHBENR_FLITFEN);
172 stm_rcc.apb1rstr = 0;
173 stm_rcc.apb2rstr = 0;
176 /* Clear reset flags */
177 stm_rcc.csr |= (1 << STM_RCC_CSR_RMVF);
181 /* Output SYSCLK on PA8 for measurments */
183 stm_rcc.ahbenr |= (1 << STM_RCC_AHBENR_GPIOAEN);
185 stm_afr_set(&stm_gpioa, 8, STM_AFR_AF0);
186 stm_moder_set(&stm_gpioa, 8, STM_MODER_ALTERNATE);
187 stm_ospeedr_set(&stm_gpioa, 8, STM_OSPEEDR_40MHz);
189 stm_rcc.cfgr |= (STM_RCC_CFGR_MCOPRE_DIV_1 << STM_RCC_CFGR_MCOPRE);
190 stm_rcc.cfgr |= (STM_RCC_CFGR_MCOSEL_HSE << STM_RCC_CFGR_MCOSEL);