2 * Copyright © 2016 Keith Packard <keithp@keithp.com>
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation, either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
12 * General Public License for more details.
18 /* VGA output from the SPI port */
21 long dot_clock; /* in Hz */
23 /* All timings are in pixels, with the first pixel out at 0,0 */
24 int hactive; /* active pixels */
25 int hsync_start; /* start of hsync pulse */
26 int hsync_end; /* end of hsync pulse */
27 int htotal; /* total h pixels */
29 int vactive; /* active scalines */
30 int vsync_start; /* start of vsync pulse */
31 int vsync_end; /* end of vsync pulse */
32 int vtotal; /* total scanlines */
35 const struct ao_modeline vga_640x480x60 = {
36 .dot_clock = 23856000, /* 23.86MHz dot, 29.82kHz line, 60.00Hz frame */
49 const struct ao_modeline vga_640x480x30 = {
50 .dot_clock = 120000000, /* 12.00MHz dot, 29.82kHz line, 30.00Hz frame */
63 #define mode vga_640x480x60
65 #define WIDTH_BYTES (AO_VGA_WIDTH >> 3)
66 #define SCANOUT ((WIDTH_BYTES + 2) >> 1)
68 uint32_t ao_vga_fb[AO_VGA_STRIDE * AO_VGA_HEIGHT];
70 static uint32_t *scanline;
72 #define DMA_INDEX STM_DMA_INDEX(STM_DMA_CHANNEL_SPI2_TX)
77 #define DMA_CCR(en) ((0 << STM_DMA_CCR_MEM2MEM) | \
78 (STM_DMA_CCR_PL_VERY_HIGH << STM_DMA_CCR_PL) | \
79 (STM_DMA_CCR_MSIZE_16 << STM_DMA_CCR_MSIZE) | \
80 (STM_DMA_CCR_PSIZE_16 << STM_DMA_CCR_PSIZE) | \
81 (1 << STM_DMA_CCR_MINC) | \
82 (0 << STM_DMA_CCR_PINC) | \
83 (0 << STM_DMA_CCR_CIRC) | \
84 (STM_DMA_CCR_DIR_MEM_TO_PER << STM_DMA_CCR_DIR) | \
85 (0 << STM_DMA_CCR_TCIE) | \
86 (en << STM_DMA_CCR_EN))
90 void stm_tim2_isr(void)
92 ao_arch_block_interrupts();
95 stm_dma.channel[DMA_INDEX].ccr = DMA_CCR(0);
96 /* Reset DMA engine for the next scanline */
97 stm_dma.channel[DMA_INDEX].cndtr = SCANOUT;
99 stm_dma.channel[DMA_INDEX].ccr = DMA_CCR(1);
101 stm_tim2.sr = ~(1 << STM_TIM234_SR_CC2IF);
103 if (vblank_off <= line && line < (AO_VGA_HEIGHT << 1) + vblank_off + 12) {
105 if ((line - vblank_off) & 1)
106 scanline += AO_VGA_STRIDE;
108 scanline = ao_vga_fb;
111 stm_dma.channel[DMA_INDEX].cmar = scanline;
112 ao_arch_release_interrupts();
118 ao_solid(0x0, AO_ALLONES,
126 ao_vga_fb + 10 * AO_VGA_STRIDE,
134 ao_vga_fb + 220 * AO_VGA_STRIDE,
141 ao_vga_fb + 10 * AO_VGA_STRIDE,
148 ao_vga_fb + 220 * AO_VGA_STRIDE,
154 ao_text("Hello, Bdale!",
155 ao_vga_fb + 100 * AO_VGA_STRIDE,
165 ao_vga_fb + (240 - 7) * AO_VGA_STRIDE,
173 /* Initialize spi2 using PB15 for output */
174 stm_rcc.ahbenr |= (1 << STM_RCC_AHBENR_GPIOBEN);
176 stm_ospeedr_set(&stm_gpiob, 15, STM_OSPEEDR_40MHz);
177 stm_afr_set(&stm_gpiob, 15, STM_AFR_AF5);
180 stm_rcc.apb1enr |= (1 << STM_RCC_APB1ENR_SPI2EN);
182 stm_spi2.cr1 = ((1 << STM_SPI_CR1_BIDIMODE) | /* Two wire mode */
183 (1 << STM_SPI_CR1_BIDIOE) |
184 (0 << STM_SPI_CR1_CRCEN) | /* CRC disabled */
185 (0 << STM_SPI_CR1_CRCNEXT) |
186 (1 << STM_SPI_CR1_DFF) |
187 (0 << STM_SPI_CR1_RXONLY) |
188 (1 << STM_SPI_CR1_SSM) | /* Software SS handling */
189 (1 << STM_SPI_CR1_SSI) | /* ... */
190 (1 << STM_SPI_CR1_LSBFIRST) | /* Little endian */
191 (1 << STM_SPI_CR1_SPE) | /* Enable SPI unit */
192 (0 << STM_SPI_CR1_BR) | /* baud rate to pclk/2 */
193 (1 << STM_SPI_CR1_MSTR) |
194 (0 << STM_SPI_CR1_CPOL) | /* Format 0 */
195 (0 << STM_SPI_CR1_CPHA));
196 stm_spi2.cr2 = ((0 << STM_SPI_CR2_TXEIE) |
197 (0 << STM_SPI_CR2_RXNEIE) |
198 (0 << STM_SPI_CR2_ERRIE) |
199 (0 << STM_SPI_CR2_SSOE) |
200 (1 << STM_SPI_CR2_TXDMAEN) |
201 (0 << STM_SPI_CR2_RXDMAEN));
206 /* Grab the DMA channel for SPI2 MOSI */
207 stm_dma.channel[DMA_INDEX].cpar = &stm_spi2.dr;
208 stm_dma.channel[DMA_INDEX].cmar = ao_vga_fb;
210 /* hclock on timer 2 */
212 /* Turn on timer 2 */
213 stm_rcc.apb1enr |= (1 << STM_RCC_APB1ENR_TIM2EN);
216 stm_rcc.ahbenr |= (1 << STM_RCC_AHBENR_GPIOAEN);
220 /* Disable channels while modifying */
223 /* Channel 1 hsync PWM values */
224 stm_tim2.ccr1 = mode.hsync_end - mode.hsync_start;
226 /* Channel 2 trigger scanout */
227 /* wait for the time to start scanout */
230 stm_tim2.ccmr1 = ((0 << STM_TIM234_CCMR1_OC2CE) |
231 (STM_TIM234_CCMR1_OC2M_SET_HIGH_ON_MATCH << STM_TIM234_CCMR1_OC2M) |
232 (1 << STM_TIM234_CCMR1_OC2PE) |
233 (0 << STM_TIM234_CCMR1_OC2FE) |
235 (0 << STM_TIM234_CCMR1_OC1CE) |
236 (STM_TIM234_CCMR1_OC1M_PWM_MODE_1 << STM_TIM234_CCMR1_OC1M) |
237 (1 << STM_TIM234_CCMR1_OC1PE) |
238 (0 << STM_TIM234_CCMR1_OC1FE) |
239 (STM_TIM234_CCMR1_CC1S_OUTPUT << STM_TIM234_CCMR1_CC1S));
241 stm_tim2.arr = mode.htotal;
244 /* Update the register contents */
245 stm_tim2.egr |= (1 << STM_TIM234_EGR_UG);
247 /* Enable the timer */
249 /* Enable the output */
250 stm_tim2.ccer = ((0 << STM_TIM234_CCER_CC1NP) |
251 (STM_TIM234_CCER_CC1P_ACTIVE_LOW << STM_TIM234_CCER_CC1P) |
252 (1 << STM_TIM234_CCER_CC1E));
254 stm_tim2.cr2 = ((0 << STM_TIM234_CR2_TI1S) |
255 (STM_TIM234_CR2_MMS_UPDATE << STM_TIM234_CR2_MMS) |
256 (0 << STM_TIM234_CR2_CCDS));
260 stm_tim2.dier = ((1 << STM_TIM234_DIER_CC2IE));
262 stm_tim2.cr1 = ((STM_TIM234_CR1_CKD_1 << STM_TIM234_CR1_CKD) |
263 (1 << STM_TIM234_CR1_ARPE) |
264 (STM_TIM234_CR1_CMS_EDGE << STM_TIM234_CR1_CMS) |
265 (STM_TIM234_CR1_DIR_UP << STM_TIM234_CR1_DIR) |
266 (0 << STM_TIM234_CR1_OPM) |
267 (1 << STM_TIM234_CR1_URS) |
268 (0 << STM_TIM234_CR1_UDIS) |
269 (0 << STM_TIM234_CR1_CEN));
273 /* PA5 is Timer 2 CH1 output */
274 stm_ospeedr_set(&stm_gpioa, 5, STM_OSPEEDR_40MHz);
275 stm_afr_set(&stm_gpioa, 5, STM_AFR_AF1);
277 /* Turn on timer 3, slaved to timer 1 using ITR1 (table 61) */
279 /* Use CH1 on PB6 (AF2) */
281 stm_rcc.apb1enr |= (1 << STM_RCC_APB1ENR_TIM3EN);
284 stm_rcc.ahbenr |= (1 << STM_RCC_AHBENR_GPIOBEN);
289 /* Channel 1 vsync PWM values */
290 stm_tim3.ccr1 = mode.vsync_end - mode.vsync_start;
291 stm_tim3.ccmr1 = ((0 << STM_TIM234_CCMR1_OC2CE) |
292 (0 << STM_TIM234_CCMR1_OC2PE) |
293 (0 << STM_TIM234_CCMR1_OC2FE) |
295 (0 << STM_TIM234_CCMR1_OC1CE) |
296 (STM_TIM234_CCMR1_OC1M_PWM_MODE_1 << STM_TIM234_CCMR1_OC1M) |
297 (1 << STM_TIM234_CCMR1_OC1PE) |
298 (0 << STM_TIM234_CCMR1_OC1FE) |
299 (STM_TIM234_CCMR1_CC1S_OUTPUT << STM_TIM234_CCMR1_CC1S));
301 stm_tim3.arr = mode.vtotal;
304 /* Update the register contents */
305 stm_tim3.egr |= (1 << STM_TIM234_EGR_UG);
307 /* Enable the timer */
309 /* Enable the output */
310 stm_tim3.ccer = ((0 << STM_TIM234_CCER_CC1NP) |
311 (STM_TIM234_CCER_CC1P_ACTIVE_LOW << STM_TIM234_CCER_CC1P) |
312 (1 << STM_TIM234_CCER_CC1E));
314 stm_tim3.cr2 = ((0 << STM_TIM234_CR2_TI1S) |
315 (STM_TIM234_CR2_MMS_UPDATE << STM_TIM234_CR2_MMS) |
316 (0 << STM_TIM234_CR2_CCDS));
319 stm_tim3.smcr = ((0 << STM_TIM234_SMCR_ETP) |
320 (0 << STM_TIM234_SMCR_ECE) |
321 (STM_TIM234_SMCR_ETPS_OFF << STM_TIM234_SMCR_ETPS) |
322 (STM_TIM234_SMCR_ETF_NONE << STM_TIM234_SMCR_ETF) |
323 (0 << STM_TIM234_SMCR_MSM) |
324 (STM_TIM234_SMCR_TS_ITR1 << STM_TIM234_SMCR_TS) |
325 (0 << STM_TIM234_SMCR_OCCS) |
326 (STM_TIM234_SMCR_SMS_EXTERNAL_CLOCK << STM_TIM234_SMCR_SMS));
330 stm_tim3.cr1 = ((STM_TIM234_CR1_CKD_1 << STM_TIM234_CR1_CKD) |
331 (1 << STM_TIM234_CR1_ARPE) |
332 (STM_TIM234_CR1_CMS_EDGE << STM_TIM234_CR1_CMS) |
333 (STM_TIM234_CR1_DIR_UP << STM_TIM234_CR1_DIR) |
334 (0 << STM_TIM234_CR1_OPM) |
335 (1 << STM_TIM234_CR1_URS) |
336 (0 << STM_TIM234_CR1_UDIS) |
337 (1 << STM_TIM234_CR1_CEN));
341 /* PB4 is Timer 3 CH1 output */
342 stm_ospeedr_set(&stm_gpiob, 4, STM_OSPEEDR_40MHz);
343 stm_afr_set(&stm_gpiob, 4, STM_AFR_AF2);
346 /* Enable the scanline interrupt */
347 stm_nvic_set_priority(STM_ISR_TIM2_POS, 0);
348 stm_nvic_set_enable(STM_ISR_TIM2_POS);
352 ao_vga_enable(int enable)
357 stm_tim2.cr1 |= (1 << STM_TIM234_CR1_CEN);
358 stm_systick.csr &= ~(1 << STM_SYSTICK_CSR_ENABLE);
360 stm_tim2.cr1 &= ~(1 << STM_TIM234_CR1_CEN);
361 stm_systick.csr |= (1 << STM_SYSTICK_CSR_ENABLE);