altosui: Add config and pyro tabs to graph widget

[fw/altos] / src / stm32f1 / ao_clock.c

diff --git a/src/stm32f1/ao_clock.c b/src/stm32f1/ao_clock.c
index 1ce32a90343c8838c5df9435d3bd0069abaf6771..899923dc5cfc0f501db1a554f774e4071b7b1b41 100644 (file)
--- a/src/stm32f1/ao_clock.c
+++ b/src/stm32f1/ao_clock.c
@@ -69,16 +69,12 @@ ao_clock_init(void)
                asm("nop");
 #endif
 
-#if 0
-       /* Set flash latency to tolerate 32MHz SYSCLK  -> 1 wait state */
+       /* Set flash latency to tolerate 72MHz SYSCLK  -> 2 wait states */
 
        /* Enable 64-bit access and prefetch */
-       stm_flash.acr |= (1 << STM_FLASH_ACR_ACC64);
-       stm_flash.acr |= (1 << STM_FLASH_ACR_PRFEN);
-
-       /* Enable 1 wait state so the CPU can run at 32MHz */
-       stm_flash.acr |= (1 << STM_FLASH_ACR_LATENCY);
-#endif
+       stm_flash.acr = ((1 << STM_FLASH_ACR_PRFTBE) |
+                        (0 << STM_FLASH_ACR_HLFCYA) |
+                        (STM_FLASH_ACR_LATENCY_2 << STM_FLASH_ACR_LATENCY));
 
        /* Enable power interface clock */
        stm_rcc.apb1enr |= (1 << STM_RCC_APB1ENR_PWREN);
@@ -122,17 +118,26 @@ ao_clock_init(void)
        cfgr |= (AO_RCC_CFGR_PPRE2_DIV << STM_RCC_CFGR_PPRE2);
        stm_rcc.cfgr = cfgr;
 
+       /* ADC Prescaler */
+       cfgr = stm_rcc.cfgr;
+       cfgr &= ~(STM_RCC_CFGR_ADCPRE_MASK << STM_RCC_CFGR_ADCPRE);
+       cfgr |= (AO_RCC_CFGR_ADCPRE << STM_RCC_CFGR_ADCPRE);
+       stm_rcc.cfgr = cfgr;
+
        /* Disable the PLL */
        stm_rcc.cr &= ~(1UL << STM_RCC_CR_PLLON);
        while (stm_rcc.cr & (1UL << STM_RCC_CR_PLLRDY))
                asm("nop");
 
-       /* PLLVCO */
+       /* PLLMUL */
        cfgr = stm_rcc.cfgr;
        cfgr &= ~(STM_RCC_CFGR_PLLMUL_MASK << STM_RCC_CFGR_PLLMUL);
-
        cfgr |= (AO_RCC_CFGR_PLLMUL << STM_RCC_CFGR_PLLMUL);
 
+       /* PLLXTPRE */
+       cfgr &= ~(STM_RCC_CFGR_PLLXTPRE_MASK << STM_RCC_CFGR_PLLXTPRE);
+       cfgr |= (AO_RCC_CFGR_PLLXTPRE << STM_RCC_CFGR_PLLXTPRE);
+
        /* PLL source */
        cfgr &= ~(1UL << STM_RCC_CFGR_PLLSRC);
        cfgr |= STM_RCC_CFGR_PLLSRC_TARGET_CLOCK;
@@ -176,6 +181,13 @@ ao_clock_init(void)
        /* Clear reset flags */
        stm_rcc.csr |= (1 << STM_RCC_CSR_RMVF);
 
+       /* Enable AFIO */
+       stm_rcc.apb2enr |= (1 << STM_RCC_APB2ENR_AFIOEN);
+
+       /* Release PB3, PA15 and PB4 from JTAG use */
+       stm_afio.mapr = (stm_afio.mapr &
+                        ~(STM_AFIO_MAPR_SWJ_CFG_MASK << STM_AFIO_MAPR_SWJ_CFG)) |
+               STM_AFIO_MAPR_SWJ_CFG_SW_DP << STM_AFIO_MAPR_SWJ_CFG;
 
 #if DEBUG_THE_CLOCK
        /* Output SYSCLK on PA8 for measurments */