*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
ao_spi_send_fixed(uint8_t value, uint16_t len, uint8_t spi_index);
void
-ao_spi_send_sync(void *block, uint16_t len, uint8_t spi_index);
+ao_spi_send_sync(const void *block, uint16_t len, uint8_t spi_index);
+
+void
+ao_spi_start_bytes(uint8_t spi_index);
+
+void
+ao_spi_stop_bytes(uint8_t spi_index);
static inline void
ao_spi_send_byte(uint8_t byte, uint8_t spi_index)
break;
}
- stm_spi->cr2 = ((0 << STM_SPI_CR2_TXEIE) |
- (0 << STM_SPI_CR2_RXNEIE) |
- (0 << STM_SPI_CR2_ERRIE) |
- (0 << STM_SPI_CR2_SSOE) |
- (0 << STM_SPI_CR2_TXDMAEN) |
- (0 << STM_SPI_CR2_RXDMAEN));
-
- /* Clear RXNE */
+ while (!(stm_spi->sr & (1 << STM_SPI_SR_TXE)))
+ ;
+ stm_spi->dr = byte;
+ while (!(stm_spi->sr & (1 << STM_SPI_SR_RXNE)))
+ ;
(void) stm_spi->dr;
+}
- while (!(stm_spi->sr & (1 << STM_SPI_SR_TXE)));
- stm_spi->dr = byte;
+static inline uint8_t
+ao_spi_recv_byte(uint8_t spi_index)
+{
+ struct stm_spi *stm_spi;
+
+ switch (AO_SPI_INDEX(spi_index)) {
+ case 0:
+ stm_spi = &stm_spi1;
+ break;
+ case 1:
+ stm_spi = &stm_spi2;
+ break;
+ }
+
+ while (!(stm_spi->sr & (1 << STM_SPI_SR_TXE)))
+ ;
+ stm_spi->dr = 0xff;
+ while (!(stm_spi->sr & (1 << STM_SPI_SR_RXNE)))
+ ;
+ return stm_spi->dr;
}
void
ao_spi_recv(void *block, uint16_t len, uint8_t spi_index);
void
-ao_spi_duplex(void *out, void *in, uint16_t len, uint8_t spi_index);
+ao_spi_duplex(const void *out, void *in, uint16_t len, uint8_t spi_index);
extern uint16_t ao_spi_speed[STM_NUM_SPI];
void
ao_dma_done_transfer(uint8_t index);
-void
-ao_dma_abort(uint8_t index);
-
void
ao_dma_alloc(uint8_t index);
typedef uint32_t ao_arch_irq_t;
+static inline void
+ao_arch_block_interrupts(void) {
+ uint32_t basepri = AO_STM_NVIC_BASEPRI_MASK;
+ asm("msr basepri,%0" : : "r" (basepri));
+}
+
+static inline void
+ao_arch_release_interrupts(void) {
+ uint32_t basepri = 0x00;
+ asm("msr basepri,%0" : : "r" (basepri));
+}
+
static inline uint32_t
ao_arch_irqsave(void) {
- uint32_t primask;
- asm("mrs %0,primask" : "=&r" (primask));
+ uint32_t basepri;
+ asm("mrs %0,basepri" : "=r" (basepri));
ao_arch_block_interrupts();
- return primask;
+ return basepri;
}
static inline void
-ao_arch_irqrestore(uint32_t primask) {
- asm("msr primask,%0" : : "r" (primask));
+ao_arch_irqrestore(uint32_t basepri) {
+ asm("msr basepri,%0" : : "r" (basepri));
}
static inline void
static inline void
ao_arch_irq_check(void) {
- uint32_t primask;
- asm("mrs %0,primask" : "=&r" (primask));
- if ((primask & 1) == 0)
+ uint32_t basepri;
+ asm("mrs %0,basepri" : "=r" (basepri));
+ if (basepri == 0)
ao_panic(AO_PANIC_IRQ);
}
/* APSR */
ARM_PUSH32(sp, 0);
- /* PRIMASK with interrupts enabled */
+ /* BASEPRI with interrupts enabled */
ARM_PUSH32(sp, 0);
task->sp = sp;
asm("mrs r0,apsr");
asm("push {r0}");
- /* Save PRIMASK */
- asm("mrs r0,primask");
+ /* Save BASEPRI */
+ asm("mrs r0,basepri");
asm("push {r0}");
}
/* Switch stacks */
asm("mov sp, %0" : : "r" (sp) );
- /* Restore PRIMASK */
+ /* Restore BASEPRI */
asm("pop {r0}");
- asm("msr primask,r0");
+ asm("msr basepri,r0");
/* Restore APSR */
asm("pop {r0}");
asm("mrs %0,msp" : "=&r" (sp));
asm("msr psp,%0" : : "r" (sp));
- asm("mrs %0,control" : "=&r" (control));
+ asm("mrs %0,control" : "=r" (control));
control |= (1 << 1);
asm("msr control,%0" : : "r" (control));
asm("isb");
#endif
-#define ao_arch_wait_interrupt() do { \
- asm("\twfi\n"); \
- ao_arch_release_interrupts(); \
- asm(".global ao_idle_loc\nao_idle_loc:"); \
- ao_arch_block_interrupts(); \
- } while (0)
+static inline void
+ao_arch_wait_interrupt(void) {
+ uint32_t enable_int = 0x00;
+ uint32_t disable_int = AO_STM_NVIC_BASEPRI_MASK;
+
+ asm(
+ "dsb\n" /* Serialize data */
+ "isb\n" /* Serialize instructions */
+ "cpsid i\n" /* Block all interrupts */
+ "msr basepri,%0\n" /* Allow all interrupts through basepri */
+ "wfi\n" /* Wait for an interrupt */
+ "cpsie i\n" /* Allow all interrupts */
+ "msr basepri,%1\n" /* Block interrupts through basepri */
+ : : "r" (enable_int), "r" (disable_int));
+}
#define ao_arch_critical(b) do { \
uint32_t __mask = ao_arch_irqsave(); \