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altos: Allow STM DMA channels to be reserved for one use
[fw/altos]
/
src
/
stm
/
ao_dma_stm.c
diff --git
a/src/stm/ao_dma_stm.c
b/src/stm/ao_dma_stm.c
index 785235a8023cfe94512ce35c5a34ef46c7201182..21390748b86dae82eddaec7e2662be60e38aa6a2 100644
(file)
--- a/
src/stm/ao_dma_stm.c
+++ b/
src/stm/ao_dma_stm.c
@@
-26,6
+26,7
@@
struct ao_dma_config {
uint8_t ao_dma_done[NUM_DMA];
static struct ao_dma_config ao_dma_config[NUM_DMA];
uint8_t ao_dma_done[NUM_DMA];
static struct ao_dma_config ao_dma_config[NUM_DMA];
+static uint8_t ao_dma_allocated[NUM_DMA];
static uint8_t ao_dma_mutex[NUM_DMA];
static uint8_t ao_dma_active;
static uint8_t ao_dma_mutex[NUM_DMA];
static uint8_t ao_dma_active;
@@
-60,7
+61,12
@@
ao_dma_set_transfer(uint8_t index,
uint16_t count,
uint32_t ccr)
{
uint16_t count,
uint32_t ccr)
{
- ao_mutex_get(&ao_dma_mutex[index]);
+ if (ao_dma_allocated[index]) {
+ if (ao_dma_mutex[index])
+ ao_panic(AO_PANIC_DMA);
+ ao_dma_mutex[index] = 1;
+ } else
+ ao_mutex_get(&ao_dma_mutex[index]);
ao_arch_critical(
if (ao_dma_active++ == 0)
stm_rcc.ahbenr |= (1 << STM_RCC_AHBENR_DMA1EN);
ao_arch_critical(
if (ao_dma_active++ == 0)
stm_rcc.ahbenr |= (1 << STM_RCC_AHBENR_DMA1EN);
@@
-93,7
+99,10
@@
ao_dma_done_transfer(uint8_t index)
if (--ao_dma_active == 0)
stm_rcc.ahbenr &= ~(1 << STM_RCC_AHBENR_DMA1EN);
);
if (--ao_dma_active == 0)
stm_rcc.ahbenr &= ~(1 << STM_RCC_AHBENR_DMA1EN);
);
- ao_mutex_put(&ao_dma_mutex[index]);
+ if (ao_dma_allocated[index])
+ ao_dma_mutex[index] = 0;
+ else
+ ao_mutex_put(&ao_dma_mutex[index]);
}
void
}
void
@@
-102,6
+111,14
@@
ao_dma_abort(uint8_t index)
stm_dma.channel[index].ccr &= ~(1 << STM_DMA_CCR_EN);
}
stm_dma.channel[index].ccr &= ~(1 << STM_DMA_CCR_EN);
}
+void
+ao_dma_alloc(uint8_t index)
+{
+ if (ao_dma_allocated[index])
+ ao_panic(AO_PANIC_DMA);
+ ao_dma_allocated[index] = 1;
+}
+
void
ao_dma_init(void)
{
void
ao_dma_init(void)
{
@@
-110,6
+127,8
@@
ao_dma_init(void)
for (index = 0; index < STM_NUM_DMA; index++) {
stm_nvic_set_enable(STM_ISR_DMA1_CHANNEL1_POS + index);
stm_nvic_set_priority(STM_ISR_DMA1_CHANNEL1_POS + index, 4);
for (index = 0; index < STM_NUM_DMA; index++) {
stm_nvic_set_enable(STM_ISR_DMA1_CHANNEL1_POS + index);
stm_nvic_set_priority(STM_ISR_DMA1_CHANNEL1_POS + index, 4);
+ ao_dma_allocated[index] = 0;
+ ao_dma_mutex[index] = 0;
}
}
}
}