2 * Copyright © 2012 Keith Packard <keithp@keithp.com>
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
12 * General Public License for more details.
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
21 #include "ao_product.h"
26 #define USB_DEBUG_DATA 0
29 #ifndef AO_PA11_PA12_RMP
30 #error "must define AO_PA11_PA12_RMP"
33 #ifndef AO_POWER_MANAGEMENT
34 #define AO_POWER_MANAGEMENT 0
38 #define USE_USB_STDIO 1
42 #define AO_USB_OUT_SLEEP_ADDR (&ao_stdin_ready)
44 #define AO_USB_OUT_SLEEP_ADDR (&ao_usb_out_avail)
48 #define debug(format, args...) printf(format, ## args);
50 #define debug(format, args...)
54 #define debug_data(format, args...) printf(format, ## args);
56 #define debug_data(format, args...)
60 uint8_t dir_type_recip;
67 static uint8_t ao_usb_ep0_state;
69 /* Pending EP0 IN data */
70 static const uint8_t *ao_usb_ep0_in_data; /* Remaining data */
71 static uint8_t ao_usb_ep0_in_len; /* Remaining amount */
73 /* Temp buffer for smaller EP0 in data */
74 static uint8_t ao_usb_ep0_in_buf[2];
76 /* Pending EP0 OUT data */
77 static uint8_t *ao_usb_ep0_out_data;
78 static uint8_t ao_usb_ep0_out_len;
81 * Objects allocated in special USB memory
84 /* Buffer description tables */
86 #define ao_usb_bdt ((union stm_usb_bdt *) (intptr_t) (void *) stm_usb_sram)
88 /* Pointer to ep0 tx/rx buffers in USB memory */
89 static uint16_t ao_usb_ep0_tx_offset;
90 static uint16_t ao_usb_ep0_rx_offset;
93 /* Pointer to interrupt buffer in USB memory */
94 static uint16_t ao_usb_int_tx_offset;
97 /* Pointer to bulk data tx/rx buffers in USB memory */
99 static uint16_t ao_usb_in_tx_offset;
100 static uint8_t ao_usb_in_tx_which;
101 static uint8_t ao_usb_tx_count;
105 static uint16_t ao_usb_out_rx_offset;
106 static uint8_t ao_usb_out_rx_which;
107 static uint8_t ao_usb_rx_count, ao_usb_rx_pos;
111 static uint16_t ao_usb_in_tx2_offset;
112 static uint8_t ao_usb_in_tx2_which;
113 static uint8_t ao_usb_tx2_count;
117 static uint16_t ao_usb_in_tx3_offset;
118 static uint8_t ao_usb_in_tx3_which;
119 static uint8_t ao_usb_tx3_count;
123 * End point register indices
126 #define AO_USB_CONTROL_EPR 0
127 #define AO_USB_INT_EPR 1
128 #define AO_USB_OUT_EPR 2
129 #define AO_USB_IN_EPR 3
130 #define AO_USB_IN2_EPR 4
131 #define AO_USB_IN3_EPR 5
133 /* Marks when we don't need to send an IN packet.
134 * This happens only when the last IN packet is not full,
135 * otherwise the host will expect to keep seeing packets.
136 * Send a zero-length packet as required
138 static uint8_t ao_usb_in_flushed;
140 /* Marks when we have delivered an IN packet to the hardware
141 * and it has not been received yet. ao_sleep on this address
142 * to wait for it to be delivered.
144 static uint8_t ao_usb_in_pending;
147 /* Marks when we have delivered an IN packet to the hardware
148 * and it has not been received yet. ao_sleep on this address
149 * to wait for it to be delivered.
151 static uint8_t ao_usb_in2_pending;
152 static uint16_t in2_count;
153 static uint8_t ao_usb_in2_flushed;
157 /* Marks when we have delivered an IN packet to the hardware
158 * and it has not been received yet. ao_sleep on this address
159 * to wait for it to be delivered.
161 static uint8_t ao_usb_in3_pending;
162 static uint16_t in3_count;
163 static uint8_t ao_usb_in3_flushed;
166 /* Marks when an OUT packet has been received by the hardware
167 * but not pulled to the shadow buffer.
169 static uint8_t ao_usb_out_avail;
170 uint8_t ao_usb_running;
171 static uint8_t ao_usb_configuration;
173 #define AO_USB_EP0_GOT_SETUP 1
174 #define AO_USB_EP0_GOT_RX_DATA 2
175 #define AO_USB_EP0_GOT_TX_ACK 4
177 static uint8_t ao_usb_ep0_receive;
178 static uint8_t ao_usb_address;
179 static uint8_t ao_usb_address_pending;
181 static inline uint32_t set_toggle(uint32_t current_value,
183 uint32_t desired_value)
185 return (current_value ^ desired_value) & mask;
188 static inline uint16_t *ao_usb_packet_buffer_addr(uint16_t sram_addr)
190 return (uint16_t *) (void *) (stm_usb_sram + sram_addr);
193 static inline uint16_t ao_usb_packet_get(uint16_t sram_addr)
195 return ao_usb_packet_buffer_addr(sram_addr)[0];
198 static inline void ao_usb_packet_put(uint16_t sram_addr, uint16_t val)
200 ao_usb_packet_buffer_addr(sram_addr)[0] = val;
203 static inline uint16_t ao_usb_packet_buffer_offset(uint16_t *addr)
205 return (uint16_t) ((uint8_t *) addr - stm_usb_sram);
208 static inline uint32_t ao_usb_epr_stat_rx(uint32_t epr) {
209 return (epr >> STM_USB_EPR_STAT_RX) & STM_USB_EPR_STAT_RX_MASK;
212 static inline uint32_t ao_usb_epr_stat_tx(uint32_t epr) {
213 return (epr >> STM_USB_EPR_STAT_TX) & STM_USB_EPR_STAT_TX_MASK;
216 static inline uint32_t ao_usb_epr_ctr_rx(uint32_t epr) {
217 return (epr >> STM_USB_EPR_CTR_RX) & 1;
220 static inline uint32_t ao_usb_epr_ctr_tx(uint32_t epr) {
221 return (epr >> STM_USB_EPR_CTR_TX) & 1;
224 static inline uint32_t ao_usb_epr_setup(uint32_t epr) {
225 return (epr >> STM_USB_EPR_SETUP) & 1;
228 static inline uint32_t ao_usb_epr_dtog_rx(uint32_t epr) {
229 return (epr >> STM_USB_EPR_DTOG_RX) & 1;
232 static inline uint32_t ao_usb_epr_sw_buf_tx(uint32_t epr) {
233 return (epr >> STM_USB_EPR_SW_BUF_TX) & 1;
236 static inline uint32_t ao_usb_epr_dtog_tx(uint32_t epr) {
237 return (epr >> STM_USB_EPR_DTOG_TX) & 1;
240 static inline uint32_t ao_usb_epr_sw_buf_rx(uint32_t epr) {
241 return (epr >> STM_USB_EPR_SW_BUF_RX) & 1;
245 * Set current device address and mark the
246 * interface as active
249 ao_usb_set_address(uint8_t address)
251 debug("ao_usb_set_address %02x\n", address);
252 stm_usb.daddr = (1 << STM_USB_DADDR_EF) | address;
253 ao_usb_address_pending = 0;
257 * Write these values to preserve register contents under HW changes
260 #define STM_USB_EPR_INVARIANT ((1 << STM_USB_EPR_CTR_RX) | \
261 (STM_USB_EPR_DTOG_RX_WRITE_INVARIANT << STM_USB_EPR_DTOG_RX) | \
262 (STM_USB_EPR_STAT_RX_WRITE_INVARIANT << STM_USB_EPR_STAT_RX) | \
263 (1 << STM_USB_EPR_CTR_TX) | \
264 (STM_USB_EPR_DTOG_TX_WRITE_INVARIANT << STM_USB_EPR_DTOG_TX) | \
265 (STM_USB_EPR_STAT_TX_WRITE_INVARIANT << STM_USB_EPR_STAT_TX))
267 #define STM_USB_EPR_INVARIANT_MASK ((1 << STM_USB_EPR_CTR_RX) | \
268 (STM_USB_EPR_DTOG_RX_MASK << STM_USB_EPR_DTOG_RX) | \
269 (STM_USB_EPR_STAT_RX_MASK << STM_USB_EPR_STAT_RX) | \
270 (1 << STM_USB_EPR_CTR_TX) | \
271 (STM_USB_EPR_DTOG_TX_MASK << STM_USB_EPR_DTOG_TX) | \
272 (STM_USB_EPR_STAT_TX_MASK << STM_USB_EPR_STAT_TX))
275 * These bits are purely under sw control, so preserve them in the
276 * register by re-writing what was read
278 #define STM_USB_EPR_PRESERVE_MASK ((STM_USB_EPR_EP_TYPE_MASK << STM_USB_EPR_EP_TYPE) | \
279 (1 << STM_USB_EPR_EP_KIND) | \
280 (STM_USB_EPR_EA_MASK << STM_USB_EPR_EA))
286 #define _tx_dbg0(msg) _dbg(__LINE__,msg,0)
287 #define _tx_dbg1(msg,value) _dbg(__LINE__,msg,value)
289 #define _tx_dbg0(msg)
290 #define _tx_dbg1(msg,value)
294 #define _rx_dbg0(msg) _dbg(__LINE__,msg,0)
295 #define _rx_dbg1(msg,value) _dbg(__LINE__,msg,value)
297 #define _rx_dbg0(msg)
298 #define _rx_dbg1(msg,value)
302 static void _dbg(int line, char *msg, uint32_t value);
306 * Set the state of the specified endpoint register to a new
307 * value. This is tricky because the bits toggle where the new
308 * value is one, and we need to write invariant values in other
309 * spots of the register. This hardware is strange...
312 _ao_usb_set_stat_tx(int ep, uint32_t stat_tx)
314 uint16_t epr_write, epr_old;
316 _tx_dbg1("set_stat_tx top", stat_tx);
317 epr_old = epr_write = stm_usb.epr[ep].r;
318 epr_write &= STM_USB_EPR_PRESERVE_MASK;
319 epr_write |= STM_USB_EPR_INVARIANT;
320 epr_write |= (uint16_t) set_toggle(epr_old,
321 STM_USB_EPR_STAT_TX_MASK << STM_USB_EPR_STAT_TX,
322 stat_tx << STM_USB_EPR_STAT_TX);
323 stm_usb.epr[ep].r = epr_write;
324 _tx_dbg1("set_stat_tx bottom", epr_write);
328 ao_usb_set_stat_tx(int ep, uint32_t stat_tx)
330 ao_arch_block_interrupts();
331 _ao_usb_set_stat_tx(ep, stat_tx);
332 ao_arch_release_interrupts();
336 _ao_usb_toggle_dtog(int ep, uint32_t dtog_rx, uint32_t dtog_tx)
340 _tx_dbg1("toggle_dtog top", dtog_rx);
341 epr_write = stm_usb.epr[ep].r;
342 epr_write &= STM_USB_EPR_PRESERVE_MASK;
343 epr_write |= STM_USB_EPR_INVARIANT;
344 epr_write |= (uint16_t) ((dtog_rx << STM_USB_EPR_DTOG_RX) |
345 (dtog_tx << STM_USB_EPR_DTOG_TX));
346 stm_usb.epr[ep].r = epr_write;
347 _tx_dbg1("toggle_dtog bottom", epr_write);
351 _ao_usb_set_stat_rx(int ep, uint32_t stat_rx) {
352 uint16_t epr_write, epr_old;
354 epr_write = epr_old = stm_usb.epr[ep].r;
355 epr_write &= STM_USB_EPR_PRESERVE_MASK;
356 epr_write |= STM_USB_EPR_INVARIANT;
357 epr_write |= (uint16_t) set_toggle(epr_old,
358 STM_USB_EPR_STAT_RX_MASK << STM_USB_EPR_STAT_RX,
359 stat_rx << STM_USB_EPR_STAT_RX);
360 stm_usb.epr[ep].r = epr_write;
364 ao_usb_set_stat_rx(int ep, uint32_t stat_rx) {
365 ao_arch_block_interrupts();
366 _ao_usb_set_stat_rx(ep, stat_rx);
367 ao_arch_release_interrupts();
371 * Initialize an entpoint
375 ao_usb_init_ep(uint8_t ep, uint16_t addr, uint16_t type,
376 uint16_t stat_rx, uint16_t stat_tx,
378 uint16_t dtog_rx, uint16_t dtog_tx)
382 ao_arch_block_interrupts();
383 epr = stm_usb.epr[ep].r;
384 epr = (uint16_t) ((0UL << STM_USB_EPR_CTR_RX) |
385 ((uint32_t) type << STM_USB_EPR_EP_TYPE) |
386 ((uint32_t) kind << STM_USB_EPR_EP_KIND) |
387 (0UL << STM_USB_EPR_CTR_TX) |
388 ((uint32_t) addr << STM_USB_EPR_EA) |
391 (1UL << STM_USB_EPR_DTOG_RX) |
392 (STM_USB_EPR_STAT_RX_MASK << STM_USB_EPR_STAT_RX) |
393 (1UL << STM_USB_EPR_DTOG_TX) |
394 (STM_USB_EPR_STAT_TX_MASK << STM_USB_EPR_STAT_TX),
396 ((uint32_t) dtog_rx << STM_USB_EPR_DTOG_RX) |
397 ((uint32_t) stat_rx << STM_USB_EPR_STAT_RX) |
398 ((uint32_t) dtog_tx << STM_USB_EPR_DTOG_TX) |
399 ((uint32_t) stat_tx << STM_USB_EPR_STAT_TX)));
400 stm_usb.epr[ep].r = epr;
401 ao_arch_release_interrupts();
402 debug ("writing epr[%d] 0x%04x wrote 0x%04x\n",
403 ep, epr, stm_usb.epr[ep].r);
407 ao_usb_alloc_buffers(void)
409 uint16_t sram_addr = 0;
411 /* allocate space for BDT, which is at the start of SRAM */
412 sram_addr += 8 * STM_USB_BDT_SIZE;
414 ao_usb_ep0_tx_offset = sram_addr;
415 sram_addr += AO_USB_CONTROL_SIZE;
417 ao_usb_ep0_rx_offset = sram_addr;
418 sram_addr += AO_USB_CONTROL_SIZE;
421 sram_addr = (uint16_t) ((uint16_t) sram_addr + (uint16_t) (sram_addr & 1));
422 ao_usb_int_tx_offset = sram_addr;
423 sram_addr += AO_USB_INT_SIZE;
427 sram_addr = (uint16_t) ((uint16_t) sram_addr + (uint16_t) (sram_addr & 1));
428 ao_usb_out_rx_offset = sram_addr;
429 sram_addr += AO_USB_OUT_SIZE * 2;
433 sram_addr = (uint16_t) ((uint16_t) sram_addr + (uint16_t) (sram_addr & 1));
434 ao_usb_in_tx_offset = sram_addr;
435 sram_addr += AO_USB_IN_SIZE * 2;
439 sram_addr = (uint16_t) ((uint16_t) sram_addr + (uint16_t) (sram_addr & 1));
440 ao_usb_in_tx2_offset = sram_addr;
441 sram_addr += AO_USB_IN_SIZE * 2;
444 sram_addr = (uint16_t) ((uint16_t) sram_addr + (uint16_t) (sram_addr & 1));
445 ao_usb_in_tx3_offset = sram_addr;
446 sram_addr += AO_USB_IN_SIZE * 2;
451 ao_usb_init_btable(void)
453 /* Set up EP 0 - a Control end point with 32 bytes of in and out buffers */
455 stm_usb_bdt[0].single.addr_tx = ao_usb_ep0_tx_offset;
456 stm_usb_bdt[0].single.count_tx = 0;
458 stm_usb_bdt[0].single.addr_rx = ao_usb_ep0_rx_offset;
459 stm_usb_bdt[0].single.count_rx = ((1 << STM_USB_BDT_COUNT_RX_BL_SIZE) |
460 (((AO_USB_CONTROL_SIZE / 32) - 1) << STM_USB_BDT_COUNT_RX_NUM_BLOCK));
468 ao_usb_init_btable();
470 /* buffer table is at the start of USB memory */
473 ao_usb_init_ep(AO_USB_CONTROL_EPR, AO_USB_CONTROL_EP,
474 STM_USB_EPR_EP_TYPE_CONTROL,
475 STM_USB_EPR_STAT_RX_VALID,
476 STM_USB_EPR_STAT_TX_NAK,
477 STM_USB_EPR_EP_KIND_NO_STATUS_OUT, 0, 0);
479 /* Clear all of the other endpoints */
480 for (e = 1; e < 8; e++) {
482 STM_USB_EPR_EP_TYPE_CONTROL,
483 STM_USB_EPR_STAT_RX_DISABLED,
484 STM_USB_EPR_STAT_TX_DISABLED,
485 STM_USB_EPR_EP_KIND_SNGL_BUF, 0, 0);
488 ao_usb_set_address(0);
492 /* Reset our internal state
495 ao_usb_ep0_state = AO_USB_EP0_IDLE;
497 ao_usb_ep0_in_data = NULL;
498 ao_usb_ep0_in_len = 0;
500 ao_usb_ep0_out_data = 0;
501 ao_usb_ep0_out_len = 0;
505 ao_usb_set_configuration(void)
507 debug ("ao_usb_set_configuration\n");
510 /* Set up the INT end point */
511 stm_usb_bdt[AO_USB_INT_EPR].single.addr_tx = ao_usb_int_tx_offset;
512 stm_usb_bdt[AO_USB_INT_EPR].single.count_tx = 0;
514 ao_usb_init_ep(AO_USB_INT_EPR,
516 STM_USB_EPR_EP_TYPE_INTERRUPT,
517 STM_USB_EPR_STAT_RX_DISABLED,
518 STM_USB_EPR_STAT_TX_NAK,
519 STM_USB_EPR_EP_KIND_SNGL_BUF, 0, 0);
523 /* Set up the OUT end point */
524 stm_usb_bdt[AO_USB_OUT_EPR].double_rx[0].addr = ao_usb_out_rx_offset;
525 stm_usb_bdt[AO_USB_OUT_EPR].double_rx[0].count = ((1 << STM_USB_BDT_COUNT_RX_BL_SIZE) |
526 (((AO_USB_OUT_SIZE / 32) - 1) << STM_USB_BDT_COUNT_RX_NUM_BLOCK));
528 stm_usb_bdt[AO_USB_OUT_EPR].double_rx[1].addr = ao_usb_out_rx_offset + AO_USB_OUT_SIZE;
529 stm_usb_bdt[AO_USB_OUT_EPR].double_rx[1].count = ((1 << STM_USB_BDT_COUNT_RX_BL_SIZE) |
530 (((AO_USB_OUT_SIZE / 32) - 1) << STM_USB_BDT_COUNT_RX_NUM_BLOCK));
532 /* set 'our' buffer to one, and the device buffer to 0 */
533 ao_usb_init_ep(AO_USB_OUT_EPR,
535 STM_USB_EPR_EP_TYPE_BULK,
536 STM_USB_EPR_STAT_RX_VALID,
537 STM_USB_EPR_STAT_TX_DISABLED,
538 STM_USB_EPR_EP_KIND_DBL_BUF, 0, 1);
540 /* At first receive, we'll flip this back to 0 */
541 ao_usb_out_rx_which = 1;
545 /* Set up the IN end point */
546 stm_usb_bdt[AO_USB_IN_EPR].double_tx[0].addr = ao_usb_in_tx_offset;
547 stm_usb_bdt[AO_USB_IN_EPR].double_tx[0].count = 0;
548 stm_usb_bdt[AO_USB_IN_EPR].double_tx[1].addr = ao_usb_in_tx_offset + AO_USB_IN_SIZE;
549 stm_usb_bdt[AO_USB_IN_EPR].double_tx[1].count = 0;
551 /* set 'our' buffer to 0, and the device buffer to 1 */
552 ao_usb_init_ep(AO_USB_IN_EPR,
554 STM_USB_EPR_EP_TYPE_BULK,
555 STM_USB_EPR_STAT_RX_DISABLED,
556 STM_USB_EPR_STAT_TX_NAK,
557 STM_USB_EPR_EP_KIND_DBL_BUF,
560 /* First transmit data goes to buffer 0 */
561 ao_usb_in_tx_which = 0;
565 /* Set up the IN2 end point */
566 stm_usb_bdt[AO_USB_IN2_EPR].double_tx[0].addr = ao_usb_in_tx2_offset;
567 stm_usb_bdt[AO_USB_IN2_EPR].double_tx[0].count = 0;
568 stm_usb_bdt[AO_USB_IN2_EPR].double_tx[1].addr = ao_usb_in_tx2_offset + AO_USB_IN_SIZE;
569 stm_usb_bdt[AO_USB_IN2_EPR].double_tx[1].count = 0;
571 ao_usb_init_ep(AO_USB_IN2_EPR,
573 STM_USB_EPR_EP_TYPE_BULK,
574 STM_USB_EPR_STAT_RX_DISABLED,
575 STM_USB_EPR_STAT_TX_NAK,
576 STM_USB_EPR_EP_KIND_DBL_BUF,
579 /* First transmit data goes to buffer 0 */
580 ao_usb_in_tx2_which = 0;
584 /* Set up the IN3 end point */
585 stm_usb_bdt[AO_USB_IN3_EPR].double_tx[0].addr = ao_usb_in_tx3_offset;
586 stm_usb_bdt[AO_USB_IN3_EPR].double_tx[0].count = 0;
587 stm_usb_bdt[AO_USB_IN3_EPR].double_tx[1].addr = ao_usb_in_tx3_offset + AO_USB_IN_SIZE;
588 stm_usb_bdt[AO_USB_IN3_EPR].double_tx[1].count = 0;
590 ao_usb_init_ep(AO_USB_IN3_EPR,
592 STM_USB_EPR_EP_TYPE_BULK,
593 STM_USB_EPR_STAT_RX_DISABLED,
594 STM_USB_EPR_STAT_TX_NAK,
595 STM_USB_EPR_EP_KIND_DBL_BUF,
598 /* First transmit data goes to buffer 0 */
599 ao_usb_in_tx3_which = 0;
602 ao_usb_in_flushed = 0;
603 ao_usb_in_pending = 0;
604 ao_wakeup(&ao_usb_in_pending);
606 ao_usb_in2_flushed = 0;
607 ao_usb_in2_pending = 0;
608 ao_wakeup(&ao_usb_in2_pending);
612 ao_usb_in3_flushed = 0;
613 ao_usb_in3_pending = 0;
614 ao_wakeup(&ao_usb_in3_pending);
617 ao_usb_out_avail = 0;
618 ao_usb_configuration = 0;
620 ao_wakeup(AO_USB_OUT_SLEEP_ADDR);
624 ao_wakeup(&ao_usb_running);
629 static uint16_t control_count;
630 static uint16_t int_count;
631 static uint16_t in_count;
632 static uint16_t out_count;
633 static uint16_t reset_count;
636 /* The USB memory must be accessed in 16-bit units
640 ao_usb_tx_byte(uint16_t offset, uint8_t byte)
643 ao_usb_packet_put(offset - 1,
644 (uint16_t) (ao_usb_packet_get(offset - 1) | ((uint16_t) byte) << 8));
646 ao_usb_packet_put(offset, (uint16_t) byte);
650 ao_usb_rx_byte(uint16_t offset)
653 return (uint8_t) ((ao_usb_packet_get(offset - 1)) >> 8);
655 return (uint8_t) ao_usb_packet_get(offset);
659 ao_usb_copy_tx(const uint8_t *src, uint16_t offset, uint16_t bytes)
662 ao_usb_tx_byte(offset++, *src++);
666 ao_usb_copy_rx(uint8_t *dst, uint16_t offset, uint16_t bytes)
669 *dst++ = ao_usb_rx_byte(offset++);
672 /* Send an IN data packet */
674 ao_usb_ep0_flush(void)
678 /* Check to see if the endpoint is still busy */
679 if (ao_usb_epr_stat_tx(stm_usb.epr[0].r) == STM_USB_EPR_STAT_TX_VALID) {
680 debug("EP0 not accepting IN data\n");
684 this_len = ao_usb_ep0_in_len;
685 if (this_len > AO_USB_CONTROL_SIZE)
686 this_len = AO_USB_CONTROL_SIZE;
688 if (this_len < AO_USB_CONTROL_SIZE)
689 ao_usb_ep0_state = AO_USB_EP0_IDLE;
691 ao_usb_ep0_in_len -= this_len;
693 debug_data ("Flush EP0 len %d:", this_len);
694 ao_usb_copy_tx(ao_usb_ep0_in_data, ao_usb_ep0_tx_offset, this_len);
696 ao_usb_ep0_in_data += this_len;
698 /* Mark the endpoint as TX valid to send the packet */
699 stm_usb_bdt[AO_USB_CONTROL_EPR].single.count_tx = this_len;
700 ao_usb_set_stat_tx(AO_USB_CONTROL_EPR, STM_USB_EPR_STAT_TX_VALID);
701 debug ("queue tx. epr 0 now %08x\n", stm_usb.epr[AO_USB_CONTROL_EPR]);
704 /* Read data from the ep0 OUT fifo */
706 ao_usb_ep0_fill(void)
708 uint16_t len = stm_usb_bdt[0].single.count_rx & STM_USB_BDT_COUNT_RX_COUNT_RX_MASK;
710 if (len > ao_usb_ep0_out_len)
711 len = ao_usb_ep0_out_len;
712 ao_usb_ep0_out_len -= (uint8_t) len;
714 /* Pull all of the data out of the packet */
715 debug_data ("Fill EP0 len %d:", len);
716 ao_usb_copy_rx(ao_usb_ep0_out_data, ao_usb_ep0_rx_offset, len);
718 ao_usb_ep0_out_data += len;
721 ao_usb_set_stat_rx(0, STM_USB_EPR_STAT_RX_VALID);
725 ao_usb_ep0_in_reset(void)
727 ao_usb_ep0_in_data = ao_usb_ep0_in_buf;
728 ao_usb_ep0_in_len = 0;
732 ao_usb_ep0_in_queue_byte(uint8_t a)
734 if (ao_usb_ep0_in_len < sizeof (ao_usb_ep0_in_buf))
735 ao_usb_ep0_in_buf[ao_usb_ep0_in_len++] = a;
739 ao_usb_ep0_in_set(const uint8_t *data, uint8_t len)
741 ao_usb_ep0_in_data = data;
742 ao_usb_ep0_in_len = len;
746 ao_usb_ep0_out_set(uint8_t *data, uint8_t len)
748 ao_usb_ep0_out_data = data;
749 ao_usb_ep0_out_len = len;
753 ao_usb_ep0_in_start(uint16_t max)
755 /* Don't send more than asked for */
756 if (ao_usb_ep0_in_len > max)
757 ao_usb_ep0_in_len = (uint8_t) max;
761 struct ao_usb_line_coding ao_usb_line_coding = {115200, 0, 0, 8};
763 #if AO_USB_DEVICE_ID_SERIAL
764 static uint8_t ao_usb_serial[2 + 48];
766 /* Convert a 32-bit value to 8 hexidecimal UCS2 characters */
768 hex_to_ucs2(uint32_t in, uint8_t *out)
772 for (i = 28; i >= 0; i -= 4) {
773 uint8_t bits = (in >> i) & 0xf;
774 *out++ = (uint8_t) (((bits < 10) ? '0' : ('a' - 10)) + bits);
779 /* Encode the device ID (96 bits) in hexidecimal to use as a device
783 ao_usb_serial_init(void)
785 ao_usb_serial[0] = 50; /* length */
786 ao_usb_serial[1] = AO_USB_DESC_STRING;
787 hex_to_ucs2(stm_device_id.u_id0, ao_usb_serial + 2 + 0);
788 hex_to_ucs2(stm_device_id.u_id1, ao_usb_serial + 2 + 16);
789 hex_to_ucs2(stm_device_id.u_id2, ao_usb_serial + 2 + 32);
793 /* Walk through the list of descriptors and find a match
796 ao_usb_get_descriptor(uint16_t value, uint16_t length)
798 const uint8_t *descriptor;
799 uint8_t type = (uint8_t) (value >> 8);
800 uint8_t index = (uint8_t) value;
802 descriptor = ao_usb_descriptors;
803 while (descriptor[0] != 0) {
804 if (descriptor[1] == type && index-- == 0) {
806 if (type == AO_USB_DESC_CONFIGURATION)
810 #if AO_USB_DEVICE_ID_SERIAL
811 /* Slightly hacky - the serial number is string 3 */
812 if (type == AO_USB_DESC_STRING && (value & 0xff) == 3) {
813 descriptor = ao_usb_serial;
814 len = sizeof (ao_usb_serial);
818 len = (uint8_t) length;
819 ao_usb_ep0_in_set(descriptor, len);
822 descriptor += descriptor[0];
827 ao_usb_ep0_setup(void)
829 /* Pull the setup packet out of the fifo */
830 ao_usb_ep0_out_set((uint8_t *) &ao_usb_setup, 8);
832 if (ao_usb_ep0_out_len != 0) {
833 debug ("invalid setup packet length\n");
837 if ((ao_usb_setup.dir_type_recip & AO_USB_DIR_IN) || ao_usb_setup.length == 0)
838 ao_usb_ep0_state = AO_USB_EP0_DATA_IN;
840 ao_usb_ep0_state = AO_USB_EP0_DATA_OUT;
842 ao_usb_ep0_in_reset();
844 switch(ao_usb_setup.dir_type_recip & AO_USB_SETUP_TYPE_MASK) {
845 case AO_USB_TYPE_STANDARD:
846 debug ("Standard setup packet\n");
847 switch(ao_usb_setup.dir_type_recip & AO_USB_SETUP_RECIP_MASK) {
848 case AO_USB_RECIP_DEVICE:
849 debug ("Device setup packet\n");
850 switch(ao_usb_setup.request) {
851 case AO_USB_REQ_GET_STATUS:
852 debug ("get status\n");
853 ao_usb_ep0_in_queue_byte(0);
854 ao_usb_ep0_in_queue_byte(0);
856 case AO_USB_REQ_SET_ADDRESS:
857 debug ("set address %d\n", ao_usb_setup.value);
858 ao_usb_address = (uint8_t) ao_usb_setup.value;
859 ao_usb_address_pending = 1;
861 case AO_USB_REQ_GET_DESCRIPTOR:
862 debug ("get descriptor %d\n", ao_usb_setup.value);
863 ao_usb_get_descriptor(ao_usb_setup.value, ao_usb_setup.length);
865 case AO_USB_REQ_GET_CONFIGURATION:
866 debug ("get configuration %d\n", ao_usb_configuration);
867 ao_usb_ep0_in_queue_byte(ao_usb_configuration);
869 case AO_USB_REQ_SET_CONFIGURATION:
870 ao_usb_configuration = (uint8_t) ao_usb_setup.value;
871 debug ("set configuration %d\n", ao_usb_configuration);
872 ao_usb_set_configuration();
876 case AO_USB_RECIP_INTERFACE:
877 debug ("Interface setup packet\n");
878 switch(ao_usb_setup.request) {
879 case AO_USB_REQ_GET_STATUS:
880 ao_usb_ep0_in_queue_byte(0);
881 ao_usb_ep0_in_queue_byte(0);
883 case AO_USB_REQ_GET_INTERFACE:
884 ao_usb_ep0_in_queue_byte(0);
886 case AO_USB_REQ_SET_INTERFACE:
890 case AO_USB_RECIP_ENDPOINT:
891 debug ("Endpoint setup packet\n");
892 switch(ao_usb_setup.request) {
893 case AO_USB_REQ_GET_STATUS:
894 ao_usb_ep0_in_queue_byte(0);
895 ao_usb_ep0_in_queue_byte(0);
901 case AO_USB_TYPE_CLASS:
902 debug ("Class setup packet\n");
903 switch (ao_usb_setup.request) {
904 case AO_USB_SET_LINE_CODING:
905 debug ("set line coding\n");
906 ao_usb_ep0_out_set((uint8_t *) &ao_usb_line_coding, 7);
908 case AO_USB_GET_LINE_CODING:
909 debug ("get line coding\n");
910 ao_usb_ep0_in_set((const uint8_t *) &ao_usb_line_coding, 7);
912 case AO_USB_SET_CONTROL_LINE_STATE:
918 /* If we're not waiting to receive data from the host,
919 * queue an IN response
921 if (ao_usb_ep0_state == AO_USB_EP0_DATA_IN)
922 ao_usb_ep0_in_start(ao_usb_setup.length);
926 ao_usb_ep0_handle(uint8_t receive)
928 ao_usb_ep0_receive = 0;
929 if (receive & AO_USB_EP0_GOT_SETUP) {
933 if (receive & AO_USB_EP0_GOT_RX_DATA) {
934 debug ("\tgot rx data\n");
935 if (ao_usb_ep0_state == AO_USB_EP0_DATA_OUT) {
937 if (ao_usb_ep0_out_len == 0) {
938 ao_usb_ep0_state = AO_USB_EP0_DATA_IN;
939 ao_usb_ep0_in_start(0);
943 if (receive & AO_USB_EP0_GOT_TX_ACK) {
944 debug ("\tgot tx ack\n");
946 #if HAS_FLIGHT && AO_USB_FORCE_IDLE
947 ao_flight_force_idle = 1;
949 /* Wait until the IN packet is received from addr 0
950 * before assigning our local address
952 if (ao_usb_address_pending)
953 ao_usb_set_address(ao_usb_address);
954 if (ao_usb_ep0_state == AO_USB_EP0_DATA_IN)
959 #if AO_POWER_MANAGEMENT
963 stm_usb.cntr |= (1 << STM_USB_CNTR_FSUSP);
965 stm_usb.cntr |= (1 << STM_USB_CNTR_LP_MODE);
973 stm_usb.cntr &= (uint16_t) ~(1 << STM_USB_CNTR_FSUSP);
981 uint32_t istr = stm_usb.istr;
983 stm_usb.istr = (uint16_t) ~istr;
984 if (istr & (1 << STM_USB_ISTR_CTR)) {
985 uint8_t ep = istr & STM_USB_ISTR_EP_ID_MASK;
986 uint16_t epr, epr_write;
988 /* Preserve the SW write bits, don't mess with most HW writable bits,
989 * clear the CTR_RX and CTR_TX bits
991 epr = stm_usb.epr[ep].r;
993 epr_write &= STM_USB_EPR_PRESERVE_MASK;
994 epr_write |= STM_USB_EPR_INVARIANT;
995 epr_write &= (uint16_t) ~(1 << STM_USB_EPR_CTR_RX);
996 epr_write &= (uint16_t) ~(1 << STM_USB_EPR_CTR_TX);
997 stm_usb.epr[ep].r = epr_write;
1004 if (ao_usb_epr_ctr_rx(epr)) {
1005 if (ao_usb_epr_setup(epr))
1006 ao_usb_ep0_receive |= AO_USB_EP0_GOT_SETUP;
1008 ao_usb_ep0_receive |= AO_USB_EP0_GOT_RX_DATA;
1010 if (ao_usb_epr_ctr_tx(epr))
1011 ao_usb_ep0_receive |= AO_USB_EP0_GOT_TX_ACK;
1012 ao_usb_ep0_handle(ao_usb_ep0_receive);
1014 case AO_USB_OUT_EPR:
1018 if (ao_usb_epr_ctr_rx(epr)) {
1019 _rx_dbg1("RX ISR", epr);
1020 ao_usb_out_avail = 1;
1021 _rx_dbg0("out avail set");
1022 ao_wakeup(AO_USB_OUT_SLEEP_ADDR);
1023 _rx_dbg0("stdin awoken");
1030 _tx_dbg1("TX ISR", epr);
1031 if (ao_usb_epr_ctr_tx(epr)) {
1032 ao_usb_in_pending = 0;
1033 ao_wakeup(&ao_usb_in_pending);
1037 case AO_USB_IN2_EPR:
1039 _tx_dbg1("TX2 ISR", epr);
1040 if (ao_usb_epr_ctr_tx(epr)) {
1041 ao_usb_in2_pending = 0;
1042 ao_wakeup(&ao_usb_in2_pending);
1047 case AO_USB_IN3_EPR:
1049 _tx_dbg1("TX3 ISR", epr);
1050 if (ao_usb_epr_ctr_tx(epr)) {
1051 ao_usb_in3_pending = 0;
1052 ao_wakeup(&ao_usb_in3_pending);
1056 case AO_USB_INT_EPR:
1060 if (ao_usb_epr_ctr_tx(epr))
1061 _ao_usb_set_stat_tx(AO_USB_INT_EPR, STM_USB_EPR_STAT_TX_NAK);
1067 if (istr & (1 << STM_USB_ISTR_RESET)) {
1071 debug ("\treset\n");
1074 #if AO_POWER_MANAGEMENT
1075 if (istr & (1 << STM_USB_ISTR_SUSP)) {
1076 debug ("\tsuspend\n");
1079 if (istr & (1 << STM_USB_ISTR_WKUP)) {
1080 debug ("\twakeup\n");
1087 /* Queue the current IN buffer for transmission */
1089 _ao_usb_in_send(void)
1091 _tx_dbg0("in_send start");
1092 debug ("send %d\n", ao_usb_tx_count);
1093 while (ao_usb_in_pending)
1094 ao_sleep(&ao_usb_in_pending);
1095 ao_usb_in_pending = 1;
1096 if (ao_usb_tx_count != AO_USB_IN_SIZE)
1097 ao_usb_in_flushed = 1;
1098 stm_usb_bdt[AO_USB_IN_EPR].double_tx[ao_usb_in_tx_which].count = ao_usb_tx_count;
1099 ao_usb_tx_count = 0;
1101 /* Toggle our usage */
1102 ao_usb_in_tx_which = 1 - ao_usb_in_tx_which;
1104 /* Toggle the SW_BUF flag */
1105 _ao_usb_toggle_dtog(AO_USB_IN_EPR, 1, 0);
1107 /* Mark the outgoing buffer as valid */
1108 _ao_usb_set_stat_tx(AO_USB_IN_EPR, STM_USB_EPR_STAT_TX_VALID);
1110 _tx_dbg0("in_send end");
1113 /* Wait for a free IN buffer. Interrupts are blocked */
1115 _ao_usb_in_wait(void)
1118 /* Check if the current buffer is writable */
1119 if (ao_usb_tx_count < AO_USB_IN_SIZE)
1122 _tx_dbg0("in_wait top");
1123 /* Wait for an IN buffer to be ready */
1124 while (ao_usb_in_pending)
1125 ao_sleep(&ao_usb_in_pending);
1126 _tx_dbg0("in_wait bottom");
1133 if (!ao_usb_running)
1136 /* Anytime we've sent a character since
1137 * the last time we flushed, we'll need
1138 * to send a packet -- the only other time
1139 * we would send a packet is when that
1140 * packet was full, in which case we now
1141 * want to send an empty packet
1143 ao_arch_block_interrupts();
1144 while (!ao_usb_in_flushed) {
1145 _tx_dbg0("flush top");
1147 _tx_dbg0("flush end");
1149 ao_arch_release_interrupts();
1153 ao_usb_putchar(char c)
1155 if (!ao_usb_running)
1158 ao_arch_block_interrupts();
1161 ao_usb_in_flushed = 0;
1162 ao_usb_tx_byte((uint16_t) (ao_usb_in_tx_offset + AO_USB_IN_SIZE * ao_usb_in_tx_which + ao_usb_tx_count++), c);
1164 /* Send the packet when full */
1165 if (ao_usb_tx_count == AO_USB_IN_SIZE) {
1166 _tx_dbg0("putchar full");
1168 _tx_dbg0("putchar flushed");
1170 ao_arch_release_interrupts();
1175 /* Queue the current IN buffer for transmission */
1177 _ao_usb_in2_send(void)
1179 _tx_dbg0("in2_send start");
1180 debug ("send2 %d\n", ao_usb_tx_count);
1181 while (ao_usb_in2_pending)
1182 ao_sleep(&ao_usb_in2_pending);
1183 ao_usb_in2_pending = 1;
1184 if (ao_usb_tx2_count != AO_USB_IN_SIZE)
1185 ao_usb_in2_flushed = 1;
1186 stm_usb_bdt[AO_USB_IN2_EPR].double_tx[ao_usb_in_tx2_which].count = ao_usb_tx2_count;
1187 ao_usb_tx2_count = 0;
1189 /* Toggle our usage */
1190 ao_usb_in_tx2_which = 1 - ao_usb_in_tx2_which;
1192 /* Toggle the SW_BUF flag */
1193 _ao_usb_toggle_dtog(AO_USB_IN2_EPR, 1, 0);
1195 /* Mark the outgoing buffer as valid */
1196 _ao_usb_set_stat_tx(AO_USB_IN2_EPR, STM_USB_EPR_STAT_TX_VALID);
1198 _tx_dbg0("in2_send end");
1201 /* Wait for a free IN buffer. Interrupts are blocked */
1203 _ao_usb_in2_wait(void)
1206 /* Check if the current buffer is writable */
1207 if (ao_usb_tx2_count < AO_USB_IN_SIZE)
1210 _tx_dbg0("in2_wait top");
1211 /* Wait for an IN buffer to be ready */
1212 while (ao_usb_in2_pending)
1213 ao_sleep(&ao_usb_in2_pending);
1214 _tx_dbg0("in_wait bottom");
1221 if (!ao_usb_running)
1224 /* Anytime we've sent a character since
1225 * the last time we flushed, we'll need
1226 * to send a packet -- the only other time
1227 * we would send a packet is when that
1228 * packet was full, in which case we now
1229 * want to send an empty packet
1231 ao_arch_block_interrupts();
1232 while (!ao_usb_in2_flushed) {
1233 _tx_dbg0("flush2 top");
1235 _tx_dbg0("flush2 end");
1237 ao_arch_release_interrupts();
1241 ao_usb_putchar2(char c)
1243 if (!ao_usb_running)
1246 ao_arch_block_interrupts();
1249 ao_usb_in2_flushed = 0;
1250 ao_usb_tx_byte((uint16_t) (ao_usb_in_tx2_offset + AO_USB_IN_SIZE * ao_usb_in_tx2_which + ao_usb_tx2_count++), c);
1252 /* Send the packet when full */
1253 if (ao_usb_tx2_count == AO_USB_IN_SIZE) {
1254 _tx_dbg0("putchar2 full");
1256 _tx_dbg0("putchar2 flushed");
1258 ao_arch_release_interrupts();
1263 /* Queue the current IN buffer for transmission */
1265 _ao_usb_in3_send(void)
1267 _tx_dbg0("in3_send start");
1268 debug ("send3 %d\n", ao_usb_tx3_count);
1269 while (ao_usb_in3_pending)
1270 ao_sleep(&ao_usb_in3_pending);
1271 ao_usb_in3_pending = 1;
1272 if (ao_usb_tx3_count != AO_USB_IN_SIZE)
1273 ao_usb_in3_flushed = 1;
1274 stm_usb_bdt[AO_USB_IN3_EPR].double_tx[ao_usb_in_tx3_which].count = ao_usb_tx3_count;
1275 ao_usb_tx3_count = 0;
1277 /* Toggle our usage */
1278 ao_usb_in_tx3_which = 1 - ao_usb_in_tx3_which;
1280 /* Toggle the SW_BUF flag */
1281 _ao_usb_toggle_dtog(AO_USB_IN3_EPR, 1, 0);
1283 /* Mark the outgoing buffer as valid */
1284 _ao_usb_set_stat_tx(AO_USB_IN3_EPR, STM_USB_EPR_STAT_TX_VALID);
1286 _tx_dbg0("in3_send end");
1289 /* Wait for a free IN buffer. Interrupts are blocked */
1291 _ao_usb_in3_wait(void)
1294 /* Check if the current buffer is writable */
1295 if (ao_usb_tx3_count < AO_USB_IN_SIZE)
1298 _tx_dbg0("in3_wait top");
1299 /* Wait for an IN buffer to be ready */
1300 while (ao_usb_in3_pending)
1301 ao_sleep(&ao_usb_in3_pending);
1302 _tx_dbg0("in_wait bottom");
1309 if (!ao_usb_running)
1312 /* Anytime we've sent a character since
1313 * the last time we flushed, we'll need
1314 * to send a packet -- the only other time
1315 * we would send a packet is when that
1316 * packet was full, in which case we now
1317 * want to send an empty packet
1319 ao_arch_block_interrupts();
1320 while (!ao_usb_in3_flushed) {
1321 _tx_dbg0("flush3 top");
1323 _tx_dbg0("flush3 end");
1325 ao_arch_release_interrupts();
1329 ao_usb_putchar3(char c)
1331 if (!ao_usb_running)
1334 ao_arch_block_interrupts();
1337 ao_usb_in3_flushed = 0;
1338 ao_usb_tx_byte((uint16_t) (ao_usb_in_tx3_offset + AO_USB_IN_SIZE * ao_usb_in_tx3_which + ao_usb_tx3_count++), c);
1340 /* Send the packet when full */
1341 if (ao_usb_tx3_count == AO_USB_IN_SIZE) {
1342 _tx_dbg0("putchar3 full");
1344 _tx_dbg0("putchar3 flushed");
1346 ao_arch_release_interrupts();
1352 _ao_usb_out_recv(void)
1354 _rx_dbg1("out_recv top", stm_usb.epr[AO_USB_OUT_EPR].r);
1356 /* Clear packet available field until we get another interrupt */
1357 ao_usb_out_avail = 0;
1359 /* Switch to new buffer */
1360 ao_usb_out_rx_which = 1 - ao_usb_out_rx_which;
1362 ao_usb_rx_count = (uint8_t) (stm_usb_bdt[AO_USB_OUT_EPR].double_rx[ao_usb_out_rx_which].count & STM_USB_BDT_COUNT_RX_COUNT_RX_MASK);
1365 /* Toggle the SW_BUF_RX bit */
1366 _ao_usb_toggle_dtog(AO_USB_OUT_EPR, 0, 1);
1368 // /* Ack the packet */
1369 // _ao_usb_set_stat_rx(AO_USB_OUT_EPR, STM_USB_EPR_STAT_RX_VALID);
1371 _rx_dbg1("out_recv count", ao_usb_rx_count);
1375 _ao_usb_pollchar(void)
1379 if (!ao_usb_running)
1380 return AO_READ_AGAIN;
1383 if (ao_usb_rx_pos != ao_usb_rx_count)
1386 // _rx_dbg0("poll check");
1387 /* Check to see if a packet has arrived */
1388 if (!ao_usb_out_avail) {
1389 // _rx_dbg0("poll none");
1390 return AO_READ_AGAIN;
1395 /* Pull a character out of the fifo */
1396 c = ao_usb_rx_byte((uint16_t) (ao_usb_out_rx_offset + ao_usb_out_rx_which * AO_USB_OUT_SIZE + ao_usb_rx_pos++));
1397 _rx_dbg1("char", c);
1402 ao_usb_getchar(void)
1406 ao_arch_block_interrupts();
1407 while ((c = _ao_usb_pollchar()) == AO_READ_AGAIN)
1408 ao_sleep(AO_USB_OUT_SLEEP_ADDR);
1409 ao_arch_release_interrupts();
1418 ao_usb_alloc(uint16_t *buffers[2])
1420 buffers[0] = ao_usb_packet_buffer_addr(ao_usb_in_tx_offset);
1421 buffers[1] = ao_usb_packet_buffer_addr(ao_usb_in_tx_offset + AO_USB_IN_SIZE);
1422 return ao_usb_in_tx_which;
1426 ao_usb_write(uint16_t len)
1428 ao_arch_block_interrupts();
1430 /* Wait for everything to be ready at the same time */
1432 /* Make sure USB is connected */
1433 if (!ao_usb_running) {
1434 ao_sleep(&ao_usb_running);
1438 /* Wait for an idle IN buffer */
1439 if (ao_usb_in_pending) {
1440 ao_sleep(&ao_usb_in_pending);
1446 ao_usb_in_pending = 1;
1447 ao_usb_in_flushed = (len != AO_USB_IN_SIZE);
1449 stm_usb_bdt[AO_USB_IN_EPR].double_tx[ao_usb_in_tx_which].count = len;
1451 /* Toggle our usage */
1452 ao_usb_in_tx_which = 1 - ao_usb_in_tx_which;
1454 /* Toggle the SW_BUF flag */
1455 _ao_usb_toggle_dtog(AO_USB_IN_EPR, 1, 0);
1457 /* Mark the outgoing buffer as valid */
1458 _ao_usb_set_stat_tx(AO_USB_IN_EPR, STM_USB_EPR_STAT_TX_VALID);
1460 ao_arch_release_interrupts();
1461 return ao_usb_in_tx_which;
1468 ao_usb_alloc2(uint16_t *buffers[2])
1470 buffers[0] = ao_usb_packet_buffer_addr(ao_usb_in_tx2_offset);
1471 buffers[1] = ao_usb_packet_buffer_addr(ao_usb_in_tx2_offset + AO_USB_IN_SIZE);
1472 return ao_usb_in_tx2_which;
1476 ao_usb_write2(uint16_t len)
1478 ao_arch_block_interrupts();
1480 /* Wait for everything to be ready at the same time */
1482 /* Make sure USB is connected */
1483 if (!ao_usb_running) {
1484 ao_sleep(&ao_usb_running);
1488 /* Wait for an idle IN buffer */
1489 if (ao_usb_in2_pending) {
1490 ao_sleep(&ao_usb_in2_pending);
1496 ao_usb_in2_pending = 1;
1497 ao_usb_in2_flushed = (len != AO_USB_IN_SIZE);
1499 stm_usb_bdt[AO_USB_IN2_EPR].double_tx[ao_usb_in_tx2_which].count = len;
1501 /* Toggle our usage */
1502 ao_usb_in_tx2_which = 1 - ao_usb_in_tx2_which;
1504 /* Toggle the SW_BUF flag */
1505 _ao_usb_toggle_dtog(AO_USB_IN2_EPR, 1, 0);
1507 /* Mark the outgoing buffer as valid */
1508 _ao_usb_set_stat_tx(AO_USB_IN2_EPR, STM_USB_EPR_STAT_TX_VALID);
1509 ao_arch_release_interrupts();
1511 return ao_usb_in_tx2_which;
1517 ao_usb_disable(void)
1519 ao_arch_block_interrupts();
1520 stm_usb.cntr = (1 << STM_USB_CNTR_FRES);
1523 /* Disable USB pull-up */
1524 stm_usb.bcdr &= (uint16_t) ~(1 << STM_USB_BCDR_DPPU);
1526 /* Switch off the device */
1527 stm_usb.cntr = (1 << STM_USB_CNTR_PDWN) | (1 << STM_USB_CNTR_FRES);
1529 /* Disable the interface */
1530 stm_rcc.apb1enr &= ~(1UL << STM_RCC_APB1ENR_USBEN);
1531 ao_arch_release_interrupts();
1539 /* Select HSI48 as USB clock source */
1540 stm_rcc.cfgr3 &= ~(1UL << STM_RCC_CFGR3_USBSW);
1542 /* Enable USB device */
1543 stm_rcc.apb1enr |= (1 << STM_RCC_APB1ENR_USBEN);
1545 /* Clear reset condition */
1546 stm_rcc.apb1rstr &= ~(1UL << STM_RCC_APB1RSTR_USBRST);
1548 /* Disable USB pull-up */
1549 stm_usb.bcdr &= (uint16_t) ~(1 << STM_USB_BCDR_DPPU);
1551 /* Do not touch the GPIOA configuration; USB takes priority
1552 * over GPIO on pins A11 and A12, but if you select alternate
1553 * input 10 (the documented correct selection), then USB is
1554 * pulled low and doesn't work at all
1557 ao_arch_block_interrupts();
1559 /* Route interrupts */
1560 stm_nvic_set_enable(STM_ISR_USB_POS);
1561 stm_nvic_set_priority(STM_ISR_USB_POS, 3);
1563 ao_usb_configuration = 0;
1565 /* Set up buffer descriptors */
1566 ao_usb_init_btable();
1568 /* Reset the USB controller */
1569 stm_usb.cntr = (1 << STM_USB_CNTR_FRES);
1571 /* Clear the reset bit */
1574 /* Clear any spurious interrupts */
1579 debug ("ao_usb_enable\n");
1581 /* Enable interrupts */
1582 stm_usb.cntr = ((1 << STM_USB_CNTR_CTRM) |
1583 (0 << STM_USB_CNTR_PMAOVRM) |
1584 (0 << STM_USB_CNTR_ERRM) |
1585 (AO_POWER_MANAGEMENT << STM_USB_CNTR_WKUPM) |
1586 (AO_POWER_MANAGEMENT << STM_USB_CNTR_SUSPM) |
1587 (1 << STM_USB_CNTR_RESETM) |
1588 (0 << STM_USB_CNTR_SOFM) |
1589 (0 << STM_USB_CNTR_ESOFM) |
1590 (0 << STM_USB_CNTR_RESUME) |
1591 (0 << STM_USB_CNTR_FSUSP) |
1592 (0 << STM_USB_CNTR_LP_MODE) |
1593 (0 << STM_USB_CNTR_PDWN) |
1594 (0 << STM_USB_CNTR_FRES));
1596 ao_arch_release_interrupts();
1598 for (t = 0; t < 50000; t++)
1601 /* Enable USB pull-up */
1602 stm_usb.bcdr |= (1 << STM_USB_BCDR_DPPU);
1606 struct ao_task ao_usb_echo_task;
1614 c = ao_usb_getchar();
1625 printf ("control: %d out: %d in: %d int: %d reset: %d\n",
1626 control_count, out_count, in_count, int_count, reset_count);
1629 const struct ao_cmds ao_usb_cmds[] = {
1630 { ao_usb_irq, "I\0Show USB interrupt counts" },
1638 /* Turn on syscfg */
1639 stm_rcc.apb2enr |= (1 << STM_RCC_APB2ENR_SYSCFGCOMPEN);
1641 /* Set PA11/PA12 remapping bit */
1642 stm_syscfg.cfgr1 |= (AO_PA11_PA12_RMP << STM_SYSCFG_CFGR1_PA11_PA12_RMP);
1644 #ifndef AO_USB_START_DISABLED
1648 #if AO_USB_DEVICE_ID_SERIAL
1649 ao_usb_serial_init();
1652 debug ("ao_usb_init\n");
1653 ao_usb_ep0_state = AO_USB_EP0_IDLE;
1655 ao_usb_alloc_buffers();
1658 ao_add_task(&ao_usb_echo_task, ao_usb_echo, "usb echo");
1661 ao_cmd_register(&ao_usb_cmds[0]);
1665 ao_add_stdio(_ao_usb_pollchar, ao_usb_putchar, ao_usb_flush);
1670 #if TX_DBG || RX_DBG
1680 uint32_t in_pending;
1682 uint32_t in_flushed;
1692 #define NUM_USB_DBG 16
1694 struct ao_usb_dbg dbg[NUM_USB_DBG];
1697 static void _dbg(int line, char *msg, uint32_t value)
1700 dbg[dbg_i].line = line;
1701 dbg[dbg_i].msg = msg;
1702 dbg[dbg_i].value = value;
1703 asm("mrs %0,primask" : "=&r" (primask));
1704 dbg[dbg_i].primask = primask;
1706 dbg[dbg_i].in_count = in3_count;
1707 dbg[dbg_i].in_epr = stm_usb.epr[AO_USB_IN3_EPR].r;
1708 dbg[dbg_i].in_pending = ao_usb_in3_pending;
1709 dbg[dbg_i].tx_count = ao_usb_tx3_count;
1710 dbg[dbg_i].in_flushed = ao_usb_in3_flushed;
1713 dbg[dbg_i].rx_count = ao_usb_rx_count;
1714 dbg[dbg_i].rx_pos = ao_usb_rx_pos;
1715 dbg[dbg_i].out_avail = ao_usb_out_avail;
1716 dbg[dbg_i].out_epr = stm_usb.epr[AO_USB_OUT_EPR].r;
1718 if (++dbg_i == NUM_USB_DBG)