2 * Copyright © 2012 Keith Packard <keithp@keithp.com>
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; version 2 of the License.
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
11 * General Public License for more details.
13 * You should have received a copy of the GNU General Public License along
14 * with this program; if not, write to the Free Software Foundation, Inc.,
15 * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
20 #ifndef BEEPER_CHANNEL
21 #error BEEPER_CHANNEL undefined
30 stm_rcc.apb2enr &= ~(1 << STM_RCC_APB2ENR_TIM1EN);
32 stm_rcc.apb2enr |= (1 << STM_RCC_APB2ENR_TIM1EN);
34 /* Master output enable */
35 stm_tim1.bdtr = (1 << STM_TIM1_BDTR_MOE);
37 stm_tim1.cr2 = ((0 << STM_TIM1_CR2_TI1S) |
38 (STM_TIM1_CR2_MMS_RESET << STM_TIM1_CR2_MMS) |
39 (0 << STM_TIM1_CR2_CCDS));
41 /* Set prescaler to match cc1111 clocks
43 stm_tim1.psc = AO_TIM_CLK / 750000;
45 /* 1. Select the counter clock (internal, external, prescaler).
47 * Setting SMCR to zero means use the internal clock
52 /* 2. Write the desired data in the TIMx_ARR and TIMx_CCRx registers. */
56 /* 3. Set the CCxIE and/or CCxDE bits if an interrupt and/or a
57 * DMA request is to be generated.
61 /* 4. Select the output mode. For example, you must write
62 * OCxM=011, OCxPE=0, CCxP=0 and CCxE=1 to toggle OCx output
63 * pin when CNT matches CCRx, CCRx preload is not used, OCx
64 * is enabled and active high.
67 #if BEEPER_CHANNEL == 1
68 stm_tim1.ccmr1 = ((0 << STM_TIM1_CCMR1_OC2CE) |
69 (STM_TIM1_CCMR1_OCM_FROZEN << STM_TIM1_CCMR1_OC2M) |
70 (0 << STM_TIM1_CCMR1_OC2PE) |
71 (0 << STM_TIM1_CCMR1_OC2FE) |
72 (STM_TIM1_CCMR1_CCS_OUTPUT << STM_TIM1_CCMR1_CC2S) |
74 (0 << STM_TIM1_CCMR1_OC1CE) |
75 (STM_TIM1_CCMR1_OCM_TOGGLE << STM_TIM1_CCMR1_OC1M) |
76 (0 << STM_TIM1_CCMR1_OC1PE) |
77 (0 << STM_TIM1_CCMR1_OC1FE) |
78 (STM_TIM1_CCMR1_CCS_OUTPUT << STM_TIM1_CCMR1_CC1S));
80 stm_tim1.ccer = ((0 << STM_TIM1_CCER_CC4P) |
81 (0 << STM_TIM1_CCER_CC4E) |
82 (0 << STM_TIM1_CCER_CC3NP) |
83 (0 << STM_TIM1_CCER_CC3NE) |
84 (0 << STM_TIM1_CCER_CC3P) |
85 (0 << STM_TIM1_CCER_CC3E) |
86 (0 << STM_TIM1_CCER_CC2NP) |
87 (0 << STM_TIM1_CCER_CC2NE) |
88 (0 << STM_TIM1_CCER_CC2P) |
89 (0 << STM_TIM1_CCER_CC2E) |
90 (0 << STM_TIM1_CCER_CC1NE) |
91 (0 << STM_TIM1_CCER_CC1P) |
92 (1 << STM_TIM1_CCER_CC1E));
94 #if BEEPER_CHANNEL == 3
95 stm_tim1.ccmr2 = ((0 << STM_TIM1_CCMR2_OC4CE) |
96 (STM_TIM1_CCMR_OCM_FROZEN << STM_TIM1_CCMR2_OC4M) |
97 (0 << STM_TIM1_CCMR2_OC4PE) |
98 (0 << STM_TIM1_CCMR2_OC4FE) |
99 (STM_TIM1_CCMR_CCS_OUTPUT << STM_TIM1_CCMR2_CC4S) |
101 (0 << STM_TIM1_CCMR2_OC3CE) |
102 (STM_TIM1_CCMR_OCM_TOGGLE << STM_TIM1_CCMR2_OC3M) |
103 (0 << STM_TIM1_CCMR2_OC3PE) |
104 (0 << STM_TIM1_CCMR2_OC3FE) |
105 (STM_TIM1_CCMR_CCS_OUTPUT << STM_TIM1_CCMR2_CC3S));
107 stm_tim1.ccer = ((0 << STM_TIM1_CCER_CC4P) |
108 (0 << STM_TIM1_CCER_CC4E) |
109 (0 << STM_TIM1_CCER_CC3NP) |
110 (0 << STM_TIM1_CCER_CC3NE) |
111 (0 << STM_TIM1_CCER_CC3P) |
112 (1 << STM_TIM1_CCER_CC3E) |
113 (0 << STM_TIM1_CCER_CC2NP) |
114 (0 << STM_TIM1_CCER_CC2NE) |
115 (0 << STM_TIM1_CCER_CC2P) |
116 (0 << STM_TIM1_CCER_CC2E) |
117 (0 << STM_TIM1_CCER_CC1NE) |
118 (0 << STM_TIM1_CCER_CC1P) |
119 (0 << STM_TIM1_CCER_CC1E));
121 #if BEEPER_CHANNEL == 4
122 stm_tim1.ccmr2 = ((0 << STM_TIM1_CCMR2_OC4CE) |
123 (STM_TIM1_CCMR2_OC4M_TOGGLE << STM_TIM1_CCMR2_OC4M) |
124 (0 << STM_TIM1_CCMR2_OC4PE) |
125 (0 << STM_TIM1_CCMR2_OC4FE) |
126 (STM_TIM1_CCMR2_CC4S_OUTPUT << STM_TIM1_CCMR2_CC4S) |
128 (0 << STM_TIM1_CCMR2_OC3CE) |
129 (STM_TIM1_CCMR2_OC3M_FROZEN << STM_TIM1_CCMR2_OC3M) |
130 (0 << STM_TIM1_CCMR2_OC3PE) |
131 (0 << STM_TIM1_CCMR2_OC3FE) |
132 (STM_TIM1_CCMR2_CC3S_OUTPUT << STM_TIM1_CCMR2_CC3S));
134 stm_tim1.ccer = ((0 << STM_TIM1_CCER_CC4NP) |
135 (0 << STM_TIM1_CCER_CC4P) |
136 (1 << STM_TIM1_CCER_CC4E) |
137 (0 << STM_TIM1_CCER_CC3NP) |
138 (0 << STM_TIM1_CCER_CC3P) |
139 (0 << STM_TIM1_CCER_CC3E) |
140 (0 << STM_TIM1_CCER_CC2NP) |
141 (0 << STM_TIM1_CCER_CC2P) |
142 (0 << STM_TIM1_CCER_CC2E) |
143 (0 << STM_TIM1_CCER_CC1NP) |
144 (0 << STM_TIM1_CCER_CC1P) |
145 (0 << STM_TIM1_CCER_CC1E));
147 /* 5. Enable the counter by setting the CEN bit in the TIMx_CR1 register. */
149 stm_tim1.cr1 = ((STM_TIM1_CR1_CKD_1 << STM_TIM1_CR1_CKD) |
150 (0 << STM_TIM1_CR1_ARPE) |
151 (STM_TIM1_CR1_CMS_EDGE << STM_TIM1_CR1_CMS) |
152 (0 << STM_TIM1_CR1_DIR) |
153 (0 << STM_TIM1_CR1_OPM) |
154 (0 << STM_TIM1_CR1_URS) |
155 (0 << STM_TIM1_CR1_UDIS) |
156 (1 << STM_TIM1_CR1_CEN));
158 /* Update the values */
159 stm_tim1.egr = (1 << STM_TIM1_EGR_UG);
164 ao_beep_for(uint8_t beep, uint16_t ticks) __reentrant
174 #if BEEPER_CHANNEL == 3
175 /* Our beeper is on PA10, which is hooked to TIM1_CH3.
177 ao_enable_port(&stm_gpioa);
178 stm_afr_set(&stm_gpioa, 10, STM_AFR_AF2);
180 #error unknown beeper channel
182 /* Leave the timer off until requested */
184 stm_rcc.apb2enr &= ~(1 << STM_RCC_APB2ENR_TIM1EN);