2 * Copyright © 2012 Keith Packard <keithp@keithp.com>
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
12 * General Public License for more details.
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
19 #ifndef _AO_ARCH_FUNCS_H_
20 #define _AO_ARCH_FUNCS_H_
27 /* PCLK is set to 48MHz (HCLK 48MHz, HPRE 1, PPRE 1) */
29 #define _AO_SPI_SPEED_24MHz STM_SPI_CR1_BR_PCLK_2
30 #define _AO_SPI_SPEED_12MHz STM_SPI_CR1_BR_PCLK_4
31 #define _AO_SPI_SPEED_6MHz STM_SPI_CR1_BR_PCLK_8
32 #define _AO_SPI_SPEED_3MHz STM_SPI_CR1_BR_PCLK_16
33 #define _AO_SPI_SPEED_1500kHz STM_SPI_CR1_BR_PCLK_32
34 #define _AO_SPI_SPEED_750kHz STM_SPI_CR1_BR_PCLK_64
35 #define _AO_SPI_SPEED_375kHz STM_SPI_CR1_BR_PCLK_128
36 #define _AO_SPI_SPEED_187500Hz STM_SPI_CR1_BR_PCLK_256
38 static inline uint32_t
39 ao_spi_speed(uint32_t hz)
41 if (hz >=24000000) return _AO_SPI_SPEED_24MHz;
42 if (hz >=12000000) return _AO_SPI_SPEED_12MHz;
43 if (hz >= 6000000) return _AO_SPI_SPEED_6MHz;
44 if (hz >= 3000000) return _AO_SPI_SPEED_3MHz;
45 if (hz >= 1500000) return _AO_SPI_SPEED_1500kHz;
46 if (hz >= 750000) return _AO_SPI_SPEED_750kHz;
47 if (hz >= 375000) return _AO_SPI_SPEED_375kHz;
48 return _AO_SPI_SPEED_187500Hz;
51 #define AO_SPI_CONFIG_1 0x00
52 #define AO_SPI_1_CONFIG_PA5_PA6_PA7 AO_SPI_CONFIG_1
53 #define AO_SPI_2_CONFIG_PB13_PB14_PB15 AO_SPI_CONFIG_1
55 #define AO_SPI_CONFIG_2 0x04
56 #define AO_SPI_1_CONFIG_PB3_PB4_PB5 AO_SPI_CONFIG_2
57 #define AO_SPI_2_CONFIG_PD1_PD3_PD4 AO_SPI_CONFIG_2
59 #define AO_SPI_CONFIG_3 0x08
60 #define AO_SPI_1_CONFIG_PE13_PE14_PE15 AO_SPI_CONFIG_3
62 #define AO_SPI_CONFIG_NONE 0x0c
64 #define AO_SPI_INDEX_MASK 0x01
65 #define AO_SPI_CONFIG_MASK 0x0c
67 #define AO_SPI_1_PA5_PA6_PA7 (STM_SPI_INDEX(1) | AO_SPI_1_CONFIG_PA5_PA6_PA7)
68 #define AO_SPI_1_PB3_PB4_PB5 (STM_SPI_INDEX(1) | AO_SPI_1_CONFIG_PB3_PB4_PB5)
69 #define AO_SPI_1_PE13_PE14_PE15 (STM_SPI_INDEX(1) | AO_SPI_1_CONFIG_PE13_PE14_PE15)
71 #define AO_SPI_2_PB13_PB14_PB15 (STM_SPI_INDEX(2) | AO_SPI_2_CONFIG_PB13_PB14_PB15)
72 #define AO_SPI_2_PD1_PD3_PD4 (STM_SPI_INDEX(2) | AO_SPI_2_CONFIG_PD1_PD3_PD4)
74 #define AO_SPI_INDEX(id) ((id) & AO_SPI_INDEX_MASK)
75 #define AO_SPI_CONFIG(id) ((id) & AO_SPI_CONFIG_MASK)
78 ao_spi_try_get(uint8_t spi_index, uint32_t speed, uint8_t task_id);
81 ao_spi_get(uint8_t spi_index, uint32_t speed);
84 ao_spi_put(uint8_t spi_index);
87 ao_spi_send(const void *block, uint16_t len, uint8_t spi_index);
90 ao_spi_send_fixed(uint8_t value, uint16_t len, uint8_t spi_index);
93 ao_spi_send_sync(const void *block, uint16_t len, uint8_t spi_index);
96 ao_spi_start_bytes(uint8_t spi_index);
99 ao_spi_stop_bytes(uint8_t spi_index);
102 ao_spi_send_byte(uint8_t byte, uint8_t spi_index)
104 struct stm_spi *stm_spi;
106 switch (AO_SPI_INDEX(spi_index)) {
115 while (!(stm_spi->sr & (1 << STM_SPI_SR_TXE)))
118 while (!(stm_spi->sr & (1 << STM_SPI_SR_RXNE)))
123 static inline uint8_t
124 ao_spi_recv_byte(uint8_t spi_index)
126 struct stm_spi *stm_spi;
128 switch (AO_SPI_INDEX(spi_index)) {
137 while (!(stm_spi->sr & (1 << STM_SPI_SR_TXE)))
140 while (!(stm_spi->sr & (1 << STM_SPI_SR_RXNE)))
146 ao_spi_recv(void *block, uint16_t len, uint8_t spi_index);
149 ao_spi_duplex(void *out, void *in, uint16_t len, uint8_t spi_index);
154 #define ao_spi_set_cs(reg,mask) ((reg)->bsrr = ((uint32_t) (mask)) << 16)
155 #define ao_spi_clr_cs(reg,mask) ((reg)->bsrr = (mask))
157 #define ao_spi_get_mask(reg,mask,bus, speed) do { \
158 ao_spi_get(bus, speed); \
159 ao_spi_set_cs(reg,mask); \
162 static inline uint8_t
163 ao_spi_try_get_mask(struct stm_gpio *reg, uint16_t mask, uint8_t bus, uint32_t speed, uint8_t task_id)
165 if (!ao_spi_try_get(bus, speed, task_id))
167 ao_spi_set_cs(reg, mask);
171 #define ao_spi_put_mask(reg,mask,bus) do { \
172 ao_spi_clr_cs(reg,mask); \
176 #define ao_spi_get_bit(reg,bit,bus,speed) ao_spi_get_mask(reg,(1<<bit),bus,speed)
177 #define ao_spi_put_bit(reg,bit,bus) ao_spi_put_mask(reg,(1<<bit),bus)
179 #if AO_POWER_MANAGEMENT
180 extern struct ao_power ao_power_gpioa;
181 extern struct ao_power ao_power_gpiob;
182 extern struct ao_power ao_power_gpioc;
183 extern struct ao_power ao_power_gpiof;
186 static inline void ao_enable_port(struct stm_gpio *port)
188 if ((port) == &stm_gpioa) {
189 stm_rcc.ahbenr |= (1 << STM_RCC_AHBENR_IOPAEN);
190 ao_power_register(&ao_power_gpioa);
191 } else if ((port) == &stm_gpiob) {
192 stm_rcc.ahbenr |= (1 << STM_RCC_AHBENR_IOPBEN);
193 ao_power_register(&ao_power_gpiob);
194 } else if ((port) == &stm_gpioc) {
195 stm_rcc.ahbenr |= (1 << STM_RCC_AHBENR_IOPCEN);
196 ao_power_register(&ao_power_gpioc);
197 } else if ((port) == &stm_gpiof) {
198 stm_rcc.ahbenr |= (1 << STM_RCC_AHBENR_IOPFEN);
199 ao_power_register(&ao_power_gpiof);
203 static inline void ao_disable_port(struct stm_gpio *port)
205 if ((port) == &stm_gpioa) {
206 stm_rcc.ahbenr &= ~(1 << STM_RCC_AHBENR_IOPAEN);
207 ao_power_unregister(&ao_power_gpioa);
208 } else if ((port) == &stm_gpiob) {
209 stm_rcc.ahbenr &= ~(1 << STM_RCC_AHBENR_IOPBEN);
210 ao_power_unregister(&ao_power_gpiob);
211 } else if ((port) == &stm_gpioc) {
212 stm_rcc.ahbenr &= ~(1 << STM_RCC_AHBENR_IOPCEN);
213 ao_power_unregister(&ao_power_gpioc);
214 } else if ((port) == &stm_gpiof) {
215 stm_rcc.ahbenr &= ~(1 << STM_RCC_AHBENR_IOPFEN);
216 ao_power_unregister(&ao_power_gpiof);
220 #define ao_gpio_set(port, bit, v) stm_gpio_set(port, bit, v)
222 #define ao_gpio_get(port, bit) stm_gpio_get(port, bit)
224 #define ao_enable_output(port,bit,v) do { \
225 ao_enable_port(port); \
226 ao_gpio_set(port, bit, v); \
227 stm_moder_set(port, bit, STM_MODER_OUTPUT);\
230 #define ao_gpio_set_mode(port,bit,mode) do { \
231 if (mode == AO_EXTI_MODE_PULL_UP) \
232 stm_pupdr_set(port, bit, STM_PUPDR_PULL_UP); \
233 else if (mode == AO_EXTI_MODE_PULL_DOWN) \
234 stm_pupdr_set(port, bit, STM_PUPDR_PULL_DOWN); \
236 stm_pupdr_set(port, bit, STM_PUPDR_NONE); \
239 #define ao_enable_input(port,bit,mode) do { \
240 ao_enable_port(port); \
241 stm_moder_set(port, bit, STM_MODER_INPUT); \
242 ao_gpio_set_mode(port, bit, mode); \
245 #define ao_enable_cs(port,bit) do { \
246 ao_enable_output(port, bit, 1); \
249 #define ao_spi_init_cs(port, mask) do { \
250 ao_enable_port(port); \
251 if ((mask) & 0x0001) ao_enable_cs(port, 0); \
252 if ((mask) & 0x0002) ao_enable_cs(port, 1); \
253 if ((mask) & 0x0004) ao_enable_cs(port, 2); \
254 if ((mask) & 0x0008) ao_enable_cs(port, 3); \
255 if ((mask) & 0x0010) ao_enable_cs(port, 4); \
256 if ((mask) & 0x0020) ao_enable_cs(port, 5); \
257 if ((mask) & 0x0040) ao_enable_cs(port, 6); \
258 if ((mask) & 0x0080) ao_enable_cs(port, 7); \
259 if ((mask) & 0x0100) ao_enable_cs(port, 8); \
260 if ((mask) & 0x0200) ao_enable_cs(port, 9); \
261 if ((mask) & 0x0400) ao_enable_cs(port, 10);\
262 if ((mask) & 0x0800) ao_enable_cs(port, 11);\
263 if ((mask) & 0x1000) ao_enable_cs(port, 12);\
264 if ((mask) & 0x2000) ao_enable_cs(port, 13);\
265 if ((mask) & 0x4000) ao_enable_cs(port, 14);\
266 if ((mask) & 0x8000) ao_enable_cs(port, 15);\
272 extern uint8_t ao_dma_done[STM_NUM_DMA];
275 ao_dma_set_transfer(uint8_t index,
276 volatile void *peripheral,
282 ao_dma_set_isr(uint8_t index, void (*isr)(int index));
285 ao_dma_start(uint8_t index);
288 ao_dma_done_transfer(uint8_t index);
291 ao_dma_abort(uint8_t index);
294 ao_dma_alloc(uint8_t index);
302 ao_i2c_get(uint8_t i2c_index);
305 ao_i2c_start(uint8_t i2c_index, uint16_t address);
308 ao_i2c_put(uint8_t i2c_index);
311 ao_i2c_send(void *block, uint16_t len, uint8_t i2c_index, uint8_t stop);
314 ao_i2c_recv(void *block, uint16_t len, uint8_t i2c_index, uint8_t stop);
319 /* ao_serial_stm.c */
321 #if USE_SERIAL_1_FLOW && USE_SERIAL_1_SW_FLOW || USE_SERIAL_2_FLOW && USE_SERIAL_2_SW_FLOW
322 #define HAS_SERIAL_SW_FLOW 1
324 #define HAS_SERIAL_SW_FLOW 0
327 #if USE_SERIAL_2_FLOW && !USE_SERIAL_2_SW_FLOW
328 #define USE_SERIAL_2_HW_FLOW 1
331 #if USE_SERIAL_1_FLOW && !USE_SERIAL_1_SW_FLOW
332 #define USE_SERIAL_1_HW_FLOW 1
335 #if USE_SERIAL_1_HW_FLOW || USE_SERIAL_2_HW_FLOW
336 #define HAS_SERIAL_HW_FLOW 1
338 #define HAS_SERIAL_HW_FLOW 0
341 struct ao_stm_usart {
342 struct ao_fifo rx_fifo;
343 struct ao_fifo tx_fifo;
344 struct stm_usart *reg;
347 #if HAS_SERIAL_SW_FLOW
348 /* RTS - 0 if we have FIFO space, 1 if not
349 * CTS - 0 if we can send, 0 if not
351 struct stm_gpio *gpio_rts;
352 struct stm_gpio *gpio_cts;
360 extern struct ao_stm_usart ao_stm_usart1;
364 extern struct ao_stm_usart ao_stm_usart2;
368 extern struct ao_stm_usart ao_stm_usart3;
371 #define ARM_PUSH32(stack, val) (*(--(stack)) = (val))
373 typedef uint32_t ao_arch_irq_t;
375 static inline uint32_t
376 ao_arch_irqsave(void) {
378 asm("mrs %0,primask" : "=&r" (primask));
379 ao_arch_block_interrupts();
384 ao_arch_irqrestore(uint32_t primask) {
385 asm("msr primask,%0" : : "r" (primask));
389 ao_arch_memory_barrier(void) {
390 asm volatile("" ::: "memory");
395 ao_arch_init_stack(struct ao_task *task, uint32_t *sp, void *start)
397 uint32_t a = (uint32_t) start;
400 /* Return address (goes into LR) */
403 /* Clear register values r0-r7 */
411 /* PRIMASK with interrupts enabled */
417 static inline void ao_arch_save_regs(void) {
418 /* Save general registers */
419 asm("push {r0-r7,lr}\n");
426 asm("mrs r0,primask");
430 static inline void ao_arch_save_stack(void) {
432 asm("mov %0,sp" : "=&r" (sp) );
433 ao_cur_task->sp32 = (sp);
434 if (sp < &ao_cur_task->stack32[0])
435 ao_panic (AO_PANIC_STACK);
438 static inline void ao_arch_restore_stack(void) {
440 asm("mov sp, %0" : : "r" (ao_cur_task->sp32) );
442 /* Restore PRIMASK */
444 asm("msr primask,r0");
448 asm("msr apsr_nczvq,r0");
450 /* Restore general registers */
451 asm("pop {r0-r7,pc}\n");
454 static inline void ao_sleep_mode(void) {
457 WFI (Wait for Interrupt) or WFE (Wait for Event) while:
458 – Set SLEEPDEEP in Cortex ® -M0 System Control register
459 – Set PDDS bit in Power Control register (PWR_CR)
460 – Clear WUF bit in Power Control/Status register (PWR_CSR)
463 ao_arch_block_interrupts();
465 /* Enable power interface clock */
466 stm_rcc.apb1enr |= (1 << STM_RCC_APB1ENR_PWREN);
468 stm_scb.scr |= (1 << STM_SCB_SCR_SLEEPDEEP);
470 stm_pwr.cr |= (1 << STM_PWR_CR_PDDS) | (1 << STM_PWR_CR_LPDS);
472 stm_pwr.cr |= (1 << STM_PWR_CR_CWUF);
482 #ifndef HAS_SAMPLE_PROFILE
483 #define HAS_SAMPLE_PROFILE 0
486 #if !HAS_SAMPLE_PROFILE
487 #define HAS_ARCH_START_SCHEDULER 1
489 static inline void ao_arch_start_scheduler(void) {
493 asm("mrs %0,msp" : "=&r" (sp));
494 asm("msr psp,%0" : : "r" (sp));
495 asm("mrs %0,control" : "=&r" (control));
497 asm("msr control,%0" : : "r" (control));
502 #define ao_arch_isr_stack()
506 #define ao_arch_wait_interrupt() do { \
508 ao_arch_release_interrupts(); \
509 asm(".global ao_idle_loc\nao_idle_loc:"); \
510 ao_arch_block_interrupts(); \
513 #define ao_arch_critical(b) do { \
514 uint32_t __mask = ao_arch_irqsave(); \
515 do { b } while (0); \
516 ao_arch_irqrestore(__mask); \
523 ao_usb_alloc(uint16_t *buffers[2]);
526 ao_usb_alloc2(uint16_t *buffers[2]);
529 ao_usb_write(uint16_t len);
532 ao_usb_write2(uint16_t len);
533 #endif /* AO_USB_DIRECTIO */
538 ao_debug_out(char c);
540 #endif /* _AO_ARCH_FUNCS_H_ */