2 * Copyright © 2012 Keith Packard <keithp@keithp.com>
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; version 2 of the License.
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
11 * General Public License for more details.
13 * You should have received a copy of the GNU General Public License along
14 * with this program; if not, write to the Free Software Foundation, Inc.,
15 * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
18 #ifndef _AO_ARCH_FUNCS_H_
19 #define _AO_ARCH_FUNCS_H_
24 /* PCLK is set to 16MHz (HCLK 32MHz, APB prescaler 2) */
26 #define AO_SPI_SPEED_8MHz STM_SPI_CR1_BR_PCLK_2
27 #define AO_SPI_SPEED_4MHz STM_SPI_CR1_BR_PCLK_4
28 #define AO_SPI_SPEED_2MHz STM_SPI_CR1_BR_PCLK_8
29 #define AO_SPI_SPEED_1MHz STM_SPI_CR1_BR_PCLK_16
30 #define AO_SPI_SPEED_500kHz STM_SPI_CR1_BR_PCLK_32
31 #define AO_SPI_SPEED_250kHz STM_SPI_CR1_BR_PCLK_64
32 #define AO_SPI_SPEED_125kHz STM_SPI_CR1_BR_PCLK_128
33 #define AO_SPI_SPEED_62500Hz STM_SPI_CR1_BR_PCLK_256
35 #define AO_SPI_SPEED_FAST AO_SPI_SPEED_8MHz
37 /* Companion bus wants something no faster than 200kHz */
39 #define AO_SPI_SPEED_200kHz AO_SPI_SPEED_125kHz
41 #define AO_SPI_CONFIG_1 0x00
42 #define AO_SPI_1_CONFIG_PA5_PA6_PA7 AO_SPI_CONFIG_1
43 #define AO_SPI_2_CONFIG_PB13_PB14_PB15 AO_SPI_CONFIG_1
45 #define AO_SPI_CONFIG_2 0x04
46 #define AO_SPI_1_CONFIG_PB3_PB4_PB5 AO_SPI_CONFIG_2
47 #define AO_SPI_2_CONFIG_PD1_PD3_PD4 AO_SPI_CONFIG_2
49 #define AO_SPI_CONFIG_3 0x08
50 #define AO_SPI_1_CONFIG_PE13_PE14_PE15 AO_SPI_CONFIG_3
52 #define AO_SPI_CONFIG_NONE 0x0c
54 #define AO_SPI_INDEX_MASK 0x01
55 #define AO_SPI_CONFIG_MASK 0x0c
57 #define AO_SPI_1_PA5_PA6_PA7 (STM_SPI_INDEX(1) | AO_SPI_1_CONFIG_PA5_PA6_PA7)
58 #define AO_SPI_1_PB3_PB4_PB5 (STM_SPI_INDEX(1) | AO_SPI_1_CONFIG_PB3_PB4_PB5)
59 #define AO_SPI_1_PE13_PE14_PE15 (STM_SPI_INDEX(1) | AO_SPI_1_CONFIG_PE13_PE14_PE15)
61 #define AO_SPI_2_PB13_PB14_PB15 (STM_SPI_INDEX(2) | AO_SPI_2_CONFIG_PB13_PB14_PB15)
62 #define AO_SPI_2_PD1_PD3_PD4 (STM_SPI_INDEX(2) | AO_SPI_2_CONFIG_PD1_PD3_PD4)
64 #define AO_SPI_INDEX(id) ((id) & AO_SPI_INDEX_MASK)
65 #define AO_SPI_CONFIG(id) ((id) & AO_SPI_CONFIG_MASK)
68 ao_spi_try_get(uint8_t spi_index, uint32_t speed, uint8_t task_id);
71 ao_spi_get(uint8_t spi_index, uint32_t speed);
74 ao_spi_put(uint8_t spi_index);
77 ao_spi_send(const void *block, uint16_t len, uint8_t spi_index);
80 ao_spi_send_fixed(uint8_t value, uint16_t len, uint8_t spi_index);
83 ao_spi_send_sync(const void *block, uint16_t len, uint8_t spi_index);
86 ao_spi_start_bytes(uint8_t spi_index);
89 ao_spi_stop_bytes(uint8_t spi_index);
92 ao_spi_send_byte(uint8_t byte, uint8_t spi_index)
94 struct stm_spi *stm_spi;
96 switch (AO_SPI_INDEX(spi_index)) {
105 while (!(stm_spi->sr & (1 << STM_SPI_SR_TXE)))
108 while (!(stm_spi->sr & (1 << STM_SPI_SR_RXNE)))
113 static inline uint8_t
114 ao_spi_recv_byte(uint8_t spi_index)
116 struct stm_spi *stm_spi;
118 switch (AO_SPI_INDEX(spi_index)) {
127 while (!(stm_spi->sr & (1 << STM_SPI_SR_TXE)))
130 while (!(stm_spi->sr & (1 << STM_SPI_SR_RXNE)))
136 ao_spi_recv(void *block, uint16_t len, uint8_t spi_index);
139 ao_spi_duplex(void *out, void *in, uint16_t len, uint8_t spi_index);
141 extern uint16_t ao_spi_speed[STM_NUM_SPI];
146 #define ao_spi_set_cs(reg,mask) ((reg)->bsrr = ((uint32_t) (mask)) << 16)
147 #define ao_spi_clr_cs(reg,mask) ((reg)->bsrr = (mask))
149 #define ao_spi_get_mask(reg,mask,bus, speed) do { \
150 ao_spi_get(bus, speed); \
151 ao_spi_set_cs(reg,mask); \
154 static inline uint8_t
155 ao_spi_try_get_mask(struct stm_gpio *reg, uint16_t mask, uint8_t bus, uint32_t speed, uint8_t task_id)
157 if (!ao_spi_try_get(bus, speed, task_id))
159 ao_spi_set_cs(reg, mask);
163 #define ao_spi_put_mask(reg,mask,bus) do { \
164 ao_spi_clr_cs(reg,mask); \
168 #define ao_spi_get_bit(reg,bit,pin,bus,speed) ao_spi_get_mask(reg,(1<<bit),bus,speed)
169 #define ao_spi_put_bit(reg,bit,pin,bus) ao_spi_put_mask(reg,(1<<bit),bus)
171 #define ao_enable_port(port) do { \
172 if ((port) == &stm_gpioa) \
173 stm_rcc.ahbenr |= (1 << STM_RCC_AHBENR_GPIOAEN); \
174 else if ((port) == &stm_gpiob) \
175 stm_rcc.ahbenr |= (1 << STM_RCC_AHBENR_GPIOBEN); \
176 else if ((port) == &stm_gpioc) \
177 stm_rcc.ahbenr |= (1 << STM_RCC_AHBENR_GPIOCEN); \
178 else if ((port) == &stm_gpiod) \
179 stm_rcc.ahbenr |= (1 << STM_RCC_AHBENR_GPIODEN); \
180 else if ((port) == &stm_gpioe) \
181 stm_rcc.ahbenr |= (1 << STM_RCC_AHBENR_GPIOEEN); \
184 #define ao_disable_port(port) do { \
185 if ((port) == &stm_gpioa) \
186 stm_rcc.ahbenr &= ~(1 << STM_RCC_AHBENR_GPIOAEN); \
187 else if ((port) == &stm_gpiob) \
188 stm_rcc.ahbenr &= ~(1 << STM_RCC_AHBENR_GPIOBEN); \
189 else if ((port) == &stm_gpioc) \
190 stm_rcc.ahbenr &= ~(1 << STM_RCC_AHBENR_GPIOCEN); \
191 else if ((port) == &stm_gpiod) \
192 stm_rcc.ahbenr &= ~(1 << STM_RCC_AHBENR_GPIODEN); \
193 else if ((port) == &stm_gpioe) \
194 stm_rcc.ahbenr &= ~(1 << STM_RCC_AHBENR_GPIOEEN); \
198 #define ao_gpio_set(port, bit, pin, v) stm_gpio_set(port, bit, v)
200 #define ao_gpio_get(port, bit, pin) stm_gpio_get(port, bit)
202 #define ao_gpio_set_bits(port, bits) stm_gpio_set_bits(port, bits)
204 #define ao_gpio_clr_bits(port, bits) stm_gpio_clr_bits(port, bits);
207 #define ao_enable_output(port,bit,pin,v) do { \
208 ao_enable_port(port); \
209 ao_gpio_set(port, bit, pin, v); \
210 stm_moder_set(port, bit, STM_MODER_OUTPUT);\
213 #define ao_gpio_set_mode(port,bit,mode) do { \
214 if (mode == AO_EXTI_MODE_PULL_UP) \
215 stm_pupdr_set(port, bit, STM_PUPDR_PULL_UP); \
216 else if (mode == AO_EXTI_MODE_PULL_DOWN) \
217 stm_pupdr_set(port, bit, STM_PUPDR_PULL_DOWN); \
219 stm_pupdr_set(port, bit, STM_PUPDR_NONE); \
222 #define ao_enable_input(port,bit,mode) do { \
223 ao_enable_port(port); \
224 stm_moder_set(port, bit, STM_MODER_INPUT); \
225 ao_gpio_set_mode(port, bit, mode); \
228 #define ao_enable_cs(port,bit) do { \
229 stm_gpio_set((port), bit, 1); \
230 stm_moder_set((port), bit, STM_MODER_OUTPUT); \
233 #define ao_spi_init_cs(port, mask) do { \
234 ao_enable_port(port); \
235 if ((mask) & 0x0001) ao_enable_cs(port, 0); \
236 if ((mask) & 0x0002) ao_enable_cs(port, 1); \
237 if ((mask) & 0x0004) ao_enable_cs(port, 2); \
238 if ((mask) & 0x0008) ao_enable_cs(port, 3); \
239 if ((mask) & 0x0010) ao_enable_cs(port, 4); \
240 if ((mask) & 0x0020) ao_enable_cs(port, 5); \
241 if ((mask) & 0x0040) ao_enable_cs(port, 6); \
242 if ((mask) & 0x0080) ao_enable_cs(port, 7); \
243 if ((mask) & 0x0100) ao_enable_cs(port, 8); \
244 if ((mask) & 0x0200) ao_enable_cs(port, 9); \
245 if ((mask) & 0x0400) ao_enable_cs(port, 10);\
246 if ((mask) & 0x0800) ao_enable_cs(port, 11);\
247 if ((mask) & 0x1000) ao_enable_cs(port, 12);\
248 if ((mask) & 0x2000) ao_enable_cs(port, 13);\
249 if ((mask) & 0x4000) ao_enable_cs(port, 14);\
250 if ((mask) & 0x8000) ao_enable_cs(port, 15);\
256 extern uint8_t ao_dma_done[STM_NUM_DMA];
259 ao_dma_set_transfer(uint8_t index,
260 volatile void *peripheral,
266 ao_dma_set_isr(uint8_t index, void (*isr)(int index));
269 ao_dma_start(uint8_t index);
272 ao_dma_done_transfer(uint8_t index);
275 ao_dma_alloc(uint8_t index);
283 ao_i2c_get(uint8_t i2c_index);
286 ao_i2c_start(uint8_t i2c_index, uint16_t address);
289 ao_i2c_put(uint8_t i2c_index);
292 ao_i2c_send(void *block, uint16_t len, uint8_t i2c_index, uint8_t stop);
295 ao_i2c_recv(void *block, uint16_t len, uint8_t i2c_index, uint8_t stop);
300 #if USE_SERIAL_1_SW_FLOW || USE_SERIAL_2_SW_FLOW || USE_SERIAL_3_SW_FLOW
301 #define HAS_SERIAL_SW_FLOW 1
303 #define HAS_SERIAL_SW_FLOW 0
306 #if USE_SERIAL_1_FLOW && !USE_SERIAL_1_SW_FLOW || USE_SERIAL_2_FLOW && !USE_SERIAL_2_SW_FLOW || USE_SERIAL_3_FLOW && !USE_SERIAL_3_SW_FLOW
307 #define HAS_SERIAL_HW_FLOW 1
309 #define HAS_SERIAL_HW_FLOW 0
312 /* ao_serial_stm.c */
313 struct ao_stm_usart {
314 struct ao_fifo rx_fifo;
315 struct ao_fifo tx_fifo;
316 struct stm_usart *reg;
319 #if HAS_SERIAL_SW_FLOW
320 /* RTS - 0 if we have FIFO space, 1 if not
321 * CTS - 0 if we can send, 0 if not
323 struct stm_gpio *gpio_rts;
324 struct stm_gpio *gpio_cts;
332 extern struct ao_stm_usart ao_stm_usart1;
336 extern struct ao_stm_usart ao_stm_usart2;
340 extern struct ao_stm_usart ao_stm_usart3;
343 #define ARM_PUSH32(stack, val) (*(--(stack)) = (val))
345 typedef uint32_t ao_arch_irq_t;
347 static inline uint32_t
348 ao_arch_irqsave(void) {
350 asm("mrs %0,primask" : "=&r" (primask));
351 ao_arch_block_interrupts();
356 ao_arch_irqrestore(uint32_t primask) {
357 asm("msr primask,%0" : : "r" (primask));
361 ao_arch_memory_barrier() {
362 asm volatile("" ::: "memory");
366 ao_arch_irq_check(void) {
368 asm("mrs %0,primask" : "=&r" (primask));
369 if ((primask & 1) == 0)
370 ao_panic(AO_PANIC_IRQ);
375 ao_arch_init_stack(struct ao_task *task, void *start)
377 uint32_t *sp = (uint32_t *) (task->stack + AO_STACK_SIZE);
378 uint32_t a = (uint32_t) start;
381 /* Return address (goes into LR) */
384 /* Clear register values r0-r12 */
392 /* PRIMASK with interrupts enabled */
398 static inline void ao_arch_save_regs(void) {
399 /* Save general registers */
400 asm("push {r0-r12,lr}\n");
407 asm("mrs r0,primask");
411 static inline void ao_arch_save_stack(void) {
413 asm("mov %0,sp" : "=&r" (sp) );
414 ao_cur_task->sp = (sp);
415 if ((uint8_t *) sp < &ao_cur_task->stack[0])
416 ao_panic (AO_PANIC_STACK);
419 static inline void ao_arch_restore_stack(void) {
421 sp = (uint32_t) ao_cur_task->sp;
424 asm("mov sp, %0" : : "r" (sp) );
426 /* Restore PRIMASK */
428 asm("msr primask,r0");
432 asm("msr apsr_nczvq,r0");
434 /* Restore general registers */
435 asm("pop {r0-r12,lr}\n");
437 /* Return to calling function */
441 #ifndef HAS_SAMPLE_PROFILE
442 #define HAS_SAMPLE_PROFILE 0
446 #define HAS_ARCH_VALIDATE_CUR_STACK 1
449 ao_validate_cur_stack(void)
453 asm("mrs %0,psp" : "=&r" (psp));
455 psp <= ao_cur_task->stack &&
456 psp >= ao_cur_task->stack - 256)
457 ao_panic(AO_PANIC_STACK);
461 #if !HAS_SAMPLE_PROFILE
462 #define HAS_ARCH_START_SCHEDULER 1
464 static inline void ao_arch_start_scheduler(void) {
468 asm("mrs %0,msp" : "=&r" (sp));
469 asm("msr psp,%0" : : "r" (sp));
470 asm("mrs %0,control" : "=&r" (control));
472 asm("msr control,%0" : : "r" (control));
477 #define ao_arch_isr_stack()
481 #define ao_arch_wait_interrupt() do { \
483 ao_arch_release_interrupts(); \
484 asm(".global ao_idle_loc\nao_idle_loc:"); \
485 ao_arch_block_interrupts(); \
488 #define ao_arch_critical(b) do { \
489 uint32_t __mask = ao_arch_irqsave(); \
490 do { b } while (0); \
491 ao_arch_irqrestore(__mask); \
494 #endif /* _AO_ARCH_FUNCS_H_ */