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   1 /*
   2  * Copyright © 2012 Keith Packard <keithp@keithp.com>
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful, but
  10  * WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  12  * General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along
  15  * with this program; if not, write to the Free Software Foundation, Inc.,
  16  * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
  17  */
  18
  19 #include <ao.h>
  20 #include <ao_data.h>
  21
  22 static uint8_t                  ao_adc_ready;
  23
  24 #define AO_ADC_CR2_VAL          ((0 << STM_ADC_CR2_SWSTART) |           \
  25                                  (STM_ADC_CR2_EXTEN_DISABLE << STM_ADC_CR2_EXTEN) | \
  26                                  (0 << STM_ADC_CR2_EXTSEL) |            \
  27                                  (0 << STM_ADC_CR2_JWSTART) |           \
  28                                  (STM_ADC_CR2_JEXTEN_DISABLE << STM_ADC_CR2_JEXTEN) | \
  29                                  (0 << STM_ADC_CR2_JEXTSEL) |           \
  30                                  (0 << STM_ADC_CR2_ALIGN) |             \
  31                                  (0 << STM_ADC_CR2_EOCS) |              \
  32                                  (1 << STM_ADC_CR2_DDS) |               \
  33                                  (1 << STM_ADC_CR2_DMA) |               \
  34                                  (STM_ADC_CR2_DELS_UNTIL_READ << STM_ADC_CR2_DELS) | \
  35                                  (0 << STM_ADC_CR2_CONT) |              \
  36                                  (1 << STM_ADC_CR2_ADON))
  37
  38 /*
  39  * Callback from DMA ISR
  40  *
  41  * Shut down DMA engine, signal anyone waiting
  42  */
  43 static void ao_adc_done(int index)
  44 {
  45         (void) index;
  46         ao_dma_done_transfer(STM_DMA_INDEX(STM_DMA_CHANNEL_ADC1));
  47         ao_adc_ready = 1;
  48         ao_wakeup((void *) &ao_adc_ready);
  49 }
  50
  51 /*
  52  * Start the ADC sequence using the DMA engine
  53  */
  54 static void
  55 ao_adc_poll(struct ao_adc *packet)
  56 {
  57         ao_adc_ready = 0;
  58         stm_adc.sr = 0;
  59         ao_dma_set_transfer(STM_DMA_INDEX(STM_DMA_CHANNEL_ADC1),
  60                             &stm_adc.dr,
  61                             (void *) packet,
  62                             AO_NUM_ADC,
  63                             (0 << STM_DMA_CCR_MEM2MEM) |
  64                             (STM_DMA_CCR_PL_HIGH << STM_DMA_CCR_PL) |
  65                             (STM_DMA_CCR_MSIZE_16 << STM_DMA_CCR_MSIZE) |
  66                             (STM_DMA_CCR_PSIZE_16 << STM_DMA_CCR_PSIZE) |
  67                             (1 << STM_DMA_CCR_MINC) |
  68                             (0 << STM_DMA_CCR_PINC) |
  69                             (0 << STM_DMA_CCR_CIRC) |
  70                             (STM_DMA_CCR_DIR_PER_TO_MEM << STM_DMA_CCR_DIR));
  71         ao_dma_set_isr(STM_DMA_INDEX(STM_DMA_CHANNEL_ADC1), ao_adc_done);
  72         ao_dma_start(STM_DMA_INDEX(STM_DMA_CHANNEL_ADC1));
  73
  74         stm_adc.cr2 = AO_ADC_CR2_VAL | (1 << STM_ADC_CR2_SWSTART);
  75 }
  76
  77 /*
  78  * Fetch a copy of the most recent ADC data
  79  */
  80 void
  81 ao_adc_single_get(struct ao_adc *packet)
  82 {
  83         ao_adc_poll(packet);
  84         ao_arch_block_interrupts();
  85         while (!ao_adc_ready)
  86                 ao_sleep(&ao_adc_ready);
  87         ao_arch_release_interrupts();
  88 }
  89
  90 #ifdef AO_ADC_SQ1_NAME
  91 static const char *ao_adc_name[AO_NUM_ADC] = {
  92         AO_ADC_SQ1_NAME,
  93 #ifdef AO_ADC_SQ2_NAME
  94         AO_ADC_SQ2_NAME,
  95 #endif
  96 #ifdef AO_ADC_SQ3_NAME
  97         AO_ADC_SQ3_NAME,
  98 #endif
  99 #ifdef AO_ADC_SQ4_NAME
 100         AO_ADC_SQ4_NAME,
 101 #endif
 102 #ifdef AO_ADC_SQ5_NAME
 103         AO_ADC_SQ5_NAME,
 104 #endif
 105 #ifdef AO_ADC_SQ6_NAME
 106         AO_ADC_SQ6_NAME,
 107 #endif
 108 #ifdef AO_ADC_SQ7_NAME
 109         AO_ADC_SQ7_NAME,
 110 #endif
 111 #ifdef AO_ADC_SQ8_NAME
 112         AO_ADC_SQ8_NAME,
 113 #endif
 114 #ifdef AO_ADC_SQ9_NAME
 115         AO_ADC_SQ9_NAME,
 116 #endif
 117 #ifdef AO_ADC_SQ10_NAME
 118         AO_ADC_SQ10_NAME,
 119 #endif
 120 #ifdef AO_ADC_SQ11_NAME
 121         AO_ADC_SQ11_NAME,
 122 #endif
 123 #ifdef AO_ADC_SQ12_NAME
 124         AO_ADC_SQ12_NAME,
 125 #endif
 126 #ifdef AO_ADC_SQ13_NAME
 127         AO_ADC_SQ13_NAME,
 128 #endif
 129 #ifdef AO_ADC_SQ14_NAME
 130         AO_ADC_SQ14_NAME,
 131 #endif
 132 #ifdef AO_ADC_SQ15_NAME
 133         AO_ADC_SQ15_NAME,
 134 #endif
 135 #ifdef AO_ADC_SQ16_NAME
 136         AO_ADC_SQ16_NAME,
 137 #endif
 138 #ifdef AO_ADC_SQ17_NAME
 139         AO_ADC_SQ17_NAME,
 140 #endif
 141 #ifdef AO_ADC_SQ18_NAME
 142         AO_ADC_SQ18_NAME,
 143 #endif
 144 #ifdef AO_ADC_SQ19_NAME
 145         AO_ADC_SQ19_NAME,
 146 #endif
 147 #ifdef AO_ADC_SQ20_NAME
 148         AO_ADC_SQ20_NAME,
 149 #endif
 150 #ifdef AO_ADC_SQ21_NAME
 151         #error "too many ADC names"
 152 #endif
 153 };
 154 #endif
 155
 156 static void
 157 ao_adc_dump(void)
 158 {
 159         struct ao_adc   packet;
 160         ao_adc_single_get(&packet);
 161         AO_ADC_DUMP(&packet);
 162 }
 163
 164 __code struct ao_cmds ao_adc_cmds[] = {
 165         { ao_adc_dump,  "a\0Display current ADC values" },
 166         { 0, NULL },
 167 };
 168
 169 void
 170 ao_adc_single_init(void)
 171 {
 172 #ifdef AO_ADC_PIN0_PORT
 173         stm_rcc.ahbenr |= AO_ADC_RCC_AHBENR;
 174 #endif
 175
 176 #ifdef AO_ADC_PIN0_PORT
 177         stm_moder_set(AO_ADC_PIN0_PORT, AO_ADC_PIN0_PIN, STM_MODER_ANALOG);
 178 #endif
 179 #ifdef AO_ADC_PIN1_PORT
 180         stm_moder_set(AO_ADC_PIN1_PORT, AO_ADC_PIN1_PIN, STM_MODER_ANALOG);
 181 #endif
 182 #ifdef AO_ADC_PIN2_PORT
 183         stm_moder_set(AO_ADC_PIN2_PORT, AO_ADC_PIN2_PIN, STM_MODER_ANALOG);
 184 #endif
 185 #ifdef AO_ADC_PIN3_PORT
 186         stm_moder_set(AO_ADC_PIN3_PORT, AO_ADC_PIN3_PIN, STM_MODER_ANALOG);
 187 #endif
 188 #ifdef AO_ADC_PIN4_PORT
 189         stm_moder_set(AO_ADC_PIN4_PORT, AO_ADC_PIN4_PIN, STM_MODER_ANALOG);
 190 #endif
 191 #ifdef AO_ADC_PIN5_PORT
 192         stm_moder_set(AO_ADC_PIN5_PORT, AO_ADC_PIN5_PIN, STM_MODER_ANALOG);
 193 #endif
 194 #ifdef AO_ADC_PIN6_PORT
 195         stm_moder_set(AO_ADC_PIN6_PORT, AO_ADC_PIN6_PIN, STM_MODER_ANALOG);
 196 #endif
 197 #ifdef AO_ADC_PIN7_PORT
 198         stm_moder_set(AO_ADC_PIN7_PORT, AO_ADC_PIN7_PIN, STM_MODER_ANALOG);
 199 #endif
 200 #ifdef AO_ADC_PIN8_PORT
 201         stm_moder_set(AO_ADC_PIN8_PORT, AO_ADC_PIN8_PIN, STM_MODER_ANALOG);
 202 #endif
 203 #ifdef AO_ADC_PIN9_PORT
 204         stm_moder_set(AO_ADC_PIN9_PORT, AO_ADC_PIN9_PIN, STM_MODER_ANALOG);
 205 #endif
 206 #ifdef AO_ADC_PIN10_PORT
 207         stm_moder_set(AO_ADC_PIN10_PORT, AO_ADC_PIN10_PIN, STM_MODER_ANALOG);
 208 #endif
 209 #ifdef AO_ADC_PIN11_PORT
 210         stm_moder_set(AO_ADC_PIN11_PORT, AO_ADC_PIN11_PIN, STM_MODER_ANALOG);
 211 #endif
 212 #ifdef AO_ADC_PIN12_PORT
 213         stm_moder_set(AO_ADC_PIN12_PORT, AO_ADC_PIN12_PIN, STM_MODER_ANALOG);
 214 #endif
 215 #ifdef AO_ADC_PIN13_PORT
 216         stm_moder_set(AO_ADC_PIN13_PORT, AO_ADC_PIN13_PIN, STM_MODER_ANALOG);
 217 #endif
 218 #ifdef AO_ADC_PIN14_PORT
 219         stm_moder_set(AO_ADC_PIN14_PORT, AO_ADC_PIN14_PIN, STM_MODER_ANALOG);
 220 #endif
 221 #ifdef AO_ADC_PIN15_PORT
 222         stm_moder_set(AO_ADC_PIN15_PORT, AO_ADC_PIN15_PIN, STM_MODER_ANALOG);
 223 #endif
 224 #ifdef AO_ADC_PIN16_PORT
 225         stm_moder_set(AO_ADC_PIN16_PORT, AO_ADC_PIN16_PIN, STM_MODER_ANALOG);
 226 #endif
 227 #ifdef AO_ADC_PIN17_PORT
 228         stm_moder_set(AO_ADC_PIN17_PORT, AO_ADC_PIN17_PIN, STM_MODER_ANALOG);
 229 #endif
 230 #ifdef AO_ADC_PIN18_PORT
 231         stm_moder_set(AO_ADC_PIN18_PORT, AO_ADC_PIN18_PIN, STM_MODER_ANALOG);
 232 #endif
 233 #ifdef AO_ADC_PIN19_PORT
 234         stm_moder_set(AO_ADC_PIN19_PORT, AO_ADC_PIN19_PIN, STM_MODER_ANALOG);
 235 #endif
 236 #ifdef AO_ADC_PIN20_PORT
 237         stm_moder_set(AO_ADC_PIN20_PORT, AO_ADC_PIN20_PIN, STM_MODER_ANALOG);
 238 #endif
 239 #ifdef AO_ADC_PIN21_PORT
 240         stm_moder_set(AO_ADC_PIN21_PORT, AO_ADC_PIN21_PIN, STM_MODER_ANALOG);
 241 #endif
 242 #ifdef AO_ADC_PIN22_PORT
 243         stm_moder_set(AO_ADC_PIN22_PORT, AO_ADC_PIN22_PIN, STM_MODER_ANALOG);
 244 #endif
 245 #ifdef AO_ADC_PIN23_PORT
 246         stm_moder_set(AO_ADC_PIN23_PORT, AO_ADC_PIN23_PIN, STM_MODER_ANALOG);
 247 #endif
 248 #ifdef AO_ADC_PIN24_PORT
 249         #error "Too many ADC ports"
 250 #endif
 251
 252         stm_rcc.apb2enr |= (1 << STM_RCC_APB2ENR_ADC1EN);
 253
 254         /* Turn off ADC during configuration */
 255         stm_adc.cr2 = 0;
 256
 257         stm_adc.cr1 = ((0 << STM_ADC_CR1_OVRIE ) |
 258                        (STM_ADC_CR1_RES_12 << STM_ADC_CR1_RES ) |
 259                        (0 << STM_ADC_CR1_AWDEN ) |
 260                        (0 << STM_ADC_CR1_JAWDEN ) |
 261                        (0 << STM_ADC_CR1_PDI ) |
 262                        (0 << STM_ADC_CR1_PDD ) |
 263                        (0 << STM_ADC_CR1_DISCNUM ) |
 264                        (0 << STM_ADC_CR1_JDISCEN ) |
 265                        (0 << STM_ADC_CR1_DISCEN ) |
 266                        (0 << STM_ADC_CR1_JAUTO ) |
 267                        (0 << STM_ADC_CR1_AWDSGL ) |
 268                        (1 << STM_ADC_CR1_SCAN ) |
 269                        (0 << STM_ADC_CR1_JEOCIE ) |
 270                        (0 << STM_ADC_CR1_AWDIE ) |
 271                        (0 << STM_ADC_CR1_EOCIE ) |
 272                        (0 << STM_ADC_CR1_AWDCH ));
 273
 274         /* 384 cycle sample time for everyone */
 275         stm_adc.smpr1 = 0x3ffff;
 276         stm_adc.smpr2 = 0x3fffffff;
 277         stm_adc.smpr3 = 0x3fffffff;
 278
 279         stm_adc.sqr1 = ((AO_NUM_ADC - 1) << 20);
 280         stm_adc.sqr2 = 0;
 281         stm_adc.sqr3 = 0;
 282         stm_adc.sqr4 = 0;
 283         stm_adc.sqr5 = 0;
 284 #if AO_NUM_ADC > 0
 285         stm_adc.sqr5 |= (AO_ADC_SQ1 << 0);
 286 #endif
 287 #if AO_NUM_ADC > 1
 288         stm_adc.sqr5 |= (AO_ADC_SQ2 << 5);
 289 #endif
 290 #if AO_NUM_ADC > 2
 291         stm_adc.sqr5 |= (AO_ADC_SQ3 << 10);
 292 #endif
 293 #if AO_NUM_ADC > 3
 294         stm_adc.sqr5 |= (AO_ADC_SQ4 << 15);
 295 #endif
 296 #if AO_NUM_ADC > 4
 297         stm_adc.sqr5 |= (AO_ADC_SQ5 << 20);
 298 #endif
 299 #if AO_NUM_ADC > 5
 300         stm_adc.sqr5 |= (AO_ADC_SQ6 << 25);
 301 #endif
 302 #if AO_NUM_ADC > 6
 303         stm_adc.sqr4 |= (AO_ADC_SQ7 << 0);
 304 #endif
 305 #if AO_NUM_ADC > 7
 306         stm_adc.sqr4 |= (AO_ADC_SQ8 << 5);
 307 #endif
 308 #if AO_NUM_ADC > 8
 309         stm_adc.sqr4 |= (AO_ADC_SQ9 << 10);
 310 #endif
 311 #if AO_NUM_ADC > 9
 312         stm_adc.sqr4 |= (AO_ADC_SQ10 << 15);
 313 #endif
 314 #if AO_NUM_ADC > 10
 315         stm_adc.sqr4 |= (AO_ADC_SQ11 << 20);
 316 #endif
 317 #if AO_NUM_ADC > 11
 318         stm_adc.sqr4 |= (AO_ADC_SQ12 << 25);
 319 #endif
 320 #if AO_NUM_ADC > 12
 321         stm_adc.sqr3 |= (AO_ADC_SQ13 << 0);
 322 #endif
 323 #if AO_NUM_ADC > 13
 324         stm_adc.sqr3 |= (AO_ADC_SQ14 << 5);
 325 #endif
 326 #if AO_NUM_ADC > 14
 327         stm_adc.sqr3 |= (AO_ADC_SQ15 << 10);
 328 #endif
 329 #if AO_NUM_ADC > 15
 330         stm_adc.sqr3 |= (AO_ADC_SQ16 << 15);
 331 #endif
 332 #if AO_NUM_ADC > 16
 333         stm_adc.sqr3 |= (AO_ADC_SQ17 << 20);
 334 #endif
 335 #if AO_NUM_ADC > 17
 336         stm_adc.sqr3 |= (AO_ADC_SQ18 << 25);
 337 #endif
 338 #if AO_NUM_ADC > 18
 339 #error "need to finish stm_adc.sqr settings"
 340 #endif
 341
 342         /* Turn ADC on */
 343         stm_adc.cr2 = AO_ADC_CR2_VAL;
 344
 345         /* Wait for ADC to be ready */
 346         while (!(stm_adc.sr & (1 << STM_ADC_SR_ADONS)))
 347                 ;
 348
 349 #ifndef HAS_ADC_TEMP
 350 #error Please define HAS_ADC_TEMP
 351 #endif
 352 #if HAS_ADC_TEMP
 353         stm_adc.ccr = ((1 << STM_ADC_CCR_TSVREFE));
 354 #else
 355         stm_adc.ccr = 0;
 356 #endif
 357         /* Clear any stale status bits */
 358         stm_adc.sr = 0;
 359
 360         ao_dma_alloc(STM_DMA_INDEX(STM_DMA_CHANNEL_ADC1));
 361
 362         ao_cmd_register(&ao_adc_cmds[0]);
 363 }