2 * Copyright © 2019 Keith Packard <keithp@keithp.com>
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation, either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
12 * General Public License for more details.
20 typedef volatile uint64_t vuint64_t;
21 typedef volatile uint32_t vuint32_t;
22 typedef volatile void * vvoid_t;
23 typedef volatile uint16_t vuint16_t;
24 typedef volatile uint8_t vuint8_t;
31 extern struct samd21_pac samd21_pac0;
32 extern struct samd21_pac samd21_pac1;
33 extern struct samd21_pac samd21_pac2;
35 #define samd21_pac0 (*(struct samd21_pac *) 0x40000000)
36 #define samd21_pac1 (*(struct samd21_pac *) 0x41000000)
37 #define samd21_pac2 (*(struct samd21_pac *) 0x42000000)
47 extern struct samd21_gclk samd21_gclk;
49 #define samd21_gclk (*(struct samd21_gclk *) 0x40000c00)
51 #define SAMD21_GCLK_CTRL_SWRST 0
53 #define SAMD21_GCLK_STATUS_SYNCBUSY 7
55 #define SAMD21_GCLK_CLKCTRL_ID 0
56 #define SAMD21_GCLK_CLKCTRL_ID_DFLL48M_REF 0
57 #define SAMD21_GCLK_CLKCTRL_ID_DPLL 1
58 #define SAMD21_GCLK_CLKCTRL_ID_DPLL_32K 2
59 #define SAMD21_GCLK_CLKCTRL_ID_WDT 3
60 #define SAMD21_GCLK_CLKCTRL_ID_RTC 4
61 #define SAMD21_GCLK_CLKCTRL_ID_EIC 5
62 #define SAMD21_GCLK_CLKCTRL_ID_USB 6
63 #define SAMD21_GCLK_CLKCTRL_ID_EVSYS_CHANNEL_0 0x07
64 #define SAMD21_GCLK_CLKCTRL_ID_EVSYS_CHANNEL_1 0x08
65 #define SAMD21_GCLK_CLKCTRL_ID_EVSYS_CHANNEL_2 0x09
66 #define SAMD21_GCLK_CLKCTRL_ID_EVSYS_CHANNEL_3 0x0a
67 #define SAMD21_GCLK_CLKCTRL_ID_EVSYS_CHANNEL_4 0x0b
68 #define SAMD21_GCLK_CLKCTRL_ID_EVSYS_CHANNEL_5 0x0c
69 #define SAMD21_GCLK_CLKCTRL_ID_EVSYS_CHANNEL_6 0x0d
70 #define SAMD21_GCLK_CLKCTRL_ID_EVSYS_CHANNEL_7 0x0e
71 #define SAMD21_GCLK_CLKCTRL_ID_EVSYS_CHANNEL_8 0e0f
72 #define SAMD21_GCLK_CLKCTRL_ID_EVSYS_CHANNEL_9 0x10
73 #define SAMD21_GCLK_CLKCTRL_ID_EVSYS_CHANNEL_10 0x11
74 #define SAMD21_GCLK_CLKCTRL_ID_EVSYS_CHANNEL_11 0x12
75 #define SAMD21_GCLK_CLKCTRL_ID_SERCOMx_SLOW 0x13
76 #define SAMD21_GCLK_CLKCTRL_ID_SERCOM0_CORE 0x14
77 #define SAMD21_GCLK_CLKCTRL_ID_SERCOM1_CORE 0x15
78 #define SAMD21_GCLK_CLKCTRL_ID_SERCOM2_CORE 0x16
79 #define SAMD21_GCLK_CLKCTRL_ID_SERCOM3_CORE 0x17
80 #define SAMD21_GCLK_CLKCTRL_ID_SERCOM4_CORE 0x18
81 #define SAMD21_GCLK_CLKCTRL_ID_SERCOM5_CORE 0x19
82 #define SAMD21_GCLK_CLKCTRL_ID_TCC0_TCC1 0x1a
83 #define SAMD21_GCLK_CLKCTRL_ID_TCC2_TC3 0x1b
84 #define SAMD21_GCLK_CLKCTRL_ID_TC4_TC5 0x1c
85 #define SAMD21_GCLK_CLKCTRL_ID_TC6_TC7 0x1d
86 #define SAMD21_GCLK_CLKCTRL_ID_ADC 0x1e
87 #define SAMD21_GCLK_CLKCTRL_ID_AC_DIG 0x1f
88 #define SAMD21_GCLK_CLKCTRL_ID_AC_ANA 0x20
89 #define SAMD21_GCLK_CLKCTRL_ID_DAC 0x21
90 #define SAMD21_GCLK_CLKCTRL_ID_PTC 0x22
91 #define SAMD21_GCLK_CLKCTRL_ID_I2S_0 0x23
92 #define SAMD21_GCLK_CLKCTRL_ID_I2S_1 0x24
93 #define SAMD21_GCLK_CLKCTRL_ID_TCC3 0x25
95 #define SAMD21_GCLK_CLKCTRL_GEN 8
96 #define SAMD21_GCLK_CLKCTRL_CLKEN 14
97 #define SAMD21_GCLK_CLKCTRL_WRTLOCK 15
99 #define SAMD21_GCLK_GENCTRL_ID 0
100 #define SAMD21_GCLK_GENCTRL_SRC 8
101 #define SAMD21_GCLK_GENCTRL_SRC_XOSC 0
102 #define SAMD21_GCLK_GENCTRL_SRC_GCLKIN 1
103 #define SAMD21_GCLK_GENCTRL_SRC_GCLKGEN1 2
104 #define SAMD21_GCLK_GENCTRL_SRC_OSCULP32K 3
105 #define SAMD21_GCLK_GENCTRL_SRC_OSC32K 4
106 #define SAMD21_GCLK_GENCTRL_SRC_XOSC32K 5
107 #define SAMD21_GCLK_GENCTRL_SRC_OSC8M 6
108 #define SAMD21_GCLK_GENCTRL_SRC_DFLL48M 7
109 #define SAMD21_GCLK_GENCTRL_SRC_FDPLL96M 8
111 #define SAMD21_GCLK_GENCTRL_GENEN 16
112 #define SAMD21_GCLK_GENCTRL_IDC 17
113 #define SAMD21_GCLK_GENCTRL_OOV 18
114 #define SAMD21_GCLK_GENCTRL_OE 19
115 #define SAMD21_GCLK_GENCTRL_DIVSEL 20
116 #define SAMD21_GCLK_GENCTRL_RUNSTDBY 21
118 #define SAMD21_GCLK_GENDIV_ID 0
119 #define SAMD21_GCLK_GENDIV_DIV 8
124 vuint8_t reserved_02;
125 vuint8_t reserved_03;
126 vuint32_t reserved_04;
131 vuint32_t reserved_0c;
133 vuint32_t reserved_10;
139 vuint32_t reserved_24;
140 vuint32_t reserved_28;
141 vuint32_t reserved_2c;
143 vuint32_t reserved_30;
147 vuint8_t reserved_37;
151 extern struct samd21_pm samd21_pm;
153 #define samd21_pm (*(struct samd21_pm *) 0x40000400)
155 #define SAMD21_PM_CPUSEL_CPUDIV 0
156 #define SAMD21_PM_APBASEL_APBADIV 0
157 #define SAMD21_PM_APBBSEL_APBBDIV 0
158 #define SAMD21_PM_APBCSEL_APBCDIV 0
160 #define SAMD21_PM_APBAMASK_PAC0 0
161 #define SAMD21_PM_APBAMASK_PM 1
162 #define SAMD21_PM_APBAMASK_SYSCTRL 2
163 #define SAMD21_PM_APBAMASK_GCLK 3
164 #define SAMD21_PM_APBAMASK_WDT 4
165 #define SAMD21_PM_APBAMASK_RTC 5
166 #define SAMD21_PM_APBAMASK_EIC 6
168 #define SAMD21_PM_AHBMASK_HPB0 0
169 #define SAMD21_PM_AHBMASK_HPB1 1
170 #define SAMD21_PM_AHBMASK_HPB2 2
171 #define SAMD21_PM_AHBMASK_DSU 3
172 #define SAMD21_PM_AHBMASK_NVMCTRL 4
173 #define SAMD21_PM_AHBMASK_DMAC 5
174 #define SAMD21_PM_AHBMASK_USB 6
176 #define SAMD21_PM_APBBMASK_PAC1 0
177 #define SAMD21_PM_APBBMASK_DSU 1
178 #define SAMD21_PM_APBBMASK_NVMCTRL 2
179 #define SAMD21_PM_APBBMASK_PORT 3
180 #define SAMD21_PM_APBBMASK_DMAC 4
181 #define SAMD21_PM_APBBMASK_USB 5
183 #define SAMD21_PM_APBCMASK_PAC2 0
184 #define SAMD21_PM_APBCMASK_EVSYS 1
185 #define SAMD21_PM_APBCMASK_SERCOM0 2
186 #define SAMD21_PM_APBCMASK_SERCOM1 3
187 #define SAMD21_PM_APBCMASK_SERCOM2 4
188 #define SAMD21_PM_APBCMASK_SERCOM3 5
189 #define SAMD21_PM_APBCMASK_SERCOM4 6
190 #define SAMD21_PM_APBCMASK_SERCOM5 7
191 #define SAMD21_PM_APBCMASK_TCC0 8
192 #define SAMD21_PM_APBCMASK_TCC1 9
193 #define SAMD21_PM_APBCMASK_TCC2 10
194 #define SAMD21_PM_APBCMASK_TC3 11
195 #define SAMD21_PM_APBCMASK_TC4 12
196 #define SAMD21_PM_APBCMASK_TC5 13
197 #define SAMD21_PM_APBCMASK_TC6 14
198 #define SAMD21_PM_APBCMASK_TC7 15
199 #define SAMD21_PM_APBCMASK_ADC 16
200 #define SAMD21_PM_APBCMASK_AC 17
201 #define SAMD21_PM_APBCMASK_DAC 18
202 #define SAMD21_PM_APBCMASK_PTC 19
203 #define SAMD21_PM_APBCMASK_I2S 20
204 #define SAMD21_PM_APBCMASK_AC1 21
205 #define SAMD21_PM_APBCMASK_TCC3 24
207 struct samd21_sysctrl {
225 vuint32_t reserved_38;
233 vuint32_t dpllstatus;
236 extern struct samd21_sysctrl samd21_sysctrl;
238 #define samd21_sysctrl (*(struct samd21_sysctrl *) 0x40000800)
240 #define SAMD21_SYSCTRL_PCLKSR_XOSCRDY 0
241 #define SAMD21_SYSCTRL_PCLKSR_XOSC32KRDY 1
242 #define SAMD21_SYSCTRL_PCLKSR_OSC32KRDY 2
243 #define SAMD21_SYSCTRL_PCLKSR_OSC8MRDY 3
244 #define SAMD21_SYSCTRL_PCLKSR_DFLLRDY 4
245 #define SAMD21_SYSCTRL_PCLKSR_DFLLOOB 5
246 #define SAMD21_SYSCTRL_PCLKSR_DFLLLCKF 6
247 #define SAMD21_SYSCTRL_PCLKSR_DFLLLCKC 7
248 #define SAMD21_SYSCTRL_PCLKSR_DFLLRCS 8
249 #define SAMD21_SYSCTRL_PCLKSR_BOD33RDY 9
250 #define SAMD21_SYSCTRL_PCLKSR_BOD33DET 10
251 #define SAMD21_SYSCTRL_PCLKSR_B33SRDY 11
252 #define SAMD21_SYSCTRL_PCLKSR_DBPLLLCKR 15
253 #define SAMD21_SYSCTRL_PCLKSR_DPLLLCKF 16
254 #define SAMD21_SYSCTRL_PCLKSR_DPLLTO 17
256 #define SAMD21_SYSCTRL_XOSC_ENABLE 1
257 #define SAMD21_SYSCTRL_XOSC_XTALEN 2
258 #define SAMD21_SYSCTRL_XOSC_RUNSTDBY 6
259 #define SAMD21_SYSCTRL_XOSC_ONDEMAND 7
260 #define SAMD21_SYSCTRL_XOSC_GAIN 8
261 #define SAMD21_SYSCTRL_XOSC_GAIN_2MHz 0
262 #define SAMD21_SYSCTRL_XOSC_GAIN_4MHz 1
263 #define SAMD21_SYSCTRL_XOSC_GAIN_8MHz 2
264 #define SAMD21_SYSCTRL_XOSC_GAIN_16MHz 3
265 #define SAMD21_SYSCTRL_XOSC_GAIN_30MHz 4
266 #define SAMD21_SYSCTRL_XOSC_AMPGC 11
267 #define SAMD21_SYSCTRL_XOSC_STARTUP 12
268 #define SAMD21_SYSCTRL_XOSC_STARTUP_1 0
269 #define SAMD21_SYSCTRL_XOSC_STARTUP_2 1
270 #define SAMD21_SYSCTRL_XOSC_STARTUP_4 2
271 #define SAMD21_SYSCTRL_XOSC_STARTUP_8 3
272 #define SAMD21_SYSCTRL_XOSC_STARTUP_16 4
273 #define SAMD21_SYSCTRL_XOSC_STARTUP_32 5
274 #define SAMD21_SYSCTRL_XOSC_STARTUP_64 6
275 #define SAMD21_SYSCTRL_XOSC_STARTUP_128 7
276 #define SAMD21_SYSCTRL_XOSC_STARTUP_256 8
277 #define SAMD21_SYSCTRL_XOSC_STARTUP_512 9
278 #define SAMD21_SYSCTRL_XOSC_STARTUP_1024 10
279 #define SAMD21_SYSCTRL_XOSC_STARTUP_2048 11
280 #define SAMD21_SYSCTRL_XOSC_STARTUP_4096 12
281 #define SAMD21_SYSCTRL_XOSC_STARTUP_8192 13
282 #define SAMD21_SYSCTRL_XOSC_STARTUP_16384 14
283 #define SAMD21_SYSCTRL_XOSC_STARTUP_32768 15
285 #define SAMD21_SYSCTRL_XOSC32K_ENABLE 1
286 #define SAMD21_SYSCTRL_XOSC32K_XTALEN 2
287 #define SAMD21_SYSCTRL_XOSC32K_EN32K 3
288 #define SAMD21_SYSCTRL_XOSC32K_AAMPEN 5
289 #define SAMD21_SYSCTRL_XOSC32K_RUNSTDBY 6
290 #define SAMD21_SYSCTRL_XOSC32K_ONDEMAND 7
291 #define SAMD21_SYSCTRL_XOSC32K_STARTUP 8
292 #define SAMD21_SYSCTRL_XOSC32K_WRTLOCK 12
294 #define SAMD21_SYSCTRL_OSC8M_ENABLE 1
295 #define SAMD21_SYSCTRL_OSC8M_RUNSTDBY 6
296 #define SAMD21_SYSCTRL_OSC8M_ONDEMAND 7
297 #define SAMD21_SYSCTRL_OSC8M_PRESC 8
298 #define SAMD21_SYSCTRL_OSC8M_PRESC_1 0
299 #define SAMD21_SYSCTRL_OSC8M_PRESC_2 1
300 #define SAMD21_SYSCTRL_OSC8M_PRESC_4 2
301 #define SAMD21_SYSCTRL_OSC8M_PRESC_8 3
302 #define SAMD21_SYSCTRL_OSC8M_PRESC_MASK 3
303 #define SAMD21_SYSCTRL_OSC8M_CALIB 16
304 #define SAMD21_SYSCTRL_OSC8M_FRANGE 30
305 #define SAMD21_SYSCTRL_OSC8M_FRANGE_4_6 0
306 #define SAMD21_SYSCTRL_OSC8M_FRANGE_6_8 1
307 #define SAMD21_SYSCTRL_OSC8M_FRANGE_8_11 2
308 #define SAMD21_SYSCTRL_OSC8M_FRANGE_11_15 3
310 #define SAMD21_SYSCTRL_DFLLCTRL_ENABLE 1
311 #define SAMD21_SYSCTRL_DFLLCTRL_MODE 2
312 #define SAMD21_SYSCTRL_DFLLCTRL_STABLE 3
313 #define SAMD21_SYSCTRL_DFLLCTRL_LLAW 4
314 #define SAMD21_SYSCTRL_DFLLCTRL_USBCRM 5
315 #define SAMD21_SYSCTRL_DFLLCTRL_RUNSTDBY 6
316 #define SAMD21_SYSCTRL_DFLLCTRL_ONDEMAND 7
317 #define SAMD21_SYSCTRL_DFLLCTRL_CCDIS 8
318 #define SAMD21_SYSCTRL_DFLLCTRL_QLDIS 9
319 #define SAMD21_SYSCTRL_DFLLCTRL_BPLCKC 10
320 #define SAMD21_SYSCTRL_DFLLCTRL_WAITLOCK 11
322 #define SAMD21_SYSCTRL_DFLLVAL_FINE 0
323 #define SAMD21_SYSCTRL_DFLLVAL_COARSE 10
324 #define SAMD21_SYSCTRL_DFLLVAL_DIFF 16
326 #define SAMD21_SYSCTRL_DFLLMUL_MUL 0
327 #define SAMD21_SYSCTRL_DFLLMUL_FSTEP 16
328 #define SAMD21_SYSCTRL_DFLLMUL_CSTEP 26
330 #define SAMD21_SYSCTRL_DFLLSYNC_READREQ 7
332 #define SAMD21_SYSCTRL_DPLLCTRLA_ENABLE 1
333 #define SAMD21_SYSCTRL_DPLLCTRLA_RUNSTDBY 6
334 #define SAMD21_SYSCTRL_DPLLCTRLA_ONDEMAND 7
336 #define SAMD21_SYSCTRL_DPLLRATIO_LDR 0
337 #define SAMD21_SYSCTRL_DPLLRATIO_LDRFRAC 0
339 #define SAMD21_SYSCTRL_DPLLCTRLB_FILTER 0
340 #define SAMD21_SYSCTRL_DPLLCTRLB_FILTER_DEFAULT 0
341 #define SAMD21_SYSCTRL_DPLLCTRLB_FILTER_LBFILT 1
342 #define SAMD21_SYSCTRL_DPLLCTRLB_FILTER_HBFILT 2
343 #define SAMD21_SYSCTRL_DPLLCTRLB_FILTER_HDFILT 3
344 #define SAMD21_SYSCTRL_DPLLCTRLB_LPEN 2
345 #define SAMD21_SYSCTRL_DPLLCTRLB_WUF 3
346 #define SAMD21_SYSCTRL_DPLLCTRLB_REFCLK 4
347 #define SAMD21_SYSCTRL_DPLLCTRLB_REFCLK_XOSC32 0
348 #define SAMD21_SYSCTRL_DPLLCTRLB_REFCLK_XOSC 1
349 #define SAMD21_SYSCTRL_DPLLCTRLB_REFCLK_GCLK_DPLL 2
350 #define SAMD21_SYSCTRL_DPLLCTRLB_LTIME 8
351 #define SAMD21_SYSCTRL_DPLLCTRLB_LTIME_DEFAULT 0
352 #define SAMD21_SYSCTRL_DPLLCTRLB_LTIME_8MS 4
353 #define SAMD21_SYSCTRL_DPLLCTRLB_LTIME_9MS 5
354 #define SAMD21_SYSCTRL_DPLLCTRLB_LTIME_10MS 6
355 #define SAMD21_SYSCTRL_DPLLCTRLB_LTIME_11MS 7
356 #define SAMD21_SYSCTRL_DPLLCTRLB_LBYPASS 12
357 #define SAMD21_SYSCTRL_DPLLCTRLB_DIV 16
359 #define SAMD21_SYSCTRL_DPLLSTATUS_LOCK 0
360 #define SAMD21_SYSCTRL_DPLLSTATUS_CLKRDY 1
361 #define SAMD21_SYSCTRL_DPLLSTATUS_ENABLE 2
362 #define SAMD21_SYSCTRL_DPLLSTATUS_DIV 3
374 vuint32_t swtrigctrl;
376 uint32_t reserved_18;
377 uint32_t reserved_1c;
380 uint16_t reserved_22;
388 uint16_t reserved_3c;
394 uint16_t reserved_42;
396 uint32_t reserved_48;
403 extern struct samd21_dmac samd21_dmac;
405 #define samd21_dmac (*(struct samd21_dmac *) 0x41004800)
407 struct samd21_dmac_desc {
413 } __attribute__((aligned(8)));
415 #define SAMD21_DMAC_NCHAN 12
417 #define SAMD21_DMAC_CTRL_SWRST 0
418 #define SAMD21_DMAC_CTRL_DMAENABLE 1
419 #define SAMD21_DMAC_CTRL_CRCENABLE 2
420 #define SAMD21_DMAC_CTRL_LVLEN(x) (8 + (x))
422 #define SAMD21_DMAC_QOSCTRL_WRBQOS 0
423 #define SAMD21_DMAC_QOSCTRL_FQOS 2
424 #define SAMD21_DMAC_QOSCTRL_DQOS 4
426 #define SAMD21_DMAC_QOSCTRL_DISABLE 0
427 #define SAMD21_DMAC_QOSCTRL_LOW 1
428 #define SAMD21_DMAC_QOSCTRL_MEDIUM 2
429 #define SAMD21_DMAC_QOSCTRL_HIGH 3
431 #define SAMD21_DMAC_SWTRIGCTRL_SWTRIG(n) (0 + (n))
433 #define SAMD21_DMAC_PRICTRL0_LVLPRI0 0
434 #define SAMD21_DMAC_PRICTRL0_RRLVLEN0 7
435 #define SAMD21_DMAC_PRICTRL0_LVLPRI1 8
436 #define SAMD21_DMAC_PRICTRL0_RRLVLEN1 15
437 #define SAMD21_DMAC_PRICTRL0_LVLPRI2 16
438 #define SAMD21_DMAC_PRICTRL0_RRLVLEN2 23
439 #define SAMD21_DMAC_PRICTRL0_LVLPRI3 24
440 #define SAMD21_DMAC_PRICTRL0_RRLVLEN3 31
442 #define SAMD21_DMAC_INTPEND_ID 0
443 #define SAMD21_DMAC_INTPEND_ID_MASK 0xf
444 #define SAMD21_DMAC_INTPEND_TERR 8
445 #define SAMD21_DMAC_INTPEND_TCMPL 9
446 #define SAMD21_DMAC_INTPEND_SUSP 10
447 #define SAMD21_DMAC_INTPEND_FERR 13
448 #define SAMD21_DMAC_INTPEND_BUSY 14
449 #define SAMD21_DMAC_INTPEND_PEND 15
451 #define SAMD21_DMAC_INTSTATUS_CHINT(n) (0 + (n))
453 #define SAMD21_DMAC_BUSYCH_BUSYCH(n) (0 + (n))
455 #define SAMD21_DMAC_PENDCH_PENDCH(n) (0 + (n))
457 #define SAMD21_DMAC_ACTIVE_LVLEX(x) (0 + (x))
458 #define SAMD21_DMAC_ACTIVE_ID 8
459 #define SAMD21_DMAC_ACTIVE_ABUSY 15
460 #define SAMD21_DMAC_ACTIVE_BTCNT 16
462 #define SAMD21_DMAC_CHCTRLA_SWRST 0
463 #define SAMD21_DMAC_CHCTRLA_ENABLE 1
465 #define SAMD21_DMAC_CHCTRLB_EVACT 0
466 #define SAMD21_DMAC_CHCTRLB_EVACT_NOACT 0
467 #define SAMD21_DMAC_CHCTRLB_EVACT_TRIG 1
468 #define SAMD21_DMAC_CHCTRLB_EVACT_CTRIG 2
469 #define SAMD21_DMAC_CHCTRLB_EVACT_CBLOCK 3
470 #define SAMD21_DMAC_CHCTRLB_EVACT_SUSPEND 4
471 #define SAMD21_DMAC_CHCTRLB_EVACT_RESUME 5
472 #define SAMD21_DMAC_CHCTRLB_EVACT_SSKIP 6
474 #define SAMD21_DMAC_CHCTRLB_EVIE 3
475 #define SAMD21_DMAC_CHCTRLB_EVOE 4
476 #define SAMD21_DMAC_CHCTRLB_LVL 5
477 #define SAMD21_DMAC_CHCTRLB_LVL_LVL0 0UL
478 #define SAMD21_DMAC_CHCTRLB_LVL_LVL1 1UL
479 #define SAMD21_DMAC_CHCTRLB_LVL_LVL2 2UL
480 #define SAMD21_DMAC_CHCTRLB_LVL_LVL3 3UL
481 #define SAMD21_DMAC_CHCTRLB_TRIGSRC 8
482 #define SAMD21_DMAC_CHCTRLB_TRIGSRC_DISABLE 0x00UL
483 #define SAMD21_DMAC_CHCTRLB_TRIGSRC_SERCOM_RX(n) (0x01UL + (n) * 2UL)
484 #define SAMD21_DMAC_CHCTRLB_TRIGSRC_SERCOM_TX(n) (0x02UL + (n) * 2UL)
485 #define SAMD21_DMAC_CHCTRLB_TRIGSRC_TCC0_OVF 0x0dUL
486 #define SAMD21_DMAC_CHCTRLB_TRIGSRC_TCC0_MC0 0x0eUL
487 #define SAMD21_DMAC_CHCTRLB_TRIGSRC_TCC0_MC1 0x0fUL
488 #define SAMD21_DMAC_CHCTRLB_TRIGSRC_TCC0_MC2 0x10UL
489 #define SAMD21_DMAC_CHCTRLB_TRIGSRC_TCC0_MC3 0x11UL
490 #define SAMD21_DMAC_CHCTRLB_TRIGSRC_TCC1_OVF 0x12UL
491 #define SAMD21_DMAC_CHCTRLB_TRIGSRC_TCC1_MC0 0x13UL
492 #define SAMD21_DMAC_CHCTRLB_TRIGSRC_TCC1_MC1 0x14UL
493 #define SAMD21_DMAC_CHCTRLB_TRIGSRC_TCC2_OVF 0x15UL
494 #define SAMD21_DMAC_CHCTRLB_TRIGSRC_TCC2_MC0 0x16UL
495 #define SAMD21_DMAC_CHCTRLB_TRIGSRC_TCC2_MC1 0x17UL
496 #define SAMD21_DMAC_CHCTRLB_TRIGSRC_TC3_OVF 0x18UL
497 #define SAMD21_DMAC_CHCTRLB_TRIGSRC_TC3_MC0 0x19UL
498 #define SAMD21_DMAC_CHCTRLB_TRIGSRC_TC3_MC1 0x1aUL
499 #define SAMD21_DMAC_CHCTRLB_TRIGSRC_TC4_OVF 0x1bUL
500 #define SAMD21_DMAC_CHCTRLB_TRIGSRC_TC4_MC0 0x1cUL
501 #define SAMD21_DMAC_CHCTRLB_TRIGSRC_TC4_MC1 0x1dUL
502 #define SAMD21_DMAC_CHCTRLB_TRIGSRC_TC5_OVF 0x1eUL
503 #define SAMD21_DMAC_CHCTRLB_TRIGSRC_TC5_MC0 0x1fUL
504 #define SAMD21_DMAC_CHCTRLB_TRIGSRC_TC5_MC1 0x20UL
505 #define SAMD21_DMAC_CHCTRLB_TRIGSRC_TC6_OVF 0x21UL
506 #define SAMD21_DMAC_CHCTRLB_TRIGSRC_TC6_MC0 0x22UL
507 #define SAMD21_DMAC_CHCTRLB_TRIGSRC_TC6_MC1 0x23UL
508 #define SAMD21_DMAC_CHCTRLB_TRIGSRC_TC7_OVF 0x24UL
509 #define SAMD21_DMAC_CHCTRLB_TRIGSRC_TC7_MC0 0x25UL
510 #define SAMD21_DMAC_CHCTRLB_TRIGSRC_TC7_MC1 0x26UL
511 #define SAMD21_DMAC_CHCTRLB_TRIGSRC_ADC_RESRDY 0x27UL
512 #define SAMD21_DMAC_CHCTRLB_TRIGSRC_DAC_EMPTY 0x28UL
513 #define SAMD21_DMAC_CHCTRLB_TRIGSRC_I2S_RX_0 0x29UL
514 #define SAMD21_DMAC_CHCTRLB_TRIGSRC_I2S_RX_1 0x2aUL
515 #define SAMD21_DMAC_CHCTRLB_TRIGSRC_I2S_TX_0 0x2bUL
516 #define SAMD21_DMAC_CHCTRLB_TRIGSRC_I2S_TX_1 0x2cUL
517 #define SAMD21_DMAC_CHCTRLB_TRIGSRC_TCC3_OVF 0x2dUL
518 #define SAMD21_DMAC_CHCTRLB_TRIGSRC_TCC3_MC0 0x2eUL
519 #define SAMD21_DMAC_CHCTRLB_TRIGSRC_TCC3_MC1 0x2fUL
520 #define SAMD21_DMAC_CHCTRLB_TRIGSRC_TCC3_MC2 0x30UL
521 #define SAMD21_DMAC_CHCTRLB_TRIGSRC_TCC3_MC3 0x31UL
523 #define SAMD21_DMAC_CHCTRLB_TRIGACT 22
524 #define SAMD21_DMAC_CHCTRLB_TRIGACT_BLOCK 0UL
525 #define SAMD21_DMAC_CHCTRLB_TRIGACT_BEAT 2UL
526 #define SAMD21_DMAC_CHCTRLB_TRIGACT_TRANSACTION 3UL
528 #define SAMD21_DMAC_CHCTRLB_CMD 24
529 #define SAMD21_DMAC_CHCTRLB_CMD_NOACT 0UL
530 #define SAMD21_DMAC_CHCTRLB_CMD_SUSPEND 1UL
531 #define SAMD21_DMAC_CHCTRLB_CMD_RESUME 2UL
533 #define SAMD21_DMAC_CHINTFLAG_TERR 0
534 #define SAMD21_DMAC_CHINTFLAG_TCMPL 1
535 #define SAMD21_DMAC_CHINTFLAG_SUSP 2
537 #define SAMD21_DMAC_CHSTATUS_PEND 0
538 #define SAMD21_DMAC_CHSTATUS_BUSY 1
539 #define SAMD21_DMAC_CHSTATUS_FERR 2
541 #define SAMD21_DMAC_DESC_BTCTRL_VALID 0
542 #define SAMD21_DMAC_DESC_BTCTRL_EVOSEL 1
543 #define SAMD21_DMAC_DESC_BTCTRL_EVOSEL_DISABLE 0UL
544 #define SAMD21_DMAC_DESC_BTCTRL_EVOSEL_BLOCK 1UL
545 #define SAMD21_DMAC_DESC_BTCTRL_EVOSEL_BEAT 3UL
546 #define SAMD21_DMAC_DESC_BTCTRL_BLOCKACT 3
547 #define SAMD21_DMAC_DESC_BTCTRL_BLOCKACT_NOACT 0UL
548 #define SAMD21_DMAC_DESC_BTCTRL_BLOCKACT_INT 1UL
549 #define SAMD21_DMAC_DESC_BTCTRL_BLOCKACT_SUSPEND 2UL
550 #define SAMD21_DMAC_DESC_BTCTRL_BLOCKACT_BOTH 3UL
551 #define SAMD21_DMAC_DESC_BTCTRL_BEATSIZE 8
552 #define SAMD21_DMAC_DESC_BTCTRL_BEATSIZE_BYTE 0UL
553 #define SAMD21_DMAC_DESC_BTCTRL_BEATSIZE_HWORD 1UL
554 #define SAMD21_DMAC_DESC_BTCTRL_BEATSIZE_WORD 2UL
555 #define SAMD21_DMAC_DESC_BTCTRL_SRCINC 10
556 #define SAMD21_DMAC_DESC_BTCTRL_DSTINC 11
557 #define SAMD21_DMAC_DESC_BTCTRL_STEPSEL 12
558 #define SAMD21_DMAC_DESC_BTCTRL_STEPSEL_DST 0UL
559 #define SAMD21_DMAC_DESC_BTCTRL_STEPSEL_SRC 1UL
560 #define SAMD21_DMAC_DESC_BTCTRL_STEPSIZE 13
561 #define SAMD21_DMAC_DESC_BTCTRL_STEPSIZE_X1 0UL
562 #define SAMD21_DMAC_DESC_BTCTRL_STEPSIZE_X2 1UL
563 #define SAMD21_DMAC_DESC_BTCTRL_STEPSIZE_X4 2UL
564 #define SAMD21_DMAC_DESC_BTCTRL_STEPSIZE_X8 3UL
565 #define SAMD21_DMAC_DESC_BTCTRL_STEPSIZE_X16 4UL
566 #define SAMD21_DMAC_DESC_BTCTRL_STEPSIZE_X32 5UL
567 #define SAMD21_DMAC_DESC_BTCTRL_STEPSIZE_X64 6UL
568 #define SAMD21_DMAC_DESC_BTCTRL_STEPSIZE_X128 7UL
584 extern struct samd21_eic samd21_eic;
586 #define samd21_eic (*(struct samd21_eic *) 0x40001800)
588 #define SAMD21_NUM_EIC 16
590 #define SAMD21_EIC_CTRL_ENABLE 1
591 #define SAMD21_EIC_CTRL_SWRST 0
593 #define SAMD21_EIC_STATUS_SYNCBUSY 7
595 #define SAMD21_EIC_NMICTRL_NMIFILTEN 3
596 #define SAMD21_EIC_NMICTRL_NMISENSE 0
598 #define SAMD21_EIC_NMIFLAG_NMI 0
600 #define SAMD21_EIC_EVCTRL_EXTINTEO(n) (n)
602 #define SAMD21_EIC_INTENCLR_EXTINT(n) (n)
604 #define SAMD21_EIC_INTENSET_EXTINT(n) (n)
606 #define SAMD21_EIC_INTFLAG_EXTINT(n) (n)
607 #define SAMD21_EIC_WAKEUP_WAKEUPEN(n) (n)
608 #define SAMD21_EIC_CONFIG_N(n) ((n) >> 3)
609 #define SAMD21_EIC_CONFIG_SENSE(n) (((n) & 7) << 2)
610 #define SAMD21_EIC_CONFIG_FILTEN(n) (SAMD21_EIC_CONFIG_SENSE(n) + 3)
611 #define SAMD21_EIC_CONFIG_SENSE_NONE 0
612 #define SAMD21_EIC_CONFIG_SENSE_RISE 1
613 #define SAMD21_EIC_CONFIG_SENSE_FALL 2
614 #define SAMD21_EIC_CONFIG_SENSE_BOTH 3
615 #define SAMD21_EIC_CONFIG_SENSE_HIGH 4
616 #define SAMD21_EIC_CONFIG_SENSE_LOW 5
617 #define SAMD21_EIC_CONFIG_SENSE_MASK 7UL
619 struct samd21_nvmctrl {
633 extern struct samd21_nvmctrl samd21_nvmctrl;
635 #define samd21_nvmctrl (*(struct samd21_nvmctrl *) 0x41004000)
637 #define SAMD21_NVMCTRL_CTRLA_CMD 0
638 #define SAMD21_NVMCTRL_CTRLA_CMD_ER 0x02
639 #define SAMD21_NVMCTRL_CTRLA_CMD_WP 0x04
640 #define SAMD21_NVMCTRL_CTRLA_CMD_EAR 0x05
641 #define SAMD21_NVMCTRL_CTRLA_CMD_WAP 0x06
642 #define SAMD21_NVMCTRL_CTRLA_CMD_RWWEEER 0x1a
643 #define SAMD21_NVMCTRL_CTRLA_CMD_RWEEEWP 0x1c
644 #define SAMD21_NVMCTRL_CTRLA_CMD_LR 0x40
645 #define SAMD21_NVMCTRL_CTRLA_CMD_UR 0x41
646 #define SAMD21_NVMCTRL_CTRLA_CMD_SPRM 0x42
647 #define SAMD21_NVMCTRL_CTRLA_CMD_CPRM 0x43
648 #define SAMD21_NVMCTRL_CTRLA_CMD_PBC 0x44
649 #define SAMD21_NVMCTRL_CTRLA_CMD_SSB 0x45
650 #define SAMD21_NVMCTRL_CTRLA_CMD_INVALL 0x46
651 #define SAMD21_NVMCTRL_CTRLA_CMD_LDR 0x47
652 #define SAMD21_NVMCTRL_CTRLA_CMD_UDR 0x48
653 #define SAMD21_NVMCTRL_CTRLA_CMDEX 8
654 #define SAMD21_NVMCTRL_CTRLA_CMDEX_KEY 0xa5
656 #define SAMD21_NVMCTRL_CTRLB_RWS 1
657 #define SAMD21_NVMCTRL_CTRLB_MANW 7
658 #define SAMD21_NVMCTRL_CTRLB_SLEEPRM 8
659 #define SAMD21_NVMCTRL_CTRLB_READMODE 16
660 #define SAMD21_NVMCTRL_CTRLB_CACHEDIS 18
662 #define SAMD21_NVMCTRL_INTENCLR_READY 0
663 #define SAMD21_NVMCTRL_INTENCLR_ERROR 1
665 #define SAMD21_NVMCTRL_INTENSET_READY 0
666 #define SAMD21_NVMCTRL_INTENSET_ERROR 1
668 #define SAMD21_NVMCTRL_INTFLAG_READY 0
669 #define SAMD21_NVMCTRL_INTFLAG_ERROR 1
671 #define SAMD21_NVMCTRL_STATUS_PRM 0
672 #define SAMD21_NVMCTRL_STATUS_LOAD 1
673 #define SAMD21_NVMCTRL_STATUS_PROGE 2
674 #define SAMD21_NVMCTRL_STATUS_LOCKE 3
675 #define SAMD21_NVMCTRL_STATUS_NVME 4
676 #define SAMD21_NVMCTRL_STATUS_SB 8
678 #define SAMD21_NVMCTRL_PARAM_NVMP 0
679 #define SAMD21_NVMCTRL_PARAM_NVMP_MASK 0xffff
680 #define SAMD21_NVMCTRL_PARAM_PSZ 16
681 #define SAMD21_NVMCTRL_PARAM_PSZ_MASK 0x7
682 #define SAMD21_NVMCTRL_PARAM_RWWEEP 20
683 #define SAMD21_NVMCTRL_PARAM_RWWEEP_MASK 0xfff
685 static inline uint32_t
686 samd21_nvmctrl_page_shift(void)
688 return(3 + ((samd21_nvmctrl.param >> SAMD21_NVMCTRL_PARAM_PSZ) &
689 SAMD21_NVMCTRL_PARAM_PSZ_MASK));
692 static inline uint32_t
693 samd21_nvmctrl_page_size(void)
695 return 1 << samd21_nvmctrl_page_shift();
699 samd21_flash_size(void);
715 vuint32_t reserved_2c;
722 extern struct samd21_port samd21_port_a;
723 extern struct samd21_port samd21_port_b;
725 #define samd21_port_a (*(struct samd21_port *) 0x41004400)
726 #define samd21_port_b (*(struct samd21_port *) 0x41004480)
728 #define SAMD21_PORT_PINCFG_PMUXEN 0
729 #define SAMD21_PORT_PINCFG_INEN 1
730 #define SAMD21_PORT_PINCFG_PULLEN 2
731 #define SAMD21_PORT_PINCFG_DRVSTR 6
733 #define SAMD21_PORT_PMUX_FUNC_A 0
734 #define SAMD21_PORT_PMUX_FUNC_B 1
735 #define SAMD21_PORT_PMUX_FUNC_C 2
736 #define SAMD21_PORT_PMUX_FUNC_D 3
737 #define SAMD21_PORT_PMUX_FUNC_E 4
738 #define SAMD21_PORT_PMUX_FUNC_F 5
739 #define SAMD21_PORT_PMUX_FUNC_G 6
740 #define SAMD21_PORT_PMUX_FUNC_H 7
741 #define SAMD21_PORT_PMUX_FUNC_I 8
743 #define SAMD21_PORT_DIR_OUT 1
744 #define SAMD21_PORT_DIR_IN 0
747 samd21_port_dir_set(struct samd21_port *port, uint8_t pin, uint8_t dir)
750 port->dirset = (1 << pin);
752 port->dirclr = (1 << pin);
756 samd21_port_pincfg_set(struct samd21_port *port, uint8_t pin, uint8_t pincfg_mask, uint8_t pincfg)
758 port->pincfg[pin] = (uint8_t) ((port->pincfg[pin] & ~pincfg_mask) | pincfg);
761 static inline uint8_t
762 samd21_port_pincfg_get(struct samd21_port *port, uint8_t pin)
764 return port->pincfg[pin];
768 samd21_port_pmux_set(struct samd21_port *port, uint8_t pin, uint8_t func)
770 uint8_t byte = pin >> 1;
771 uint8_t bit = (pin & 1) << 2;
772 uint8_t mask = 0xf << bit;
773 uint8_t value = (uint8_t) ((port->pmux[byte] & ~mask) | (func << bit));
774 port->pmux[byte] = value;
775 samd21_port_pincfg_set(port, pin,
776 (1 << SAMD21_PORT_PINCFG_PMUXEN),
777 (1 << SAMD21_PORT_PINCFG_PMUXEN));
781 samd21_port_pmux_clr(struct samd21_port *port, uint8_t pin)
783 samd21_port_pincfg_set(port, pin,
784 (0 << SAMD21_PORT_PINCFG_PMUXEN),
785 (1 << SAMD21_PORT_PINCFG_PMUXEN));
794 vuint16_t reserved_06;
796 vuint8_t reserved_09;
797 vuint16_t reserved_0a;
799 vuint8_t reserved_0d;
800 vuint16_t reserved_0e;
804 vuint8_t reserved_15;
811 vuint16_t reserved_1e;
814 vuint16_t reserved_22;
816 vuint16_t offsetcorr;
819 vuint8_t reserved_2b;
820 vuint32_t reserved_2c;
823 #define SAMD21_ADC_CTRLA_SWRST 0
824 #define SAMD21_ADC_CTRLA_ENABLE 1
825 #define SAMD21_ADC_CTRLA_RUNSTDBY 2
827 #define SAMD21_ADC_REFCTRL_REFSEL 0
828 #define SAMD21_ADC_REFCTRL_REFSEL_INT1V 0
829 #define SAMD21_ADC_REFCTRL_REFSEL_INTVCC0 1
830 #define SAMD21_ADC_REFCTRL_REFSEL_INTVCC1 2
831 #define SAMD21_ADC_REFCTRL_REFSEL_VREFA 3
832 #define SAMD21_ADC_REFCTRL_REFSEL_VREFB 4
833 #define SAMD21_ADC_REFCTRL_REFCOMP 7
835 #define SAMD21_ADC_AVGCTRL_SAMPLENUM 0
836 #define SAMD21_ADC_AVGCTRL_ADJRES 4
838 #define SAMD21_ADC_SAMPCTRL_SAMPLEN 0
840 #define SAMD21_ADC_CTRLB_DIFFMODE 0
841 #define SAMD21_ADC_CTRLB_LEFTADJ 1
842 #define SAMD21_ADC_CTRLB_FREERUN 2
843 #define SAMD21_ADC_CTRLB_CORREN 3
844 #define SAMD21_ADC_CTRLB_RESSEL 4
845 #define SAMD21_ADC_CTRLB_RESSEL_12BIT 0
846 #define SAMD21_ADC_CTRLB_RESSEL_16BIT 1
847 #define SAMD21_ADC_CTRLB_RESSEL_10BIT 2
848 #define SAMD21_ADC_CTRLB_RESSEL_8BIT 3
849 #define SAMD21_ADC_CTRLB_PRESCALER 8
850 #define SAMD21_ADC_CTRLB_PRESCALER_DIV4 0
851 #define SAMD21_ADC_CTRLB_PRESCALER_DIV8 1
852 #define SAMD21_ADC_CTRLB_PRESCALER_DIV16 2
853 #define SAMD21_ADC_CTRLB_PRESCALER_DIV32 3
854 #define SAMD21_ADC_CTRLB_PRESCALER_DIV64 4
855 #define SAMD21_ADC_CTRLB_PRESCALER_DIV128 5
856 #define SAMD21_ADC_CTRLB_PRESCALER_DIV256 6
857 #define SAMD21_ADC_CTRLB_PRESCALER_DIV512 7
859 #define SAMD21_ADC_SWTRIG_FLUSH 0
860 #define SAMD21_ADC_SWTRIG_START 1
862 #define SAMD21_ADC_INPUTCTRL_MUXPOS 0
863 # define SAMD21_ADC_INPUTCTRL_MUXPOS_BANDGAP 0x19
864 # define SAMD21_ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC 0x1a
865 # define SAMD21_ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC 0x1b
866 # define SAMD21_ADC_INPUTCTRL_MUXPOS_DAC 0x1c
867 #define SAMD21_ADC_INPUTCTRL_MUXNEG 8
868 # define SAMD21_ADC_INPUTCTRL_MUXNEG_GND 0x18
869 # define SAMD21_ADC_INPUTCTRL_MUXNEG_IOGND 0x19
870 #define SAMD21_ADC_INPUTCTRL_INPUTSCAN 16
871 #define SAMD21_ADC_INPUTCTRL_INPUTOFFSET 20
872 #define SAMD21_ADC_INPUTCTRL_GAIN 24
873 #define SAMD21_ADC_INPUTCTRL_GAIN_1X 0
874 #define SAMD21_ADC_INPUTCTRL_GAIN_DIV2 0xf
876 #define SAMD21_ADC_INTFLAG_RESRDY 0
877 #define SAMD21_ADC_INTFLAG_OVERRUN 1
878 #define SAMD21_ADC_INTFLAG_WINMON 2
879 #define SAMD21_ADC_INTFLAG_SYNCRDY 3
881 #define SAMD21_ADC_STATUS_SYNCBUSY 7
883 #define SAMD21_ADC_CALIB_LINEARITY_CAL 0
884 #define SAMD21_ADC_CALIB_BIAS_CAL 16
886 extern struct samd21_adc samd21_adc;
888 #define samd21_adc (*(struct samd21_adc *) 0x42004000)
902 uint16_t reserved_0a;
907 #define SAMD21_DAC_CTRLA_SWRST 0
908 #define SAMD21_DAC_CTRLA_ENABLE 1
909 #define SAMD21_DAC_CTRLA_RUNSTDBY 2
911 #define SAMD21_DAC_CTRLB_EOEN 0
912 #define SAMD21_DAC_CTRLB_IOEN 1
913 #define SAMD21_DAC_CTRLB_LEFTADJ 2
914 #define SAMD21_DAC_CTRLB_VPD 3
915 #define SAMD21_DAC_CTRLB_BDWP 4
916 #define SAMD21_DAC_CTRLB_REFSEL 6
917 #define SAMD21_DAC_CTRLB_REFSEL_INTREF 0
918 #define SAMD21_DAC_CTRLB_REFSEL_VDDANA 1
919 #define SAMD21_DAC_CTRLB_REFSEL_VREFA 2
920 #define SAMD21_DAC_CTRLB_REFSEL_MASK 3
922 #define SAMD21_DAC_EVCTRL_STARTEI 0
923 #define SAMD21_DAC_EVCTRL_EMPTYEO 1
925 #define SAMD21_DAC_INTENCLR_UNDERRUN 0
926 #define SAMD21_DAC_INTENCLR_EMPTY 1
927 #define SAMD21_DAC_INTENCLR_SYNCRDY 2
929 #define SAMD21_DAC_INTENSET_UNDERRUN 0
930 #define SAMD21_DAC_INTENSET_EMPTY 1
931 #define SAMD21_DAC_INTENSET_SYNCRDY 2
933 #define SAMD21_DAC_INTFLAG_UNDERRUN 0
934 #define SAMD21_DAC_INTFLAG_EMPTY 1
935 #define SAMD21_DAC_INTFLAG_SYNCRDY 2
937 #define SAMD21_DAC_STATUS_SYNCBUSY 7
939 extern struct samd21_dac samd21_dac;
940 #define samd21_dac (*(struct samd21_dac *) 0x42004800)
949 vuint8_t reserved_07;
951 vuint8_t reserved_09;
961 vuint8_t reserved_11;
962 vuint16_t reserved_12;
964 vuint8_t reserved_15;
965 vuint16_t reserved_16;
970 vuint16_t reserved_12;
971 vuint32_t reserved_14;
976 vuint32_t reserved_14;
982 extern struct samd21_tc samd21_tc3;
983 #define samd21_tc3 (*(struct samd21_tc *) 0x42002c00)
985 extern struct samd21_tc samd21_tc4;
986 #define samd21_tc4 (*(struct samd21_tc *) 0x42003000)
988 extern struct samd21_tc samd21_tc5;
989 #define samd21_tc5 (*(struct samd21_tc *) 0x42003400)
992 /* Present on all of the samd21j parts and the samd21g16l */
993 extern struct samd21_tc samd21_tc6;
994 #define samd21_tc6 (*(struct samd21_tc *) 0x42003800)
996 extern struct samd21_tc samd21_tc7;
997 #define samd21_tc7 (*(struct samd21_tc *) 0x42003c00)
1000 #define SAMD21_TC_CTRLA_SWRST 0
1001 #define SAMD21_TC_CTRLA_ENABLE 1
1002 #define SAMD21_TC_CTRLA_MODE 2
1003 #define SAMD21_TC_CTRLA_MODE_COUNT16 0
1004 #define SAMD21_TC_CTRLA_MODE_COUNT8 1
1005 #define SAMD21_TC_CTRLA_MODE_COUNT32 2
1006 #define SAMD21_TC_CTRLA_WAVEGEN 5
1007 #define SAMD21_TC_CTRLA_WAVEGEN_NFRQ 0
1008 #define SAMD21_TC_CTRLA_WAVEGEN_MFRQ 1
1009 #define SAMD21_TC_CTRLA_WAVEGEN_NPWM 2
1010 #define SAMD21_TC_CTRLA_WAVEGEN_MPWM 3
1011 #define SAMD21_TC_CTRLA_PRESCALER 8
1012 #define SAMD21_TC_CTRLA_PRESCALER_DIV1 0
1013 #define SAMD21_TC_CTRLA_PRESCALER_DIV2 1
1014 #define SAMD21_TC_CTRLA_PRESCALER_DIV4 2
1015 #define SAMD21_TC_CTRLA_PRESCALER_DIV8 3
1016 #define SAMD21_TC_CTRLA_PRESCALER_DIV16 4
1017 #define SAMD21_TC_CTRLA_PRESCALER_DIV64 5
1018 #define SAMD21_TC_CTRLA_PRESCALER_DIV256 6
1019 #define SAMD21_TC_CTRLA_PRESCALER_DIV1024 7
1020 #define SAMD21_TC_CTRLA_RUNSTDBY 11
1021 #define SAMD21_TC_CTRLA_PRESCSYNC 12
1022 #define SAMD21_TC_CTRLA_PRESCSYNC_GCLK 0
1023 #define SAMD21_TC_CTRLA_PRESCSYNC_PRSEC 1
1024 #define SAMD21_TC_CTRLA_PRESCSYNC_RESYNC 2
1026 #define SAMD21_TC_READREQ_ADDR 0
1027 #define SAMD21_TC_READREQ_RCONT 14
1028 #define SAMD21_TC_READREQ_RREQ 15
1029 #define SAMD21_TC_CTRLB_DIR 0
1030 #define SAMD21_TC_CTRLB_ONESHOT 2
1031 #define SAMD21_TC_CTRLB_CMD 6
1032 #define SAMD21_TC_CTRLC_INVEN(x) (0 + (x))
1033 #define SAMD21_TC_CTRLC_CPTEN(x) (4 + (x))
1034 #define SAMD21_TC_DBGCTRL_DBGRUN 0
1035 #define SAMD21_TC_EVCTRL_EVACT 0
1036 #define SAMD21_TC_EVCTRL_TCINV 4
1037 #define SAMD21_TC_EVCTRL_TCEI 5
1038 #define SAMD21_TC_EVCTRL_OVFEO 8
1039 #define SAMD21_TC_EVCTRL_MCEO(x) (12 + (x))
1041 #define SAMD21_TC_INTFLAG_MC(x) (4 + (x))
1042 #define SAMD21_TC_INTFLAG_SYNCRDY 3
1043 #define SAMD21_TC_INTFLAG_ERR 1
1044 #define SAMD21_TC_INTFLAG_OVF 0
1046 #define SAMD21_TC_STATUS_STOP 3
1047 #define SAMD21_TC_STATUS_FOLLOWER 4
1048 #define SAMD21_TC_STATUS_SYNCBUSY 7
1056 vuint16_t reserved_06;
1063 vuint16_t reserved_1c;
1065 vuint8_t reserved_1f;
1075 vuint16_t reserved_3a;
1080 vuint32_t reserved_54;
1081 vuint32_t reserved_58;
1082 vuint32_t reserved_5c;
1084 vuint32_t reserved_60;
1086 vuint16_t reserved_66;
1093 extern struct samd21_tcc samd21_tcc0;
1094 #define samd21_tcc0 (*(struct samd21_tcc *) 0x42002000)
1096 extern struct samd21_tcc samd21_tcc1;
1097 #define samd21_tcc1 (*(struct samd21_tcc *) 0x42002400)
1099 extern struct samd21_tcc samd21_tcc2;
1100 #define samd21_tcc2 (*(struct samd21_tcc *) 0x42002800)
1103 /* only on the samd21e17d */
1104 extern struct samd21_tcc samd21_tcc3;
1105 #define samd21_tcc3 (*(struct samd21_tcc *) 0x42006000)
1108 #define SAMD21_TCC_CTRLA_SWRST 0
1109 #define SAMD21_TCC_CTRLA_ENABLE 1
1110 #define SAMD21_TCC_CTRLA_RESOLUTION 5
1111 #define SAMD21_TCC_CTRLA_RESOLUTION_NONE 0
1112 #define SAMD21_TCC_CTRLA_RESOLUTION_DITH4 1
1113 #define SAMD21_TCC_CTRLA_RESOLUTION_DITH5 2
1114 #define SAMD21_TCC_CTRLA_RESOLUTION_DITH6 3
1115 #define SAMD21_TCC_CTRLA_PRESCALER 8
1116 #define SAMD21_TCC_CTRLA_PRESCALER_DIV1 0
1117 #define SAMD21_TCC_CTRLA_PRESCALER_DIV2 1
1118 #define SAMD21_TCC_CTRLA_PRESCALER_DIV4 2
1119 #define SAMD21_TCC_CTRLA_PRESCALER_DIV8 3
1120 #define SAMD21_TCC_CTRLA_PRESCALER_DIV16 4
1121 #define SAMD21_TCC_CTRLA_PRESCALER_DIV64 5
1122 #define SAMD21_TCC_CTRLA_PRESCALER_DIV256 6
1123 #define SAMD21_TCC_CTRLA_PRESCALER_DIV1024 7
1124 #define SAMD21_TCC_CTRLA_RUNSTDBY 11
1125 #define SAMD21_TCC_CTRLA_PRESYNC 12
1126 #define SAMD21_TCC_CTRLA_PRESYNC_GCLK 0
1127 #define SAMD21_TCC_CTRLA_PRESYNC_PRESC 1
1128 #define SAMD21_TCC_CTRLA_PRESYNC_RESYNC 2
1129 #define SAMD21_TCC_CTRLA_ALOCK 14
1130 #define SAMD21_TCC_CTRLA_CPTEN(n) (24 + (n))
1132 #define SAMD21_TCC_CTRLB_DIR 0
1133 #define SAMD21_TCC_CTRLB_LUPD 1
1134 #define SAMD21_TCC_CTRLB_ONESHOT 2
1135 #define SAMD21_TCC_CTRLB_IDXCMD 3
1136 #define SAMD21_TCC_CTRLB_IDXCMD_DISABLE 0
1137 #define SAMD21_TCC_CTRLB_IDXCMD_SET 1
1138 #define SAMD21_TCC_CTRLB_IDXCMD_CLEAR 2
1139 #define SAMD21_TCC_CTRLB_IDXCMD_HOLD 3
1140 #define SAMD21_TCC_CTRLB_CMD 5
1141 #define SAMD21_TCC_CTRLB_CMD_NONE 0
1142 #define SAMD21_TCC_CTRLB_CMD_RETRIGGER 1
1143 #define SAMD21_TCC_CTRLB_CMD_STOP 2
1144 #define SAMD21_TCC_CTRLB_CMD_UPDATE 3
1145 #define SAMD21_TCC_CTRLB_CMD_READSYNC 4
1146 #define SAMD21_TCC_CTRLB_CMD_DMAOS 5
1148 #define SAMD21_TCC_SYNCBUSY_SWRST 0
1149 #define SAMD21_TCC_SYNCBUSY_ENABLE 1
1150 #define SAMD21_TCC_SYNCBUSY_CTRLB 2
1151 #define SAMD21_TCC_SYNCBUSY_STATUS 3
1152 #define SAMD21_TCC_SYNCBUSY_COUNT 4
1153 #define SAMD21_TCC_SYNCBUSY_PATT 5
1154 #define SAMD21_TCC_SYNCBUSY_WAVE 6
1155 #define SAMD21_TCC_SYNCBUSY_PER 7
1156 #define SAMD21_TCC_SYNCBUSY_CC(x) (8 + (x))
1157 #define SAMD21_TCC_SYNCBUSY_PATTB 16
1158 #define SAMD21_TCC_SYNCBUSY_WAVEB 17
1159 #define SAMD21_TCC_SYNCBUSY_PERB 18
1160 #define SAMD21_TCC_SYNCBUSY_CCB(x) ((19 + (x))
1162 #define SAMD21_TCC_DBGCTRL_FDDBD 2
1163 #define SAMD21_TCC_DBGCTRL_DBGRUN 0
1165 #define SAMD21_TCC_EVCTRL_EVACTO 0
1166 #define SAMD21_TCC_EVCTRL_EVACT1 3
1167 #define SAMD21_TCC_EVCTRL_CNTSEL 6
1168 #define SAMD21_TCC_EVCTRL_OVFEO 8
1169 #define SAMD21_TCC_EVCTRL_TRGEO 9
1170 #define SAMD21_TCC_EVCTRL_CNTEO 10
1171 #define SAMD21_TCC_EVCTRL_TCINV(x) (12 + (x))
1172 #define SAMD21_TCC_EVCTRL_MCEI(x) (16 + (x))
1173 #define SAMD21_TCC_EVCTRL_MCEO(x) (24 + (x))
1175 #define SAMD21_TCC_INTFLAG_OVF 0
1176 #define SAMD21_TCC_INTFLAG_TRG 1
1177 #define SAMD21_TCC_INTFLAG_CNT 2
1178 #define SAMD21_TCC_INTFLAG_ERR 3
1179 #define SAMD21_TCC_INTFLAG_UFS 10
1180 #define SAMD21_TCC_INTFLAG_DFS 11
1181 #define SAMD21_TCC_INTFLAG_FAULTA 12
1182 #define SAMD21_TCC_INTFLAG_FAULTB 13
1183 #define SAMD21_TCC_INTFLAG_FAULT0 14
1184 #define SAMD21_TCC_INTFLAG_FAULT1 15
1185 #define SAMD21_TCC_INTFLAG_MC(x) (16 + (x))
1187 #define SAMD21_TCC_WAVE_WAVEGEN 0
1188 #define SAMD21_TCC_WAVE_WAVEGEN_NFRQ 0
1189 #define SAMD21_TCC_WAVE_WAVEGEN_MFRQ 1
1190 #define SAMD21_TCC_WAVE_WAVEGEN_NPWM 2
1191 #define SAMD21_TCC_WAVE_WAVEGEN_DSCRITICAL 4
1192 #define SAMD21_TCC_WAVE_WAVEGEN_DSBOTTOM 5
1193 #define SAMD21_TCC_WAVE_WAVEGEN_DSBOTH 6
1194 #define SAMD21_TCC_WAVE_WAVEGEN_DSTOP 7
1195 #define SAMD21_TCC_WAVE_RAMP 4
1196 #define SAMD21_TCC_WAVE_CIPEREN 7
1197 #define SAMD21_TCC_WAVE_CCCEN(x) (8 + (x))
1198 #define SAMD21_TCC_WAVE_POL(x) (16 + (x))
1199 #define SAMD21_TCC_WAVE_SWAP(x) (24 + (x))
1205 vuint8_t reserved_01;
1209 vuint32_t reserved_04;
1212 vuint8_t reserved_0b;
1215 vuint16_t reserved_0e;
1218 vuint16_t reserved_12;
1220 vuint16_t reserved_16;
1222 vuint16_t reserved_1a;
1224 vuint16_t reserved_1e;
1226 vuint16_t epintsmry;
1227 vuint16_t reserved_22;
1231 uint8_t reserved_2a[0x100 - 0x2a];
1235 vuint8_t reserved_01;
1236 vuint8_t reserved_02;
1238 vuint8_t epstatusclr;
1239 vuint8_t epstatusset;
1242 vuint8_t epintenclr;
1243 vuint8_t epintenset;
1244 vuint8_t reserved_0a[0x20 - 0x0a];
1248 extern struct samd21_usb samd21_usb;
1250 #define samd21_usb (*(struct samd21_usb *) 0x41005000)
1252 #define SAMD21_USB_CTRLA_SWRST 0
1253 #define SAMD21_USB_CTRLA_ENABLE 1
1254 #define SAMD21_USB_CTRLA_RUNSTDBY 2
1255 #define SAMD21_USB_CTRLA_MODE 7
1257 #define SAMD21_USB_SYNCBUSY_SWRST 0
1258 #define SAMD21_USB_SYNCBUSY_ENABLE 1
1260 #define SAMD21_USB_QOSCTRL_CQOS 0
1261 #define SAMD21_USB_QOSCTRL_DQOS 2
1263 #define SAMD21_USB_CTRLB_DETACH 0
1264 #define SAMD21_USB_CTRLB_UPRSM 1
1265 #define SAMD21_USB_CTRLB_SPDCONF 2
1266 #define SAMD21_USB_CTRLB_SPDCONF_FS 0
1267 #define SAMD21_USB_CTRLB_SPDCONF_LS 1
1268 #define SAMD21_USB_CTRLB_SPDCONF_MASK 0x3
1269 #define SAMD21_USB_CTRLB_NREPLY 4
1270 #define SAMD21_USB_CTRLB_GNAK 9
1271 #define SAMD21_USB_CTRLB_LPMHDSK 10
1272 #define SAMD21_USB_CTRLB_LPMHDSK_NONE 0
1273 #define SAMD21_USB_CTRLB_LPMHDSK_ACK 1
1274 #define SAMD21_USB_CTRLB_LPMHDSK_NYET 2
1275 #define SAMD21_USB_CTRLB_LPMHDSK_MASK 3
1277 #define SAMD21_USB_DADD_DADD 0
1278 #define SAMD21_USB_DADD_ADDEN 7
1280 #define SAMD21_USB_STATUS_SPEED 2
1281 #define SAMD21_USB_STATUS_LINESTATE 6
1282 #define SAMD21_USB_FNUM_MFNUM 0
1283 #define SAMD21_USB_FNUM_FNUM 3
1284 #define SAMD21_USB_FNUM_FNCERR 15
1285 #define SAMD21_USB_INTFLAG_SUSPEND 0
1286 #define SAMD21_USB_INTFLAG_SOF 2
1287 #define SAMD21_USB_INTFLAG_EORST 3
1288 #define SAMD21_USB_INTFLAG_WAKEUP 4
1289 #define SAMD21_USB_INTFLAG_EORSM 5
1290 #define SAMD21_USB_INTFLAG_UPRSM 6
1291 #define SAMD21_USB_INTFLAG_RAMACER 7
1292 #define SAMD21_USB_INTFLAG_LPMNYET 8
1293 #define SAMD21_USB_INTFLAG_LPMSUSP 9
1295 #define SAMD21_USB_PADCAL_TRANSP 0
1296 #define SAMD21_USB_PADCAL_TRANSN 6
1297 #define SAMD21_USB_PADCAL_TRIM 12
1299 #define SAMD21_USB_EP_EPCFG_EP_TYPE_OUT 0
1300 #define SAMD21_USB_EP_EPCFG_EP_TYPE_OUT_DISABLED 0
1301 #define SAMD21_USB_EP_EPCFG_EP_TYPE_OUT_CONTROL 1
1302 #define SAMD21_USB_EP_EPCFG_EP_TYPE_OUT_ISOCHRONOUS 2
1303 #define SAMD21_USB_EP_EPCFG_EP_TYPE_OUT_BULK 3
1304 #define SAMD21_USB_EP_EPCFG_EP_TYPE_OUT_INTERRUPT 4
1305 #define SAMD21_USB_EP_EPCFG_EP_TYPE_OUT_DUAL_BANK 5
1306 #define SAMD21_USB_EP_EPCFG_EP_TYPE_IN 4
1307 #define SAMD21_USB_EP_EPCFG_EP_TYPE_IN_DISABLED 0
1308 #define SAMD21_USB_EP_EPCFG_EP_TYPE_IN_CONTROL 1
1309 #define SAMD21_USB_EP_EPCFG_EP_TYPE_IN_ISOCHRONOUS 2
1310 #define SAMD21_USB_EP_EPCFG_EP_TYPE_IN_BULK 3
1311 #define SAMD21_USB_EP_EPCFG_EP_TYPE_IN_INTERRUPT 4
1312 #define SAMD21_USB_EP_EPCFG_EP_TYPE_IN_DUAL_BANK 5
1314 #define SAMD21_USB_EP_EPSTATUS_DTGLOUT 0
1315 #define SAMD21_USB_EP_EPSTATUS_DTGLIN 1
1316 #define SAMD21_USB_EP_EPSTATUS_CURBK 2
1317 #define SAMD21_USB_EP_EPSTATUS_STALLRQ0 4
1318 #define SAMD21_USB_EP_EPSTATUS_STALLRQ1 5
1319 #define SAMD21_USB_EP_EPSTATUS_BK0RDY 6
1320 #define SAMD21_USB_EP_EPSTATUS_BK1RDY 7
1322 #define SAMD21_USB_EP_EPINTFLAG_TRCPT0 0
1323 #define SAMD21_USB_EP_EPINTFLAG_TRCPT1 1
1324 #define SAMD21_USB_EP_EPINTFLAG_TRFAIL0 2
1325 #define SAMD21_USB_EP_EPINTFLAG_TRFAIL1 3
1326 #define SAMD21_USB_EP_EPINTFLAG_RXSTP 4
1327 #define SAMD21_USB_EP_EPINTFLAG_STALL 5
1329 struct samd21_usb_desc_bank {
1334 vuint8_t reserved_0b;
1335 vuint32_t reserved_0c;
1338 struct samd21_usb_desc {
1339 struct samd21_usb_desc_bank bank[2];
1342 extern struct samd21_usb_desc samd21_usb_desc[8];
1344 #define SAMD21_USB_DESC_PCKSIZE_BYTE_COUNT 0
1345 #define SAMD21_USB_DESC_PCKSIZE_BYTE_COUNT_MASK 0x3fffU
1346 #define SAMD21_USB_DESC_PCKSIZE_MULTI_PACKET_SIZE 14
1347 #define SAMD21_USB_DESC_PCKSIZE_MULTI_PACKET_SIZE_MASK 0x3fffU
1348 #define SAMD21_USB_DESC_PCKSIZE_SIZE 28
1349 #define SAMD21_USB_DESC_PCKSIZE_SIZE_8 0
1350 #define SAMD21_USB_DESC_PCKSIZE_SIZE_16 1
1351 #define SAMD21_USB_DESC_PCKSIZE_SIZE_32 2
1352 #define SAMD21_USB_DESC_PCKSIZE_SIZE_64 3
1353 #define SAMD21_USB_DESC_PCKSIZE_SIZE_128 4
1354 #define SAMD21_USB_DESC_PCKSIZE_SIZE_256 5
1355 #define SAMD21_USB_DESC_PCKSIZE_SIZE_512 6
1356 #define SAMD21_USB_DESC_PCKSIZE_SIZE_1023 7
1357 #define SAMD21_USB_DESC_PCKSIZE_SIZE_MASK 7U
1358 #define SAMD21_USB_DESC_PCKSIZE_AUTO_ZLP 31
1360 static inline uint16_t
1361 samd21_usb_desc_get_byte_count(uint8_t ep, uint8_t bank)
1363 return ((samd21_usb_desc[ep].bank[bank].pcksize >> SAMD21_USB_DESC_PCKSIZE_BYTE_COUNT) &
1364 SAMD21_USB_DESC_PCKSIZE_BYTE_COUNT_MASK);
1368 samd21_usb_desc_set_byte_count(uint8_t ep, uint8_t bank, uint32_t count)
1370 uint32_t pcksize = samd21_usb_desc[ep].bank[bank].pcksize;
1372 pcksize &= ~(SAMD21_USB_DESC_PCKSIZE_BYTE_COUNT_MASK << SAMD21_USB_DESC_PCKSIZE_BYTE_COUNT);
1373 pcksize &= ~(SAMD21_USB_DESC_PCKSIZE_MULTI_PACKET_SIZE_MASK << SAMD21_USB_DESC_PCKSIZE_MULTI_PACKET_SIZE);
1374 pcksize |= (count << SAMD21_USB_DESC_PCKSIZE_BYTE_COUNT);
1375 samd21_usb_desc[ep].bank[bank].pcksize = pcksize;
1379 samd21_usb_desc_set_size(uint8_t ep, uint8_t bank, uint32_t size)
1381 uint32_t pcksize = samd21_usb_desc[ep].bank[bank].pcksize;
1383 pcksize &= ~(SAMD21_USB_DESC_PCKSIZE_SIZE_MASK << SAMD21_USB_DESC_PCKSIZE_SIZE);
1385 uint32_t size_bits = 0;
1387 case 8: size_bits = SAMD21_USB_DESC_PCKSIZE_SIZE_8; break;
1388 case 16: size_bits = SAMD21_USB_DESC_PCKSIZE_SIZE_16; break;
1389 case 32: size_bits = SAMD21_USB_DESC_PCKSIZE_SIZE_32; break;
1390 case 64: size_bits = SAMD21_USB_DESC_PCKSIZE_SIZE_64; break;
1391 case 128: size_bits = SAMD21_USB_DESC_PCKSIZE_SIZE_128; break;
1392 case 256: size_bits = SAMD21_USB_DESC_PCKSIZE_SIZE_256; break;
1393 case 512: size_bits = SAMD21_USB_DESC_PCKSIZE_SIZE_512; break;
1394 case 1023: size_bits = SAMD21_USB_DESC_PCKSIZE_SIZE_1023; break;
1396 pcksize |= (size_bits << SAMD21_USB_DESC_PCKSIZE_SIZE);
1397 samd21_usb_desc[ep].bank[bank].pcksize = pcksize;
1401 samd21_usb_ep_set_ready(uint8_t ep, uint8_t bank)
1403 samd21_usb.ep[ep].epstatusset = (1 << (SAMD21_USB_EP_EPSTATUS_BK0RDY + bank));
1404 samd21_usb.ep[ep].epintflag = (1 << (SAMD21_USB_EP_EPINTFLAG_TRFAIL0 + bank));
1408 samd21_usb_ep_clr_ready(uint8_t ep, uint8_t bank)
1410 samd21_usb.ep[ep].epstatusclr = (1 << (SAMD21_USB_EP_EPSTATUS_BK0RDY + bank));
1413 static inline uint8_t
1414 samd21_usb_ep_ready(uint8_t ep)
1416 return (samd21_usb.ep[ep].epstatus >> SAMD21_USB_EP_EPSTATUS_BK0RDY) & 3;
1419 static inline uint8_t
1420 samd21_usb_ep_curbk(uint8_t ep)
1422 return (samd21_usb.ep[ep].epstatus >> SAMD21_USB_EP_EPSTATUS_CURBK) & 1;
1427 struct samd21_evsys {
1429 vuint8_t reserved_01;
1430 vuint16_t reserved_02;
1433 vuint16_t reserved_0a;
1441 extern struct samd21_evsys samd21_evsys;
1443 #define SAMD21_NUM_EVSYS 16
1445 #define samd21_evsys (*(struct samd21_evsys *) 0x42000400)
1447 #define SAMD21_EVSYS_CONTROL_SWRST 0
1448 #define SAMD21_EVSYS_CONTROL_GCLKREQ 4
1450 #define SAMD21_EVSYS_CHANNEL_CHANNEL 0
1452 #define SAMD21_EVSYS_CHANNEL_SWEVT 8
1454 #define SAMD21_EVSYS_CHANNEL_EVGEN 16
1455 #define SAMD21_EVSYS_CHANNEL_EVGEN_NONE 0x00
1456 #define SAMD21_EVSYS_CHANNEL_EVGEN_RTC_CMP(i) (0x01 + (i))
1457 #define SAMD21_EVSYS_CHANNEL_EVGEN_OVF 0x03
1458 #define SAMD21_EVSYS_CHANNEL_EVGEN_PER(i) (0x04 + (i))
1459 #define SAMD21_EVSYS_CHANNEL_EVGEN_EXTINT(i) (0x0c + (i))
1460 #define SAMD21_EVSYS_CHANNEL_EVGEN_DMAC_CH(i) (0x1e + (i))
1461 #define SAMD21_EVSYS_CHANNEL_EVGEN_TCC0_OVF 0x22
1462 #define SAMD21_EVSYS_CHANNEL_EVGEN_TCC0_TRG 0x23
1463 #define SAMD21_EVSYS_CHANNEL_EVGEN_TCC0_CNT 0x29
1464 #define SAMD21_EVSYS_CHANNEL_EVGEN_TCC0_MCX(i) (0x25 + (i))
1465 #define SAMD21_EVSYS_CHANNEL_EVGEN_TCC1_OVF 0x29
1466 #define SAMD21_EVSYS_CHANNEL_EVGEN_TCC1_TRG 0x2a
1467 #define SAMD21_EVSYS_CHANNEL_EVGEN_TCC1_CNT 0x2b
1468 #define SAMD21_EVSYS_CHANNEL_EVGEN_TCC1_MCX(i) (0x2c + (i))
1469 #define SAMD21_EVSYS_CHANNEL_EVGEN_TCC2_OVF 0x2e
1470 #define SAMD21_EVSYS_CHANNEL_EVGEN_TCC2_TRG 0x2f
1471 #define SAMD21_EVSYS_CHANNEL_EVGEN_TCC2_CNT 0x30
1472 #define SAMD21_EVSYS_CHANNEL_EVGEN_TCC2_MCX(i) (0x31 + (i))
1473 #define SAMD21_EVSYS_CHANNEL_EVGEN_TC3_OVF 0x33
1474 #define SAMD21_EVSYS_CHANNEL_EVGEN_TC3_MC(i) (0x34 + (i))
1475 #define SAMD21_EVSYS_CHANNEL_EVGEN_TC4_OVF 0x36
1476 #define SAMD21_EVSYS_CHANNEL_EVGEN_TC4_MC(i) (0x37 + (i))
1477 #define SAMD21_EVSYS_CHANNEL_EVGEN_TC5_OVF 0x39
1478 #define SAMD21_EVSYS_CHANNEL_EVGEN_TC5_MC(i) (0x3a + (i))
1479 #define SAMD21_EVSYS_CHANNEL_EVGEN_TC6_OVF 0x3c
1480 #define SAMD21_EVSYS_CHANNEL_EVGEN_TC6_MC(i) (0x3d + (i))
1481 #define SAMD21_EVSYS_CHANNEL_EVGEN_TC7_OVF 0x3f
1482 #define SAMD21_EVSYS_CHANNEL_EVGEN_TC7_MC(i) (0x40 + (i))
1483 #define SAMD21_EVSYS_CHANNEL_EVGEN_ADC_RESRDY 0x42
1484 #define SAMD21_EVSYS_CHANNEL_EVGEN_ADC_WINMON 0x43
1485 #define SAMD21_EVSYS_CHANNEL_EVGEN_AC_COMP0 0x44
1486 #define SAMD21_EVSYS_CHANNEL_EVGEN_AC_COMP1 0x45
1487 #define SAMD21_EVSYS_CHANNEL_EVGEN_AC_WIN0 0x46
1488 #define SAMD21_EVSYS_CHANNEL_EVGEN_DAC_EMPTY 0x47
1489 #define SAMD21_EVSYS_CHANNEL_EVGEN_PTC_EOC 0x48
1490 #define SAMD21_EVSYS_CHANNEL_EVGEN_PTC_WCOMP 0x49
1491 #define SAMD21_EVSYS_CHANNEL_EVGEN_AC_COMP2 0x4a
1492 #define SAMD21_EVSYS_CHANNEL_EVGEN_AC_COMP3 0x4b
1493 #define SAMD21_EVSYS_CHANNEL_EVGEN_AC_WIN1 0x4c
1494 #define SAMD21_EVSYS_CHANNEL_EVGEN_TCC3_OVF 0x4d
1495 #define SAMD21_EVSYS_CHANNEL_EVGEN_TCC3_TRG 0x4e
1496 #define SAMD21_EVSYS_CHANNEL_EVGEN_TCC3_CNT 0x4f
1497 #define SAMD21_EVSYS_CHANNEL_EVGEN_TCC3_MCX(i) (0x50 + (i))
1499 #define SAMD21_EVSYS_CHANNEL_PATH 24
1500 #define SAMD21_EVSYS_CHANNEL_PATH_SYNCHRONOUS 0
1501 #define SAMD21_EVSYS_CHANNEL_PATH_RESYNCHRONIZED 1
1502 #define SAMD21_EVSYS_CHANNEL_PATH_ASYNCHRONOUS 2
1504 #define SAMD21_EVSYS_CHANNEL_EDGESEL 26
1505 #define SAMD21_EVSYS_CHANNEL_EDGESEL_NO_EVT_OUTPUT 0
1506 #define SAMD21_EVSYS_CHANNEL_EDGESEL_RISING_EDGE 1
1507 #define SAMD21_EVSYS_CHANNEL_EDGESEL_FALLING_EDGE 2
1508 #define SAMD21_EVSYS_CHANNEL_EDGESEL_BOTH_EDGES 3
1510 #define SAMD21_EVSYS_USER_USER 0
1511 #define SAMD21_EVSYS_USER_USER_DMAC_CH(n) (0x00 + (n))
1512 #define SAMD21_EVSYS_USER_USER_TCC0_EV(n) (0x04 + (n))
1513 #define SAMD21_EVSYS_USER_USER_TCC0_MC(n) (0x06 + (n))
1514 #define SAMD21_EVSYS_USER_USER_TCC1_EV(n) (0x0a + (n))
1515 #define SAMD21_EVSYS_USER_USER_TCC1_MC(n) (0x0c + (n))
1516 #define SAMD21_EVSYS_USER_USER_TCC2_EV(n) (0x0e + (n))
1517 #define SAMD21_EVSYS_USER_USER_TCC2_MC(n) (0x10 + (n))
1518 #define SAMD21_EVSYS_USER_USER_TC(n) (0x12 + (n))
1519 #define SAMD21_EVSYS_USER_USER_ADC_START (0x17)
1520 #define SAMD21_EVSYS_USER_USER_ADC_SYNC 0x18
1521 #define SAMD21_EVSYS_USER_USER_AC_COMP0 0x19
1522 #define SAMD21_EVSYS_USER_USER_AC_COMP1 0x1a
1523 #define SAMD21_EVSYS_USER_USER_DAC_START 0x1b
1524 #define SAMD21_EVSYS_USER_USER_PTC_STCONV 0x1c
1525 #define SAMD21_EVSYS_USER_USER_AC_COMP2 0x1d
1526 #define SAMD21_EVSYS_USER_USER_AC_COMP3 0x1e
1527 #define SAMD21_EVSYS_USER_USER_TCC3_EV(n) (0x1f + (n))
1528 #define SAMD21_EVSYS_USER_USER_TCC3_MC(n) (0x21 + (n))
1530 #define SAMD21_EVSYS_USER_CHANNEL 8
1531 #define SAMD21_EVSYS_USER_CHANNEL_NONE 0
1532 #define SAMD21_EVSYS_USER_CHANNEL_NUM(n) ((n) + 1)
1535 #define SAMD21_EVSYS_CHSTATUS_USRRDY(n) (((n) & 7) | (((n) & 8) << 1))
1536 #define SAMD21_EVSYS_CHSTATUS_CHBUSY(n) (((n) & 7) | (((n) & 8) << 1) | 8)
1540 struct samd21_sercom {
1543 vuint32_t reserved_08;
1546 vuint8_t reserved_0f;
1548 vuint32_t reserved_10;
1550 vuint8_t reserved_15;
1552 vuint8_t reserved_17;
1554 vuint8_t reserved_19;
1558 vuint32_t reserved_20;
1561 vuint16_t reserved_2a;
1562 vuint32_t reserved_2c;
1565 vuint8_t reserved_31;
1566 vuint16_t reserved_32;
1567 vuint16_t fifospace;
1571 extern struct samd21_sercom samd21_sercom0;
1572 extern struct samd21_sercom samd21_sercom1;
1573 extern struct samd21_sercom samd21_sercom2;
1574 extern struct samd21_sercom samd21_sercom3;
1575 extern struct samd21_sercom samd21_sercom4;
1576 extern struct samd21_sercom samd21_sercom5;
1578 #define SAMD21_NUM_SERCOM 6
1580 #define samd21_sercom0 (*(struct samd21_sercom *) 0x42000800)
1581 #define samd21_sercom1 (*(struct samd21_sercom *) 0x42000c00)
1582 #define samd21_sercom2 (*(struct samd21_sercom *) 0x42001000)
1583 #define samd21_sercom3 (*(struct samd21_sercom *) 0x42001400)
1584 #define samd21_sercom4 (*(struct samd21_sercom *) 0x42001800)
1585 #define samd21_sercom5 (*(struct samd21_sercom *) 0x42001c00)
1587 #define SAMD21_SERCOM_CTRLA_SWRST 0
1588 #define SAMD21_SERCOM_CTRLA_ENABLE 1
1589 #define SAMD21_SERCOM_CTRLA_MODE 2
1590 # define SAMD21_SERCOM_CTRLA_MODE_USART 1
1591 # define SAMD21_SERCOM_CTRLA_MODE_SPI_CLIENT 2
1592 # define SAMD21_SERCOM_CTRLA_MODE_SPI_HOST 3
1593 # define SAMD21_SERCOM_CTRLA_MODE_I2C_CLIENT 4
1594 # define SAMD21_SERCOM_CTRLA_MODE_I2C_HOST 5
1596 #define SAMD21_SERCOM_CTRLA_RUNSTDBY 7
1599 #define SAMD21_SERCOM_CTRLA_IBON 8
1600 #define SAMD21_SERCOM_CTRLA_SAMPR 13
1601 #define SAMD21_SERCOM_CTRLA_TXPO 16
1602 #define SAMD21_SERCOM_CTRLA_RXPO 20
1603 #define SAMD21_SERCOM_CTRLA_SAMPA 22
1604 #define SAMD21_SERCOM_CTRLA_FORM 24
1605 #define SAMD21_SERCOM_CTRLA_CMODE 28
1606 #define SAMD21_SERCOM_CTRLA_CPOL 29
1607 #define SAMD21_SERCOM_CTRLA_DORD 30
1609 /* I2C controller mode */
1610 #define SAMD21_SERCOM_CTRLA_PINOUT 16
1611 #define SAMD21_SERCOM_CTRLA_SDAHOLD 20
1612 #define SAMD21_SERCOM_CTRLA_SDAHOLD_DIS 0
1613 #define SAMD21_SERCOM_CTRLA_SDAHOLD_75NS 1
1614 #define SAMD21_SERCOM_CTRLA_SDAHOLD_450NS 2
1615 #define SAMD21_SERCOM_CTRLA_SDAHOLD_600NS 3
1616 #define SAMD21_SERCOM_CTRLA_MEXTTOEN 22
1617 #define SAMD21_SERCOM_CTRLA_SEXTTOEN 23
1618 #define SAMD21_SERCOM_CTRLA_SPEED 24
1619 #define SAMD21_SERCOM_CTRLA_SPEED_STANDARD 0
1620 #define SAMD21_SERCOM_CTRLA_SPEED_FAST 1
1621 #define SAMD21_SERCOM_CTRLA_SPEED_HIGH 2
1622 #define SAMD21_SERCOM_CTRLA_SCLSM 27
1623 #define SAMD21_SERCOM_CTRLA_INACTOUT 28
1624 #define SAMD21_SERCOM_CTRLA_INACTOUT_DIS 0
1625 #define SAMD21_SERCOM_CTRLA_INACTOUT_55US 1
1626 #define SAMD21_SERCOM_CTRLA_INACTOUT_105US 2
1627 #define SAMD21_SERCOM_CTRLA_INACTOUT_205US 3
1628 #define SAMD21_SERCOM_CTRLA_LOWTOUT 30
1630 /* SPI controller mode */
1631 #define SAMD21_SERCOM_CTRLA_DOPO 16
1632 #define SAMD21_SERCOM_CTRLA_DOPO_MOSI_0_SCLK_1 0UL
1633 #define SAMD21_SERCOM_CTRLA_DOPO_MOSI_2_SCLK_3 1UL
1634 #define SAMD21_SERCOM_CTRLA_DOPO_MOSI_3_SCLK_1 2UL
1635 #define SAMD21_SERCOM_CTRLA_DOPO_MOSI_0_SCLK_3 3UL
1636 #define SAMD21_SERCOM_CTRLA_DOPO_MASK 3UL
1638 #define SAMD21_SERCOM_CTRLA_DIPO 20
1639 #define SAMD21_SERCOM_CTRLA_DIPO_MISO_0 0UL
1640 #define SAMD21_SERCOM_CTRLA_DIPO_MISO_1 1UL
1641 #define SAMD21_SERCOM_CTRLA_DIPO_MISO_2 2UL
1642 #define SAMD21_SERCOM_CTRLA_DIPO_MISO_3 3UL
1643 #define SAMD21_SERCOM_CTRLA_DIPO_MASK 3UL
1645 #define SAMD21_SERCOM_CTRLA_FORM 24
1646 #define SAMD21_SERCOM_CTRLA_CPHA 28
1647 #define SAMD21_SERCOM_CTRLA_CPOL 29
1648 #define SAMD21_SERCOM_CTRLA_DORD 30
1649 #define SAMD21_SERCOM_CTRLA_DORD_LSB 1
1650 #define SAMD21_SERCOM_CTRLA_DORD_MSB 0
1653 #define SAMD21_SERCOM_CTRLB_CHSIZE 0
1654 #define SAMD21_SERCOM_CTRLB_SBMODE 6
1655 #define SAMD21_SERCOM_CTRLB_COLDEN 8
1656 #define SAMD21_SERCOM_CTRLB_SFDE 9
1657 #define SAMD21_SERCOM_CTRLB_ENC 10
1658 #define SAMD21_SERCOM_CTRLB_PMODE 13
1659 #define SAMD21_SERCOM_CTRLB_TXEN 16
1660 #define SAMD21_SERCOM_CTRLB_RXEN 17
1661 #define SAMD21_SERCOM_CTRLB_FIFOCLR 22
1664 #define SAMD21_SERCOM_CTRLB_SMEN 8
1665 #define SAMD21_SERCOM_CTRLB_QCEN 9
1666 #define SAMD21_SERCOM_CTRLB_CMD 16
1667 #define SAMD21_SERCOM_CTRLB_CMD_NOP 0
1668 #define SAMD21_SERCOM_CTRLB_CMD_START 1
1669 #define SAMD21_SERCOM_CTRLB_CMD_READ 2
1670 #define SAMD21_SERCOM_CTRLB_CMD_STOP 3
1671 #define SAMD21_SERCOM_CTRLB_ACKACT 18
1672 #define SAMD21_SERCOM_CTRLB_ACKACT_ACK 0
1673 #define SAMD21_SERCOM_CTRLB_ACKACT_NACK 1
1674 #define SAMD21_SERCOM_CTRLB_FIFOCLR 22
1677 #define SAMD21_SERCOM_CTRLB_CHSIZE 0
1678 # define SAMD21_SERCOM_CTRLB_CHSIZE_8 0
1679 #define SAMD21_SERCOM_CTRLB_PLOADEN 6
1680 #define SAMD21_SERCOM_CTRLB_SSDE 9
1681 #define SAMD21_SERCOM_CTRLB_MSSEN 13
1682 #define SAMD21_SERCOM_CTRLB_AMODE 14
1683 #define SAMD21_SERCOM_CTRLB_RXEN 17
1686 #define SAMD21_SERCOM_INTFLAG_DRE 0
1687 #define SAMD21_SERCOM_INTFLAG_TXC 1
1688 #define SAMD21_SERCOM_INTFLAG_RXC 2
1689 #define SAMD21_SERCOM_INTFLAG_RXS 3
1690 #define SAMD21_SERCOM_INTFLAG_CTSIC 4
1691 #define SAMD21_SERCOM_INTFLAG_RXBRK 5
1692 #define SAMD21_SERCOM_INTFLAG_ERROR 7
1695 #define SAMD21_SERCOM_INTFLAG_ERROR 7
1696 #define SAMD21_SERCOM_INTFLAG_RXFF 4
1697 #define SAMD21_SERCOM_INTFLAG_TXFE 3
1698 #define SAMD21_SERCOM_INTFLAG_SB 1
1699 #define SAMD21_SERCOM_INTFLAG_MB 0
1702 #define SAMD21_SERCOM_INTFLAG_SSL 3
1704 #define SAMD21_SERCOM_INTENCLR_DRE 0
1705 #define SAMD21_SERCOM_INTENCLR_TXC 1
1706 #define SAMD21_SERCOM_INTENCLR_RXC 2
1707 #define SAMD21_SERCOM_INTENCLR_RXS 3
1708 #define SAMD21_SERCOM_INTENCLR_CTSIC 4
1709 #define SAMD21_SERCOM_INTENCLR_RXBRK 5
1710 #define SAMD21_SERCOM_INTENCLR_ERROR 7
1712 #define SAMD21_SERCOM_STATUS_PERR 0
1713 #define SAMD21_SERCOM_STATUS_FERR 1
1714 #define SAMD21_SERCOM_STATUS_BUFOVF 2
1715 #define SAMD21_SERCOM_STATUS_CTS 3
1716 #define SAMD21_SERCOM_STATUS_ISF 4
1717 #define SAMD21_SERCOM_STATUS_COLL 5
1718 #define SAMD21_SERCOM_STATUS_TXE 6
1720 #define SAMD21_SERCOM_SYNCBUSY_SWRST 0
1721 #define SAMD21_SERCOM_SYNCBUSY_ENABLE 1
1722 #define SAMD21_SERCOM_SYNCBUSY_CTRLB 2
1723 #define SAMD21_SERCOM_SYNCBUSY_SYSOP 2
1725 #define SAMD21_SERCOM_ADDR_ADDR 0
1726 #define SAMD21_SERCOM_ADDR_LENEN 13
1727 #define SAMD21_SERCOM_ADDR_HS 14
1728 #define SAMD21_SERCOM_ADDR_TENBITEN 15
1729 #define SAMD21_SERCOM_ADDR_LEN 16
1731 #define SAMD21_SERCOM_DBGCTRL_DBGSTOP 0
1733 #define SAMD21_SERCOM_FIFOSPACE_TXSPACE 0
1734 #define SAMD21_SERCOM_FIFOSPACE_TXSPACE_MASK 0x1f
1735 #define SAMD21_SERCOM_FIFOSPACE_RXSPACE 8
1736 #define SAMD21_SERCOM_FIFOSPACE_RXSPACE_MASK 0x1f
1738 #define SAMD21_SERCOM_FIFOPTR_CPUWRPTR 0
1739 #define SAMD21_SERCOM_FIFOPTR_CPUWRPTR_MASK 0xf
1740 #define SAMD21_SERCOM_FIFOPTR_CPURDPTR 8
1741 #define SAMD21_SERCOM_FIFOPTR_CPURDPTR_MASK 0xf
1743 /* The SYSTICK starts at 0xe000e010 */
1744 struct samd21_systick {
1751 extern struct samd21_systick samd21_systick;
1753 #define samd21_systick (*(struct samd21_systick *) 0xe000e010)
1755 #define SAMD21_SYSTICK_CSR_ENABLE 0
1756 #define SAMD21_SYSTICK_CSR_TICKINT 1
1757 #define SAMD21_SYSTICK_CSR_CLKSOURCE 2
1758 #define SAMD21_SYSTICK_CSR_CLKSOURCE_EXTERNAL 0
1759 #define SAMD21_SYSTICK_CSR_CLKSOURCE_HCLK_8 1
1760 #define SAMD21_SYSTICK_CSR_COUNTFLAG 16
1762 #define SAMD21_SYSTICK_PRI 15
1764 /* The NVIC starts at 0xe000e100, so add that to the offsets to find the absolute address */
1766 struct samd21_nvic {
1767 vuint32_t iser; /* 0x000 0xe000e100 Set Enable Register */
1769 uint8_t _unused020[0x080 - 0x004];
1771 vuint32_t icer; /* 0x080 0xe000e180 Clear Enable Register */
1773 uint8_t _unused0a0[0x100 - 0x084];
1775 vuint32_t ispr; /* 0x100 0xe000e200 Set Pending Register */
1777 uint8_t _unused120[0x180 - 0x104];
1779 vuint32_t icpr; /* 0x180 0xe000e280 Clear Pending Register */
1781 uint8_t _unused1a0[0x300 - 0x184];
1783 vuint32_t ipr[8]; /* 0x300 0xe000e400 Priority Register */
1786 extern struct samd21_nvic samd21_nvic;
1788 #define samd21_nvic (*(struct samd21_nvic *) 0xe000e100)
1790 #define SAMD21_NVIC_ISR_PM_POS 0
1791 #define SAMD21_NVIC_ISR_SYSCTRL_POS 1
1792 #define SAMD21_NVIC_ISR_WDT_POS 2
1793 #define SAMD21_NVIC_ISR_RTC_POS 3
1794 #define SAMD21_NVIC_ISR_EIC_POS 4
1795 #define SAMD21_NVIC_ISR_NVMCTRL_POS 5
1796 #define SAMD21_NVIC_ISR_DMAC_POS 6
1797 #define SAMD21_NVIC_ISR_USB_POS 7
1798 #define SAMD21_NVIC_ISR_EVSYS_POS 8
1799 #define SAMD21_NVIC_ISR_SERCOM0_POS 9
1800 #define SAMD21_NVIC_ISR_SERCOM1_POS 10
1801 #define SAMD21_NVIC_ISR_SERCOM2_POS 11
1802 #define SAMD21_NVIC_ISR_SERCOM3_POS 12
1803 #define SAMD21_NVIC_ISR_SERCOM4_POS 13
1804 #define SAMD21_NVIC_ISR_SERCOM5_POS 14
1805 #define SAMD21_NVIC_ISR_TCC0_POS 15
1806 #define SAMD21_NVIC_ISR_TCC1_POS 16
1807 #define SAMD21_NVIC_ISR_TCC2_POS 17
1808 #define SAMD21_NVIC_ISR_TC3_POS 18
1809 #define SAMD21_NVIC_ISR_TC4_POS 19
1810 #define SAMD21_NVIC_ISR_TC5_POS 20
1811 #define SAMD21_NVIC_ISR_TC6_POS 21
1812 #define SAMD21_NVIC_ISR_TC7_POS 22
1813 #define SAMD21_NVIC_ISR_ADC_POS 23
1814 #define SAMD21_NVIC_ISR_AC_POS 24
1815 #define SAMD21_NVIC_ISR_DAC_POS 25
1816 #define SAMD21_NVIC_ISR_PTC_POS 26
1817 #define SAMD21_NVIC_ISR_I2S_POS 27
1818 #define SAMD21_NVIC_ISR_AC1_POS 28
1819 #define SAMD21_NVIC_ISR_TCC3_POS 29
1821 #define IRQ_MASK(irq) (1 << (irq))
1822 #define IRQ_BOOL(v,irq) (((v) >> (irq)) & 1)
1825 samd21_nvic_set_enable(int irq) {
1826 samd21_nvic.iser = IRQ_MASK(irq);
1830 samd21_nvic_clear_enable(int irq) {
1831 samd21_nvic.icer = IRQ_MASK(irq);
1835 samd21_nvic_enabled(int irq) {
1836 return IRQ_BOOL(samd21_nvic.iser, irq);
1840 samd21_nvic_set_pending(int irq) {
1841 samd21_nvic.ispr = IRQ_MASK(irq);
1845 samd21_nvic_clear_pending(int irq) {
1846 samd21_nvic.icpr = IRQ_MASK(irq);
1850 samd21_nvic_pending(int irq) {
1851 return IRQ_BOOL(samd21_nvic.ispr, irq);
1854 #define IRQ_PRIO_REG(irq) ((irq) >> 2)
1855 #define IRQ_PRIO_BIT(irq) (((irq) & 3) << 3)
1856 #define IRQ_PRIO_MASK(irq) (0xffU << IRQ_PRIO_BIT(irq))
1859 samd21_nvic_set_priority(int irq, uint8_t prio) {
1860 int n = IRQ_PRIO_REG(irq);
1863 v = samd21_nvic.ipr[n];
1864 v &= ~IRQ_PRIO_MASK(irq);
1865 v |= (prio) << IRQ_PRIO_BIT(irq);
1866 samd21_nvic.ipr[n] = v;
1869 static inline uint8_t
1870 samd21_nvic_get_priority(int irq) {
1871 return (samd21_nvic.ipr[IRQ_PRIO_REG(irq)] >> IRQ_PRIO_BIT(irq)) & IRQ_PRIO_MASK(0);
1876 /* Cortex M0+ SCB */
1899 extern struct samd21_scb samd21_scb;
1901 #define samd21_scb (*(struct samd21_scb *) 0xe000ed00)
1903 #define SAMD21_SCB_AIRCR_VECTKEY 16
1904 #define SAMD21_SCB_AIRCR_VECTKEY_KEY 0x05fa
1905 #define SAMD21_SCB_AIRCR_PRIGROUP 8
1906 #define SAMD21_SCB_AIRCR_SYSRESETREQ 2
1907 #define SAMD21_SCB_AIRCR_VECTCLRACTIVE 1
1908 #define SAMD21_SCB_AIRCR_VECTRESET 0
1910 /* The NVM Calibration and auxiliary space starts at 0x00800000 */
1912 struct samd21_aux0 {
1916 extern struct samd21_aux0 samd21_aux0;
1918 #define samd21_aux0 (*(struct samd21_aux0 *) 0x00804000)
1920 #define SAMD21_AUX0_USERROW_BOOTPROT 0
1921 #define SAMD21_AUX0_USERROW_EEPROM 4
1922 #define SAMD21_AUX0_USERROW_BOD33_LEVEL 8
1923 #define SAMD21_AUX0_USERROW_BOD33_ENABLE 14
1924 #define SAMD21_AUX0_USERROW_BOD33_ACTION 15
1925 #define SAMD21_AUX0_USERROW_WDT_ENABLE 25
1926 #define SAMD21_AUX0_USERROW_WDT_ALWAYS_ON 26
1927 #define SAMD21_AUX0_USERROW_WDT_PERIOD 27
1928 #define SAMD21_AUX0_USERROW_WDT_WINDOW 31
1929 #define SAMD21_AUX0_USERROW_WDT_EWOFFSET 35
1930 #define SAMD21_AUX0_USERROW_WDT_WEN 39
1931 #define SAMD21_AUX0_USERROW_BOD33_HYST 40
1932 #define SAMD21_AUX0_USERROW_LOCK 48
1934 struct samd21_aux1 {
1935 vuint64_t reserved_00;
1936 vuint64_t device_config;
1938 vuint64_t reserved_10;
1939 vuint64_t reserved_18;
1941 vuint64_t calibration;
1942 vuint64_t reserved_28;
1945 extern struct samd21_aux1 samd21_aux1;
1947 #define samd21_aux1 (*(struct samd21_aux1 *) 0x00806000)
1949 #define SAMD21_AUX1_CALIBRATION_ADC_LINEARITY 27
1950 #define SAMD21_AUX1_CALIBRATION_ADC_LINEARITY_MASK 0xff
1951 #define SAMD21_AUX1_CALIBRATION_ADC_BIASCAL 35
1952 #define SAMD21_AUX1_CALIBRATION_ADC_BIASCAL_MASK 0x7
1953 #define SAMD21_AUX1_CALIBRATION_OSC32K_CAL 38
1954 #define SAMD21_AUX1_CALIBRATION_USB_TRANSN 45
1955 #define SAMD21_AUX1_CALIBRATION_USB_TRANSN_MASK 0x1f
1956 #define SAMD21_AUX1_CALIBRATION_USB_TRANSP 50
1957 #define SAMD21_AUX1_CALIBRATION_USB_TRANSP_MASK 0x1f
1958 #define SAMD21_AUX1_CALIBRATION_USB_TRIM 55
1959 #define SAMD21_AUX1_CALIBRATION_USB_TRIM_MASK 0x07
1960 #define SAMD21_AUX1_CALIBRATION_DFLL48M_COARSE_CAL 58
1961 #define SAMD21_AUX1_CALIBRATION_DFLL48M_COARSE_CAL_MASK 0x3f
1963 struct samd21_serial {
1964 vuint32_t reserved_00;
1965 vuint32_t reserved_04;
1966 vuint32_t reserved_08;
1969 vuint32_t reserved_10;
1970 vuint32_t reserved_14;
1971 vuint32_t reserved_18;
1972 vuint32_t reserved_1c;
1974 vuint32_t reserved_20;
1975 vuint32_t reserved_24;
1976 vuint32_t reserved_28;
1977 vuint32_t reserved_2c;
1979 vuint32_t reserved_30;
1980 vuint32_t reserved_34;
1981 vuint32_t reserved_38;
1982 vuint32_t reserved_3c;
1987 vuint32_t reserved_4c;
1990 extern struct samd21_serial samd21_serial;
1992 #define samd21_serial (*(struct samd21_serial *) 0x0080a000)
1995 samd21_gclk_wait_sync(void)
1997 while (samd21_gclk.status & (1 << SAMD21_GCLK_STATUS_SYNCBUSY))
2002 samd21_dfll_wait_sync(void)
2004 while ((samd21_sysctrl.pclksr & (1 << SAMD21_SYSCTRL_PCLKSR_DFLLRDY)) == 0)
2009 samd21_gclk_gendiv(uint32_t id, uint32_t div)
2013 samd21_gclk.gendiv = ((id << SAMD21_GCLK_GENDIV_ID) |
2014 (div << SAMD21_GCLK_GENDIV_DIV));
2015 samd21_gclk_wait_sync();
2019 samd21_gclk_genctrl(uint32_t src, uint32_t id)
2021 samd21_gclk.genctrl = ((id << SAMD21_GCLK_GENCTRL_ID) |
2022 (src << SAMD21_GCLK_GENCTRL_SRC) |
2023 (0 << SAMD21_GCLK_GENCTRL_OE) |
2024 (1 << SAMD21_GCLK_GENCTRL_GENEN));
2025 samd21_gclk_wait_sync();
2029 samd21_gclk_clkctrl(uint32_t gen, uint32_t id)
2031 samd21_gclk.clkctrl = (uint16_t) ((gen << SAMD21_GCLK_CLKCTRL_GEN) |
2032 (id << SAMD21_GCLK_CLKCTRL_ID) |
2033 (1U << SAMD21_GCLK_CLKCTRL_CLKEN));
2034 samd21_gclk_wait_sync();
2037 #define isr_decl(name) \
2038 void samd21_ ## name ## _isr(void)
2043 isr_decl(hardfault);
2044 isr_decl(memmanage);
2046 isr_decl(usagefault);
2051 isr_decl(pm); /* IRQ0 */
2084 #endif /* _SAMD21_H_ */