fix up oshpark zip generation for 4 layers

diff --git a/Makefile b/Makefile
index 30c597821c2c6608d414d71f59fe44e5eeb231ac..06575938e699a823c0b13fecce6caec569bbdfdd 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -51,19 +51,21 @@ usbrelay.xy:        usbrelay.pcb
 usbrelay.bottom.gbr:   usbrelay.pcb
        pcb -x gerber usbrelay.pcb
 
-zip:   usbrelay.bottom.gbr usbrelay.bottommask.gbr usbrelay.fab.gbr usbrelay.top.gbr usbrelay.topmask.gbr usbrelay.toppaste.gbr usbrelay.topsilk.gbr usbrelay.plated-drill.cnc usbrelay.xy  Makefile # usbrelay.xls
-       zip usbrelay.zip usbrelay.*.gbr usbrelay.*.cnc usbrelay.xy # usbrelay.xls
-
-oshpark: usbrelay.bottom.gbr usbrelay.bottommask.gbr usbrelay.top.gbr usbrelay.topmask.gbr usbrelay.topsilk.gbr usbrelay.plated-drill.cnc
-       mv usbrelay.bottom.gbr bottom\ layer.ger
-       mv usbrelay.bottommask.gbr bottom\ solder\ mask.ger
-       mv usbrelay.bottomsilk.gbr bottom\ silk\ screen.ger
-       mv usbrelay.outline.gbr board\ outline.ger
-       mv usbrelay.top.gbr top\ layer.ger
-       mv usbrelay.topmask.gbr top\ solder\ mask.ger
-       mv usbrelay.topsilk.gbr top\ silk\ screen.ger
-       mv usbrelay.plated-drill.cnc drills.xln
-       zip usbrelay-oshpark.zip *.ger *.xln
+zip:   $(PROJECT).bottom.gbr $(PROJECT).bottommask.gbr $(PROJECT).fab.gbr $(PROJECT).top.gbr $(PROJECT).topmask.gbr $(PROJECT).toppaste.gbr $(PROJECT).topsilk.gbr $(PROJECT).group2.gbr $(PROJECT).group3.gbr $(PROJECT).plated-drill.cnc $(PROJECT).xy  Makefile 
+       zip $(PROJECT).zip $(PROJECT).*.gbr $(PROJECT).*.cnc $(PROJECT).xy # $(PROJECT).xls
+
+oshpark: $(PROJECT).bottom.gbr $(PROJECT).bottommask.gbr $(PROJECT).top.gbr $(PROJECT).topmask.gbr $(PROJECT).topsilk.gbr $(PROJECT).plated-drill.cnc
+       mv $(PROJECT).bottom.gbr bottom\ layer.ger
+       mv $(PROJECT).bottommask.gbr bottom\ solder\ mask.ger
+       mv $(PROJECT).bottomsilk.gbr bottom\ silk\ screen.ger
+       mv $(PROJECT).outline.gbr board\ outline.ger
+       mv $(PROJECT).top.gbr top\ layer.ger
+       mv $(PROJECT).topmask.gbr top\ solder\ mask.ger
+       mv $(PROJECT).topsilk.gbr top\ silk\ screen.ger
+       mv $(PROJECT).plated-drill.cnc drills.xln
+       mv $(PROJECT).group2.gbr internal\ plane\ 1.ger
+       mv $(PROJECT).group3.gbr internal\ plane\ 2.ger
+       zip $(PROJECT)-oshpark.zip *.ger *.xln
 
 stencil:       usbrelay.bottom.gbr usbrelay.toppaste.gbr usbrelay.outline.gbr
        zip usbrelay-stencil.zip usbrelay.toppaste.gbr usbrelay.outline.gbr

diff --git a/usbrelay.pcb b/usbrelay.pcb
index 0b1d0df4b8f3185ad4d60c206bfe43f838dcbd69..1f69b2009c5d186e75ac204912e9a7af623fe5be 100644 (file)
--- a/usbrelay.pcb
+++ b/usbrelay.pcb
@@ -3,7 +3,7 @@
 # To read pcb files, the pcb version (or the git source date) must be >= the file version
 FileVersion[20091103]
 
-PCB["TeleMega" 1500.00mil 1250.00mil]
+PCB["USBrelay" 1500.00mil 850.00mil]
 
 Grid[100.000000 0.0000 0.0000 0]
 PolyArea[200000000.000000]