changes due to keithp's design review .. LCD hole diameter and SMA

notch width both changed

diff --git a/teleterra.pcb b/teleterra.pcb
index a7fc5dd90e6d949bb2952da97804ad1ff3ff6dd9..87ac0e8d17ecdd5efa65c9bc8e4ec71dc189fc4f 100644 (file)
--- a/teleterra.pcb
+++ b/teleterra.pcb
@@ -1295,23 +1295,23 @@ Element["" "0402" "L1" "27nH" 330874 59000 -7625 -2760 0 100 ""]
 
 Element["" "NHD-C0216" "X2" "unknown" 167800 51700 -106358 43714 0 100 ""]
 (
-       Pin[47243 49802 4331 1200 4931 2165 "XRESET" "1" "square,edge2"]
-       Pin[41338 49802 4331 1200 4931 2165 "RS" "2" "edge2"]
-       Pin[35432 49802 4331 1200 4931 2165 "R/_W_" "3" "edge2,thermal(1X)"]
-       Pin[29527 49802 4331 1200 4931 2165 "E" "4" "edge2"]
-       Pin[23621 49802 4331 1200 4931 2165 "DB0" "5" "edge2"]
-       Pin[17716 49802 4331 1200 4931 2165 "DB1" "6" "edge2"]
-       Pin[11810 49802 4331 1200 4931 2165 "DB2" "7" "edge2"]
-       Pin[5905 49802 4331 1200 4931 2165 "DB3" "8" "edge2"]
-       Pin[0 49802 4331 1200 4931 2165 "DB4" "9" "edge2"]
-       Pin[-5906 49802 4331 1200 4931 2165 "DB5" "10" "edge2"]
-       Pin[-11811 49802 4331 1200 4931 2165 "DB6" "11" "edge2"]
-       Pin[-17717 49802 4331 1200 4931 2165 "DB7" "12" "edge2"]
-       Pin[-23622 49802 4331 1200 4931 2165 "VSS" "13" "edge2,thermal(1X)"]
-       Pin[-29528 49802 4331 1200 4931 2165 "VDD" "14" "edge2"]
-       Pin[-35433 49802 4331 1200 4931 2165 "VOUT" "15" "edge2"]
-       Pin[-41339 49802 4331 1200 4931 2165 "CAP1P" "16" "edge2"]
-       Pin[-47244 49802 4331 1200 4931 2165 "CAP1N" "17" "edge2"]
+       Pin[47243 49802 4961 1200 5561 2835 "XRESET" "1" "square,edge2"]
+       Pin[41338 49802 4961 1200 5561 2835 "RS" "2" "edge2"]
+       Pin[35432 49802 4961 1200 5561 2835 "R/_W_" "3" "edge2,thermal(1X)"]
+       Pin[29527 49802 4961 1200 5561 2835 "E" "4" "edge2"]
+       Pin[23621 49802 4961 1200 5561 2835 "DB0" "5" "edge2"]
+       Pin[17716 49802 4961 1200 5561 2835 "DB1" "6" "edge2"]
+       Pin[11810 49802 4961 1200 5561 2835 "DB2" "7" "edge2"]
+       Pin[5905 49802 4961 1200 5561 2835 "DB3" "8" "edge2"]
+       Pin[0 49802 4961 1200 5561 2835 "DB4" "9" "edge2"]
+       Pin[-5906 49802 4961 1200 5561 2835 "DB5" "10" "edge2"]
+       Pin[-11811 49802 4961 1200 5561 2835 "DB6" "11" "edge2"]
+       Pin[-17717 49802 4961 1200 5561 2835 "DB7" "12" "edge2"]
+       Pin[-23622 49802 4961 1200 5561 2835 "VSS" "13" "edge2,thermal(1X)"]
+       Pin[-29528 49802 4961 1200 5561 2835 "VDD" "14" "edge2"]
+       Pin[-35433 49802 4961 1200 5561 2835 "VOUT" "15" "edge2"]
+       Pin[-41339 49802 4961 1200 5561 2835 "CAP1P" "16" "edge2"]
+       Pin[-47244 49802 4961 1200 5561 2835 "CAP1N" "17" "edge2"]
        ElementLine [89960 14369 -89961 -41929 500]
        ElementLine [-89961 14369 89960 -41929 500]
        ElementLine [-89961 -41929 -89961 14369 500]
@@ -1708,9 +1708,9 @@ Layer(1 "top")
        Line[27550 0 342550 0 600 2000 "clearline,lock"]
        Line[27550 175200 342550 175200 600 2000 "clearline,lock"]
        Line[0 28550 0 146650 600 2000 "clearline,lock"]
-       Line[370100 60000 370100 146650 600 2000 "clearline,lock"]
-       Line[365100 60000 370100 60000 600 2000 "clearline,lock"]
-       Line[365100 28550 365100 60000 600 2000 "clearline,lock"]
+       Line[370100 70000 370100 146650 600 2000 "clearline,lock"]
+       Line[365100 70000 370100 70000 600 2000 "clearline,lock"]
+       Line[365100 28550 365100 70000 600 2000 "clearline,lock"]
        Line[27550 0 27550 12850 600 2000 "clearline,lock"]
        Line[342550 0 342550 12850 600 2000 "clearline,lock"]
        Line[27550 162350 27550 175200 600 2000 "clearline,lock"]
@@ -2091,9 +2091,9 @@ Layer(2 "bottom")
        Line[27550 0 342550 0 600 2000 "clearline,lock"]
        Line[27550 175200 342550 175200 600 2000 "clearline,lock"]
        Line[0 28550 0 146650 600 2000 "clearline,lock"]
-       Line[370100 60000 370100 146650 600 2000 "clearline,lock"]
-       Line[365100 60000 370100 60000 600 2000 "clearline,lock"]
-       Line[365100 28550 365100 60000 600 2000 "clearline,lock"]
+       Line[370100 70000 370100 146650 600 2000 "clearline,lock"]
+       Line[365100 70000 370100 70000 600 2000 "clearline,lock"]
+       Line[365100 28550 365100 70000 600 2000 "clearline,lock"]
        Line[27550 0 27550 12850 600 2000 "clearline,lock"]
        Line[342550 0 342550 12850 600 2000 "clearline,lock"]
        Line[27550 162350 27550 175200 600 2000 "clearline,lock"]
@@ -2181,9 +2181,9 @@ Layer(3 "outline")
        Line[27550 0 342550 0 1000 2000 "lock"]
        Line[27550 175200 342550 175200 1000 2000 "lock"]
        Line[0 28550 0 146650 1000 2000 "lock"]
-       Line[370100 60000 370100 146650 1000 2000 "lock"]
-       Line[365100 60000 370100 60000 1000 2000 "lock"]
-       Line[365100 28550 365100 60000 1000 2000 "lock"]
+       Line[370100 70000 370100 146650 1000 2000 "lock"]
+       Line[365100 70000 370100 70000 1000 2000 "lock"]
+       Line[365100 28550 365100 70000 1000 2000 "lock"]
        Line[27550 0 27550 12850 1000 2000 "lock"]
        Line[342550 0 342550 12850 1000 2000 "lock"]
        Line[27550 162350 27550 175200 1000 2000 "lock"]