switch USB footprint to one without projection, pull board length in

add voltage divider for sampling v_pyro

diff --git a/telepyro.pcb b/telepyro.pcb
index 04d7e9e10a75a5bb55f8c87e486fc50f93710317..b2e2bd1dbda59f20dcf30cb858601c44bbee182e 100644 (file)
--- a/telepyro.pcb
+++ b/telepyro.pcb
@@ -1,12 +1,12 @@
 # release: pcb 20100929
-# date:    Thu Mar 10 09:50:00 2011
+# date:    Tue Apr 19 02:18:20 2011
 # user:    bdale (Bdale Garbee,KB0G)
 # host:    rover
 
 # To read pcb files, the pcb version (or the git source date) must be >= the file version
 FileVersion[20100606]
 
-PCB["TelePyro" 282500 110000]
+PCB["TelePyro" 275000 110000]
 
 Grid[100.000000 0 0 0]
 Cursor[0 0 0.000000]
@@ -1237,11 +1237,11 @@ Element["" "0402" "C103" "47pF" 246026 54300 -18876 -4250 0 100 ""]
 
        )
 
-Element["" "ZX62-B-5PA" "J101" "USB" 256143 55000 17989 5461 1 100 ""]
+Element["" "ZX62-B-5PA" "J101" "USB" 256143 55000 5461 -17989 2 100 ""]
 (
-       Pad[787 0 4528 0 1575 984 2362 "DATA+" "3" "square"]
-       Pad[787 2558 4528 2558 1575 984 2362 "DATA-" "2" "square"]
-       Pad[787 -2559 4528 -2559 1575 984 2362 "ID" "4" "square"]
+       Pad[787 0 4528 0 1575 984 2362 "D+" "3" "square"]
+       Pad[787 2558 4528 2558 1575 984 2362 "D-" "2" "square"]
+       Pad[787 -2559 4528 -2559 1575 984 2362 "HS" "4" "square"]
        Pad[787 5117 4528 5117 1575 984 2362 "VBUS" "1" "square"]
        Pad[787 -5118 4528 -5118 1575 984 2362 "GND" "5" "square"]
        Pad[3150 -13189 3150 -11220 6299 984 7087 "tab1" "G" "square"]
@@ -1250,12 +1250,12 @@ Element["" "ZX62-B-5PA" "J101" "USB" 256143 55000 17989 5461 1 100 ""]
        Pad[13189 4723 13189 4723 7480 984 8268 "tab4" "G" "square,edge2"]
        Pad[12992 -15748 13386 -15748 7087 984 7874 "tab5" "G" "square,edge2"]
        Pad[12992 15747 13386 15747 7087 984 7874 "tab6" "G" "square,edge2"]
-       ElementLine [18898 -19291 18898 -15551 1000]
-       ElementLine [18898 15550 18898 19290 1000]
-       ElementLine [24016 -15551 24016 15550 1000]
+       ElementLine [0 15550 18898 15550 1000]
+       ElementLine [0 -15551 18898 -15551 1000]
        ElementLine [0 -15551 0 15550 1000]
-       ElementLine [0 -15551 24016 -15551 1000]
-       ElementLine [0 15550 24016 15550 1000]
+       ElementLine [18898 -15551 18898 15550 1000]
+       ElementLine [18898 15550 18898 19290 1000]
+       ElementLine [18898 -19291 18898 -15551 1000]
 
        )
 
@@ -1608,6 +1608,20 @@ Element["onsolder" "282834-8" "J4" "unknown" 135906 1205 0 0 2 100 "auto"]
        ElementLine [-81811 25591 -81811 0 600]
        ElementLine [-81811 0 0 0 600]
 
+       )
+
+Element["" "0402" "R40" "100k" 65774 91800 2776 -8650 0 100 ""]
+(
+       Pad[-1574 -393 -1574 393 1968 2000 2568 "1" "1" "square"]
+       Pad[1574 -393 1574 393 1968 2000 2568 "2" "2" "square"]
+
+       )
+
+Element["" "0402" "R41" "27k" 59474 91800 8524 -3450 0 100 ""]
+(
+       Pad[-1574 -393 -1574 393 1968 2000 2568 "1" "1" "square"]
+       Pad[1574 -393 1574 393 1968 2000 2568 "2" "2" "square"]
+
        )
 Layer(1 "top")
 (
@@ -2024,11 +2038,11 @@ Layer(1 "top")
        Line[125346 75100 117100 75100 1000 2000 "clearline"]
        Line[117100 75100 97000 95200 1000 2000 "clearline"]
        Line[62500 33700 62600 33600 1000 2000 "clearline"]
-       Line[83800 95100 59500 57300 1000 2000 "clearline"]
+       Line[87600 95100 59500 57300 1000 2000 "clearline"]
        Line[59500 57300 59500 34800 1000 2000 "clearline"]
        Line[59500 34800 60600 33700 1000 2000 "clearline"]
        Line[60600 33700 62500 33700 1000 2000 "clearline"]
-       Line[83800 95100 97200 95100 1000 2000 "clearline"]
+       Line[87600 95100 97200 95100 1000 2000 "clearline"]
        Line[87000 79500 87000 84900 1000 2000 "clearline"]
        Line[69452 61952 87000 79500 1000 2000 "clearline"]
        Line[134402 53446 134402 54702 1000 2000 "clearline"]
@@ -2136,6 +2150,17 @@ Layer(1 "top")
        Line[202100 73900 204600 71400 1000 2000 "clearline"]
        Line[204600 71400 207800 71400 1000 2000 "clearline"]
        Line[207800 71400 210800 68400 1000 2000 "clearline"]
+       Line[61048 91800 64200 91800 1000 2000 "clearline"]
+       Line[57900 91800 57900 96074 1000 2000 "clearline"]
+       Line[57900 96074 58826 97000 1000 2000 "clearline"]
+       Line[64200 91800 64200 89500 1000 2000 "clearline"]
+       Line[64200 89500 64800 88900 1000 2000 "clearline"]
+       Line[64800 88900 77000 88900 1000 2000 "clearline"]
+       Line[77000 88900 85900 97800 1000 2000 "clearline"]
+       Line[85900 97800 97000 97800 1000 2000 "clearline"]
+       Line[97000 97800 114000 80800 1000 2000 "clearline"]
+       Line[114000 80800 124748 80800 1000 2000 "clearline"]
+       Line[124748 80800 125346 81398 1000 2000 "clearline"]
 )
 Layer(2 "bottom")
 (
@@ -2540,6 +2565,7 @@ NetList()
                Connect("R30-1")
                Connect("R31-1")
                Connect("R32-1")
+               Connect("R41-1")
                Connect("U1-2")
                Connect("U2-12")
                Connect("U2-17")
@@ -2757,6 +2783,12 @@ NetList()
                Connect("J101-3")
                Connect("R103-1")
        )
+       Net("v_batt" "(unknown)")
+       (
+               Connect("R40-1")
+               Connect("R41-2")
+               Connect("U3-41")
+       )
        Net("v_lipo" "(unknown)")
        (
                Connect("J2-8")
@@ -2785,6 +2817,7 @@ NetList()
                Connect("J5-8")
                Connect("J6-2")
                Connect("J7-3")
+               Connect("R40-2")
        )
        Net("v_usb" "(unknown)")
        (

diff --git a/telepyro.sch b/telepyro.sch
index c591b1d3d57800b36ea0e9719c32ebc2a9e3a432..41804e48bcb7a143985b91ae3a9fc41b7f3be355 100644 (file)
--- a/telepyro.sch
+++ b/telepyro.sch
@@ -1,4 +1,4 @@
-v 20100214 2
+v 20110115 2
 C 40000 40000 0 0 0 EMBEDDEDtitle-D-bdale.sym
 [
 B 40000 40000 34000 22000 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
@@ -2106,8 +2106,6 @@ footprint=0402
 }
 C 61300 51100 1 0 0 gnd-1.sym
 C 62200 51100 1 0 0 gnd-1.sym
-T 40000 40000 8 10 1 1 0 0 1
-value=47pF
 N 61400 53000 61400 52300 4
 N 62300 52600 62300 52300 4
 C 62600 55600 1 0 1 conn-3.sym
@@ -2184,3 +2182,53 @@ vendor_part_number=TC2185-3.3VCCT-ND
 T 62700 43300 5 10 1 1 0 0 1
 value=TC2185-3.3
 }
+N 70500 51400 72000 51400 4
+{
+T 71500 51500 5 10 1 1 0 0 1
+netname=v_batt
+}
+C 55200 50300 1 90 0 resistor.sym
+{
+T 54800 50600 5 10 0 0 90 0 1
+device=RESISTOR
+T 55600 51000 5 10 1 1 180 0 1
+refdes=R40
+T 55300 50500 5 10 1 1 0 0 1
+value=100k
+T 55200 50300 5 10 0 0 0 0 1
+footprint=0402
+T 55200 50300 5 10 0 0 0 0 1
+vendor=digikey
+T 55200 50300 5 10 0 0 0 0 1
+vendor_part_number=RMCF1/16S100KFRCT-ND
+T 55200 50300 5 10 0 0 0 0 1
+loadstatus=smt
+}
+C 55200 49400 1 90 0 resistor.sym
+{
+T 54800 49700 5 10 0 0 90 0 1
+device=RESISTOR
+T 55600 50100 5 10 1 1 180 0 1
+refdes=R41
+T 55300 49600 5 10 1 1 0 0 1
+value=27k
+T 55200 49400 5 10 0 0 0 0 1
+footprint=0402
+T 55200 49400 5 10 0 0 0 0 1
+vendor=digikey
+T 55200 49400 5 10 0 0 0 0 1
+vendor_part_number=311-27KJRCT-ND
+T 55200 49400 5 10 0 0 0 0 1
+loadstatus=smt
+}
+C 55000 49100 1 0 0 gnd-1.sym
+N 55100 50300 57000 50300 4
+{
+T 56500 50400 5 10 1 1 0 0 1
+netname=v_batt
+}
+N 55100 51200 53500 51200 4
+{
+T 53500 51300 5 10 1 1 0 0 1
+netname=v_pyro
+}