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added mounting holes, cleaned up back-side silk (product name, etc)
author
Bdale Garbee
<bdale@gag.com>
Wed, 3 Nov 2010 19:04:03 +0000
(13:04 -0600)
committer
Bdale Garbee
<bdale@gag.com>
Wed, 3 Nov 2010 19:04:03 +0000
(13:04 -0600)
telenano.pcb
patch
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telenano.sch
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diff --git
a/telenano.pcb
b/telenano.pcb
index d7a7080d7f5678033547435ef9393e6d5dad983b..e6d64d2e46bcb3800f107ae388e0ccf30d178365 100644
(file)
--- a/
telenano.pcb
+++ b/
telenano.pcb
@@
-1,5
+1,5
@@
# release: pcb 20091103
# release: pcb 20091103
-# date: Wed Nov 3 1
2:31:26
2010
+# date: Wed Nov 3 1
3:03:57
2010
# user: bdale (Bdale Garbee,KB0G)
# host: rover
# user: bdale (Bdale Garbee,KB0G)
# host: rover
@@
-798,12
+798,12
@@
Symbol('~' 12)
SymbolLine(20 35 25 30 8)
)
Via[96000 35000 3600 0 4200 2000 "" "thermal(0X,1X)"]
SymbolLine(20 35 25 30 8)
)
Via[96000 35000 3600 0 4200 2000 "" "thermal(0X,1X)"]
-Via[96000 15000 3600 2000 4200 2000 "" "thermal(0X,1
X
)"]
+Via[96000 15000 3600 2000 4200 2000 "" "thermal(0X,1
S
)"]
Via[31600 1600 2800 2000 0 1500 "" "thermal(1t)"]
Via[59400 40100 3600 2000 0 2000 "" "thermal(1X)"]
Via[9400 43500 3600 2000 0 2000 "" "thermal(1X)"]
Via[31600 1600 2800 2000 0 1500 "" "thermal(1t)"]
Via[59400 40100 3600 2000 0 2000 "" "thermal(1X)"]
Via[9400 43500 3600 2000 0 2000 "" "thermal(1X)"]
-Via[7
5900 11600 3600 2000 0 20
00 "" "thermal(1X)"]
-Via[
78200 35100 3600 2000 0 20
00 "" "thermal(1X)"]
+Via[7
2800 11600 2800 2000 0 15
00 "" "thermal(1X)"]
+Via[
64800 2000 2800 2000 0 15
00 "" "thermal(1X)"]
Via[77800 47600 3600 2000 0 2000 "" "thermal(1X)"]
Via[24900 43200 2800 2000 0 1500 "" ""]
Via[30600 26100 2800 2000 0 1500 "" ""]
Via[77800 47600 3600 2000 0 2000 "" "thermal(1X)"]
Via[24900 43200 2800 2000 0 1500 "" ""]
Via[30600 26100 2800 2000 0 1500 "" ""]
@@
-819,10
+819,6
@@
Via[60100 11200 2800 2000 0 1500 "" "thermal(1X)"]
Via[26100 4400 2800 2000 0 1500 "" ""]
Via[13700 36400 2800 2000 0 1500 "" ""]
Via[6500 26600 2800 2000 0 1500 "" ""]
Via[26100 4400 2800 2000 0 1500 "" ""]
Via[13700 36400 2800 2000 0 1500 "" ""]
Via[6500 26600 2800 2000 0 1500 "" ""]
-Via[68200 11600 2800 2000 0 1500 "" "thermal(1X)"]
-Via[64800 2000 2800 2000 0 1500 "" "thermal(1X)"]
-Via[96000 2500 3600 0 4200 2000 "" "thermal(0X,1X)"]
-Via[96000 47500 3600 2000 4200 2000 "" ""]
Element["" "0402" "C9" "0.1uF" 66207 16326 -3068 -8116 0 100 ""]
(
Element["" "0402" "C9" "0.1uF" 66207 16326 -3068 -8116 0 100 ""]
(
@@
-1215,6
+1211,20
@@
Element["onsolder" "MOT1317" "U6" "MP3H6115A" 44980 25056 13011 2761 3 100 "auto
ElementLine [-14566 -14567 -14566 14566 1000]
ElementArc [-12499 -16693 500 500 0 360 1000]
ElementLine [-14566 -14567 -14566 14566 1000]
ElementArc [-12499 -16693 500 500 0 360 1000]
+ )
+
+Element["" "hole-M2.5" "H1" "unknown" 90000 10000 -2352 -3100 0 100 ""]
+(
+ Pin[0 0 11000 2000 11000 9800 "pin1" "1" "usetherm,thermal(1S)"]
+ ElementArc [0 0 8000 8000 0 360 1000]
+
+ )
+
+Element["" "hole-M2.5" "H2" "unknown" 90000 40000 -4900 -1000 0 100 ""]
+(
+ Pin[0 0 11000 2000 11000 9800 "pin1" "1" "usetherm,thermal(1S)"]
+ ElementArc [0 0 8000 8000 0 360 1000]
+
)
Layer(1 "top")
(
)
Layer(1 "top")
(
@@
-1243,7
+1253,7
@@
Layer(1 "top")
Line[4000 47300 2700 47300 1000 2000 "clearline"]
Line[9400 43500 17462 43500 2500 2000 "clearline"]
Line[35386 1600 35800 2014 1000 2000 "clearline"]
Line[4000 47300 2700 47300 1000 2000 "clearline"]
Line[9400 43500 17462 43500 2500 2000 "clearline"]
Line[35386 1600 35800 2014 1000 2000 "clearline"]
- Line[
78200 35100 81100 351
00 1000 2000 "clearline"]
+ Line[
58000 2000 64800 20
00 1000 2000 "clearline"]
Line[2700 47300 1500 46100 1000 2000 "clearline"]
Line[77374 17874 77400 17848 1000 2000 "clearline"]
Line[77374 20807 77374 17874 1000 2000 "clearline"]
Line[2700 47300 1500 46100 1000 2000 "clearline"]
Line[77374 17874 77400 17848 1000 2000 "clearline"]
Line[77374 20807 77374 17874 1000 2000 "clearline"]
@@
-1252,8
+1262,8
@@
Layer(1 "top")
Line[71034 27800 70748 27514 1000 2000 ""]
Line[74100 27800 71034 27800 1000 2000 ""]
Line[70748 27514 70748 24438 1000 2000 ""]
Line[71034 27800 70748 27514 1000 2000 ""]
Line[74100 27800 71034 27800 1000 2000 ""]
Line[70748 27514 70748 24438 1000 2000 ""]
- Line[
78200 33286 77000 320
86 1000 2000 "clearline"]
- Line[
78200 35100 78200 33286
1000 2000 "clearline"]
+ Line[
61014 5148 61014 82
86 1000 2000 "clearline"]
+ Line[
61014 8286 61000 8300
1000 2000 "clearline"]
Line[69300 19700 69300 18181 1000 2000 "clearline"]
Line[31600 1600 35386 1600 1000 2000 "clearline"]
Line[5600 43400 9300 43400 2500 2000 "clearline"]
Line[69300 19700 69300 18181 1000 2000 "clearline"]
Line[31600 1600 35386 1600 1000 2000 "clearline"]
Line[5600 43400 9300 43400 2500 2000 "clearline"]
@@
-1411,17
+1421,20
@@
Layer(1 "top")
Line[6500 26600 6500 13100 2500 2000 "clearline"]
Line[6500 13100 15200 4400 2500 2000 "clearline"]
Line[15200 4400 26100 4400 2500 2000 "clearline"]
Line[6500 26600 6500 13100 2500 2000 "clearline"]
Line[6500 13100 15200 4400 2500 2000 "clearline"]
Line[15200 4400 26100 4400 2500 2000 "clearline"]
- Line[
66600 14752 66600 13200
1000 2000 "clearline"]
- Line[
66600 13200 68200 116
00 1000 2000 "clearline"]
- Line[
69607 14726 69607 13007
1000 2000 "clearline"]
- Line[
69607 13007 68200 116
00 1000 2000 "clearline"]
+ Line[
77414 32500 77000 32086
1000 2000 "clearline"]
+ Line[
80200 32500 77414 325
00 1000 2000 "clearline"]
+ Line[
90000 40000 87700 40000
1000 2000 "clearline"]
+ Line[
87700 40000 80200 325
00 1000 2000 "clearline"]
Line[74200 14700 74200 13300 1000 2000 "clearline"]
Line[74200 13300 75900 11600 1000 2000 "clearline"]
Line[77400 14700 77400 13100 1000 2000 "clearline"]
Line[77400 13100 75900 11600 1000 2000 "clearline"]
Line[74200 14700 74200 13300 1000 2000 "clearline"]
Line[74200 13300 75900 11600 1000 2000 "clearline"]
Line[77400 14700 77400 13100 1000 2000 "clearline"]
Line[77400 13100 75900 11600 1000 2000 "clearline"]
- Line[61014 5148 61014 8286 1000 2000 "clearline"]
- Line[61014 8286 61000 8300 1000 2000 "clearline"]
- Line[58000 2000 64800 2000 1000 2000 "clearline"]
+ Line[69607 14726 69226 14726 1000 2000 "clearline"]
+ Line[81000 11600 67800 11700 2500 2000 "clearline"]
+ Line[66600 14752 66600 12700 1000 2000 "clearline"]
+ Line[66600 12700 67600 11700 1000 2000 "clearline"]
+ Line[70393 14726 70393 14007 1000 2000 "clearline"]
+ Line[70393 14007 72800 11600 1000 2000 "clearline"]
Polygon("")
(
[99100 49500] [80100 49500] [80100 32000] [99100 32000]
Polygon("")
(
[99100 49500] [80100 49500] [80100 32000] [99100 32000]
@@
-1469,10
+1482,9
@@
Layer(2 "bottom")
)
Layer(3 "silk")
(
)
Layer(3 "silk")
(
- Text[72466 49000 3 100 "License TAPR OHL" "auto"]
- Text[92693 46768 3 100 "TeleNano v0.1" "auto"]
- Text[86536 44393 3 100 "Copyright 2010" "auto"]
- Text[79227 46529 3 100 "by Bdale Garbee" "auto"]
+ Text[77215 35422 3 100 "(c) 2010" "auto"]
+ Text[84093 42768 3 100 "TeleNano v0.1" "auto"]
+ Text[71400 43400 3 100 "Bdale Garbee" "auto"]
)
Layer(4 "silk")
(
)
Layer(4 "silk")
(
@@
-1534,6
+1546,8
@@
NetList()
Connect("C37-1")
Connect("D2-3")
Connect("D2-4")
Connect("C37-1")
Connect("D2-3")
Connect("D2-4")
+ Connect("H1-1")
+ Connect("H2-1")
Connect("J6-1")
Connect("J8-2")
Connect("R4-1")
Connect("J6-1")
Connect("J8-2")
Connect("R4-1")
diff --git
a/telenano.sch
b/telenano.sch
index 58119a9b9066eeb7e60739e40bb3f9b72927c162..c898f79781ce888601c0fa1fc7c5fd54df044db4 100644
(file)
--- a/
telenano.sch
+++ b/
telenano.sch
@@
-1,26
+1,26
@@
v 20100214 2
C 40000 40000 0 0 0 EMBEDDEDtitle-C-bdale.sym
[
v 20100214 2
C 40000 40000 0 0 0 EMBEDDEDtitle-C-bdale.sym
[
-T
31100 408
00 5 10 0 0 0 0 1
+T
43200 411
00 5 10 0 0 0 0 1
graphical=1
graphical=1
-B 40000 40000 22000 17000 15 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
-L 54400 41400 62000 41400 15 0 0 0 -1 -1
+T 54500 40400 15 8 1 0 0 0 1
+FILE:
+T 59500 40400 15 8 1 0 0 0 1
+REVISION:
+T 57400 40400 15 8 1 0 0 0 1
+PAGE
+T 58200 40400 15 8 1 0 0 0 1
+OF
+B 54400 40000 7600 2700 15 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
+L 54400 40600 62000 40600 15 0 0 0 -1 -1
+T 54500 40100 15 10 1 0 0 0 1
+Project URL:
T 54900 40800 9 10 1 0 0 0 2
Copyright 2010 by Bdale Garbee <bdale@gag.com>
Licensed under the TAPR Open Hardware License, http://www.tapr.org/OHL
T 54900 40800 9 10 1 0 0 0 2
Copyright 2010 by Bdale Garbee <bdale@gag.com>
Licensed under the TAPR Open Hardware License, http://www.tapr.org/OHL
-T 54500 40100 15 10 1 0 0 0 1
-Project URL:
-L 54400 40600 62000 40600 15 0 0 0 -1 -1
-B 54400 40000 7600 2700 15 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
-T 58200 40400 15 8 1 0 0 0 1
-OF
-T 57400 40400 15 8 1 0 0 0 1
-PAGE
-T 59500 40400 15 8 1 0 0 0 1
-REVISION:
-T 54500 40400 15 8 1 0 0 0 1
-FILE:
-T 43200 41100 5 10 0 0 0 0 1
+L 54400 41400 62000 41400 15 0 0 0 -1 -1
+B 40000 40000 22000 17000 15 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
+T 31100 40800 5 10 0 0 0 0 1
graphical=1
]
C 43600 54400 1 0 0 gnd-1.sym
graphical=1
]
C 43600 54400 1 0 0 gnd-1.sym
@@
-906,3
+906,23
@@
vendor_part_number=160-1452-1-ND
}
N 45900 50300 45900 49900 4
C 46200 49200 1 0 0 gnd-1.sym
}
N 45900 50300 45900 49900 4
C 46200 49200 1 0 0 gnd-1.sym
+C 58900 46700 1 0 0 hole_plated.sym
+{
+T 59000 48400 5 10 0 0 0 0 1
+device=HOLE_PLATED
+T 59000 47200 5 10 1 1 0 0 1
+refdes=H1
+T 58900 46700 5 10 0 0 0 0 1
+footprint=hole-M2.5
+}
+C 58900 45900 1 0 0 hole_plated.sym
+{
+T 59000 47600 5 10 0 0 0 0 1
+device=HOLE_PLATED
+T 59000 46400 5 10 1 1 0 0 1
+refdes=H2
+T 58900 45900 5 10 0 0 0 0 1
+footprint=hole-M2.5
+}
+C 59400 45800 1 0 0 gnd-1.sym
+N 59500 46900 59500 46100 4